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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=future -ppc-asm-full-reg-names \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \6; RUN: -mcpu=future -ppc-asm-full-reg-names \7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8 9define void @test_wacc_copy(ptr noundef %vdmrp, ptr noundef %vpp, <16 x i8> noundef %vc, ptr noundef %resp) #0 {10; CHECK-LABEL: test_wacc_copy:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: std r31, -8(r1)13; CHECK-NEXT: std r30, -16(r1)14; CHECK-NEXT: mr r30, r115; CHECK-NEXT: clrldi r0, r1, 5716; CHECK-NEXT: subfic r0, r0, -38417; CHECK-NEXT: stdux r1, r1, r018; CHECK-NEXT: .cfi_def_cfa_register r3019; CHECK-NEXT: .cfi_offset r31, -820; CHECK-NEXT: .cfi_offset r30, -1621; CHECK-NEXT: mr r31, r122; CHECK-NEXT: std r3, 360(r31)23; CHECK-NEXT: std r4, 352(r31)24; CHECK-NEXT: stxv v2, 336(r31)25; CHECK-NEXT: std r7, 328(r31)26; CHECK-NEXT: ld r3, 360(r31)27; CHECK-NEXT: lxvp vsp34, 0(r3)28; CHECK-NEXT: lxvp vsp36, 32(r3)29; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 130; CHECK-NEXT: lxvp vsp34, 64(r3)31; CHECK-NEXT: lxvp vsp36, 96(r3)32; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 033; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 034; CHECK-NEXT: stxvp vsp34, 224(r31)35; CHECK-NEXT: stxvp vsp36, 192(r31)36; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 137; CHECK-NEXT: stxvp vsp34, 160(r31)38; CHECK-NEXT: stxvp vsp36, 128(r31)39; CHECK-NEXT: ld r3, 352(r31)40; CHECK-NEXT: lxv v2, 16(r3)41; CHECK-NEXT: lxv v3, 0(r3)42; CHECK-NEXT: stxv v2, 112(r31)43; CHECK-NEXT: stxv v3, 96(r31)44; CHECK-NEXT: lxv v2, 112(r31)45; CHECK-NEXT: lxv v3, 96(r31)46; CHECK-NEXT: lxv vs0, 336(r31)47; CHECK-NEXT: dmxvi8gerx4 dmr0, vsp34, vs048; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 049; CHECK-NEXT: stxvp vsp34, 224(r31)50; CHECK-NEXT: stxvp vsp36, 192(r31)51; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 152; CHECK-NEXT: stxvp vsp34, 160(r31)53; CHECK-NEXT: stxvp vsp36, 128(r31)54; CHECK-NEXT: lxvp vsp34, 128(r31)55; CHECK-NEXT: lxvp vsp36, 160(r31)56; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 157; CHECK-NEXT: lxvp vsp34, 192(r31)58; CHECK-NEXT: lxvp vsp36, 224(r31)59; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 060; CHECK-NEXT: ld r3, 328(r31)61; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 062; CHECK-NEXT: stxvp vsp34, 96(r3)63; CHECK-NEXT: stxvp vsp36, 64(r3)64; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 165; CHECK-NEXT: stxvp vsp34, 32(r3)66; CHECK-NEXT: stxvp vsp36, 0(r3)67; CHECK-NEXT: mr r1, r3068; CHECK-NEXT: ld r31, -8(r1)69; CHECK-NEXT: ld r30, -16(r1)70; CHECK-NEXT: blr71;72; CHECK-BE-LABEL: test_wacc_copy:73; CHECK-BE: # %bb.0: # %entry74; CHECK-BE-NEXT: std r31, -8(r1)75; CHECK-BE-NEXT: std r30, -16(r1)76; CHECK-BE-NEXT: mr r30, r177; CHECK-BE-NEXT: clrldi r0, r1, 5778; CHECK-BE-NEXT: subfic r0, r0, -38479; CHECK-BE-NEXT: stdux r1, r1, r080; CHECK-BE-NEXT: mr r31, r181; CHECK-BE-NEXT: std r3, 360(r31)82; CHECK-BE-NEXT: std r4, 352(r31)83; CHECK-BE-NEXT: stxv v2, 336(r31)84; CHECK-BE-NEXT: std r5, 328(r31)85; CHECK-BE-NEXT: ld r3, 360(r31)86; CHECK-BE-NEXT: lxvp vsp34, 96(r3)87; CHECK-BE-NEXT: lxvp vsp36, 64(r3)88; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 189; CHECK-BE-NEXT: lxvp vsp34, 32(r3)90; CHECK-BE-NEXT: lxvp vsp36, 0(r3)91; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 092; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 193; CHECK-BE-NEXT: stxvp vsp36, 224(r31)94; CHECK-BE-NEXT: stxvp vsp34, 192(r31)95; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 096; CHECK-BE-NEXT: stxvp vsp36, 160(r31)97; CHECK-BE-NEXT: stxvp vsp34, 128(r31)98; CHECK-BE-NEXT: ld r3, 352(r31)99; CHECK-BE-NEXT: lxv v2, 0(r3)100; CHECK-BE-NEXT: lxv v3, 16(r3)101; CHECK-BE-NEXT: stxv v3, 112(r31)102; CHECK-BE-NEXT: stxv v2, 96(r31)103; CHECK-BE-NEXT: lxv v2, 96(r31)104; CHECK-BE-NEXT: lxv v3, 112(r31)105; CHECK-BE-NEXT: lxv vs0, 336(r31)106; CHECK-BE-NEXT: dmxvi8gerx4 dmr0, vsp34, vs0107; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1108; CHECK-BE-NEXT: stxvp vsp36, 224(r31)109; CHECK-BE-NEXT: stxvp vsp34, 192(r31)110; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0111; CHECK-BE-NEXT: stxvp vsp36, 160(r31)112; CHECK-BE-NEXT: stxvp vsp34, 128(r31)113; CHECK-BE-NEXT: lxvp vsp34, 224(r31)114; CHECK-BE-NEXT: lxvp vsp36, 192(r31)115; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1116; CHECK-BE-NEXT: lxvp vsp34, 160(r31)117; CHECK-BE-NEXT: lxvp vsp36, 128(r31)118; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0119; CHECK-BE-NEXT: ld r3, 328(r31)120; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1121; CHECK-BE-NEXT: stxvp vsp36, 96(r3)122; CHECK-BE-NEXT: stxvp vsp34, 64(r3)123; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0124; CHECK-BE-NEXT: stxvp vsp36, 32(r3)125; CHECK-BE-NEXT: stxvp vsp34, 0(r3)126; CHECK-BE-NEXT: mr r1, r30127; CHECK-BE-NEXT: ld r31, -8(r1)128; CHECK-BE-NEXT: ld r30, -16(r1)129; CHECK-BE-NEXT: blr130entry:131 %vdmrp.addr = alloca ptr, align 8132 %vpp.addr = alloca ptr, align 8133 %vc.addr = alloca <16 x i8>, align 16134 %resp.addr = alloca ptr, align 8135 %vdmr = alloca <1024 x i1>, align 128136 %vp = alloca <256 x i1>, align 32137 store ptr %vdmrp, ptr %vdmrp.addr, align 8138 store ptr %vpp, ptr %vpp.addr, align 8139 store <16 x i8> %vc, ptr %vc.addr, align 16140 store ptr %resp, ptr %resp.addr, align 8141 %0 = load ptr, ptr %vdmrp.addr, align 8142 %1 = load <1024 x i1>, ptr %0, align 128143 store <1024 x i1> %1, ptr %vdmr, align 128144 %2 = load ptr, ptr %vpp.addr, align 8145 %3 = load <256 x i1>, ptr %2, align 32146 store <256 x i1> %3, ptr %vp, align 32147 %4 = load <256 x i1>, ptr %vp, align 32148 %5 = load <16 x i8>, ptr %vc.addr, align 16149 %6 = call <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1> %4, <16 x i8> %5)150 store <1024 x i1> %6, ptr %vdmr, align 128151 %7 = load <1024 x i1>, ptr %vdmr, align 128152 %8 = load ptr, ptr %resp.addr, align 8153 store <1024 x i1> %7, ptr %8, align 128154 ret void155}156 157define void @foo(ptr noundef readonly captures(none) %p1, ptr noundef readonly captures(none) %p2, ptr noundef writeonly captures(none) initializes((0, 128)) %res1, ptr noundef writeonly captures(none) initializes((0, 128)) %res2) local_unnamed_addr #0 {158; CHECK-LABEL: foo:159; CHECK: # %bb.0: # %entry160; CHECK-NEXT: dmsetdmrz dmr0161; CHECK-NEXT: lxvp vsp34, 0(r3)162; CHECK-NEXT: lxvp vsp36, 32(r3)163; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1164; CHECK-NEXT: lxvp vsp34, 64(r3)165; CHECK-NEXT: lxvp vsp36, 96(r3)166; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0167; CHECK-NEXT: dmmr dmr2, dmr0168; CHECK-NEXT: dmxor dmr2, dmr1169; CHECK-NEXT: lxvp vsp34, 0(r4)170; CHECK-NEXT: lxvp vsp36, 32(r4)171; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1172; CHECK-NEXT: lxvp vsp34, 64(r4)173; CHECK-NEXT: lxvp vsp36, 96(r4)174; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0175; CHECK-NEXT: dmxor dmr0, dmr1176; CHECK-NEXT: dmmr dmr1, dmr2177; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0178; CHECK-NEXT: stxvp vsp34, 96(r5)179; CHECK-NEXT: stxvp vsp36, 64(r5)180; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1181; CHECK-NEXT: stxvp vsp34, 32(r5)182; CHECK-NEXT: stxvp vsp36, 0(r5)183; CHECK-NEXT: dmmr dmr0, dmr0184; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0185; CHECK-NEXT: stxvp vsp34, 96(r6)186; CHECK-NEXT: stxvp vsp36, 64(r6)187; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1188; CHECK-NEXT: stxvp vsp34, 32(r6)189; CHECK-NEXT: stxvp vsp36, 0(r6)190; CHECK-NEXT: blr191;192; CHECK-BE-LABEL: foo:193; CHECK-BE: # %bb.0: # %entry194; CHECK-BE-NEXT: dmsetdmrz dmr0195; CHECK-BE-NEXT: lxvp vsp34, 96(r3)196; CHECK-BE-NEXT: lxvp vsp36, 64(r3)197; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1198; CHECK-BE-NEXT: lxvp vsp34, 32(r3)199; CHECK-BE-NEXT: lxvp vsp36, 0(r3)200; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0201; CHECK-BE-NEXT: dmmr dmr2, dmr0202; CHECK-BE-NEXT: dmxor dmr2, dmr1203; CHECK-BE-NEXT: lxvp vsp34, 96(r4)204; CHECK-BE-NEXT: lxvp vsp36, 64(r4)205; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1206; CHECK-BE-NEXT: lxvp vsp34, 32(r4)207; CHECK-BE-NEXT: lxvp vsp36, 0(r4)208; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0209; CHECK-BE-NEXT: dmxor dmr0, dmr1210; CHECK-BE-NEXT: dmmr dmr1, dmr2211; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi1, 1212; CHECK-BE-NEXT: stxvp vsp36, 96(r5)213; CHECK-BE-NEXT: stxvp vsp34, 64(r5)214; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0215; CHECK-BE-NEXT: stxvp vsp36, 32(r5)216; CHECK-BE-NEXT: stxvp vsp34, 0(r5)217; CHECK-BE-NEXT: dmmr dmr0, dmr0218; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1219; CHECK-BE-NEXT: stxvp vsp36, 96(r6)220; CHECK-BE-NEXT: stxvp vsp34, 64(r6)221; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0222; CHECK-BE-NEXT: stxvp vsp36, 32(r6)223; CHECK-BE-NEXT: stxvp vsp34, 0(r6)224; CHECK-BE-NEXT: blr225entry:226 %0 = tail call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()227 %1 = load <1024 x i1>, ptr %p1, align 128228 %2 = tail call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %0, <1024 x i1> %1)229 %3 = load <1024 x i1>, ptr %p2, align 128230 %4 = tail call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %0, <1024 x i1> %3)231 %5 = tail call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %2)232 store <1024 x i1> %5, ptr %res1, align 128233 %6 = tail call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %4)234 store <1024 x i1> %6, ptr %res2, align 128235 ret void236}237 238declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()239declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>)240declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>)241declare <1024 x i1> @llvm.ppc.mma.dmxvi8gerx4(<256 x i1>, <16 x i8>)242 243attributes #0 = { noinline nounwind optnone uwtable "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="future" "target-features"="+64bit,+allow-unaligned-fp-access,+altivec,+bpermd,+cmpb,+crbits,+crypto,+direct-move,+extdiv,+fast-MFLR,+fcpsgn,+fpcvt,+fprnd,+fpu,+fre,+fres,+frsqrte,+frsqrtes,+fsqrt,+fuse-add-logical,+fuse-arith-add,+fuse-logical,+fuse-logical-add,+fuse-sha3,+fuse-store,+fusion,+hard-float,+icbt,+isa-future-instructions,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+isel,+ldbrx,+lfiwax,+mfocrf,+mma,+paired-vector-memops,+partword-atomics,+pcrelative-memops,+popcntd,+power10-vector,+power8-altivec,+power8-vector,+power9-altivec,+power9-vector,+ppc-postra-sched,+ppc-prera-sched,+predictable-select-expensive,+prefix-instrs,+quadword-atomics,+recipprec,+stfiwx,+two-const-nr,+vsx" }244 245 246