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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=future -ppc-asm-full-reg-names \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix \6; RUN: -mcpu=future -ppc-asm-full-reg-names \7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8 9define void @tdmrz(ptr nocapture readonly %vp1, ptr nocapture %resp) {10; CHECK-LABEL: tdmrz:11; CHECK: # %bb.0: # %entry12; CHECK-NEXT: dmsetdmrz dmr013; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 014; CHECK-NEXT: stxvp vsp34, 96(r4)15; CHECK-NEXT: stxvp vsp36, 64(r4)16; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 117; CHECK-NEXT: stxvp vsp34, 32(r4)18; CHECK-NEXT: stxvp vsp36, 0(r4)19; CHECK-NEXT: blr20;21; CHECK-BE-LABEL: tdmrz:22; CHECK-BE: # %bb.0: # %entry23; CHECK-BE-NEXT: dmsetdmrz dmr024; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 125; CHECK-BE-NEXT: stxvp vsp36, 96(r4)26; CHECK-BE-NEXT: stxvp vsp34, 64(r4)27; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 028; CHECK-BE-NEXT: stxvp vsp36, 32(r4)29; CHECK-BE-NEXT: stxvp vsp34, 0(r4)30; CHECK-BE-NEXT: blr31entry:32 %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()33 store <1024 x i1> %z, ptr %resp, align 3234 ret void35}36 37define void @tdmmr(ptr nocapture readonly %vp1, ptr nocapture %resp) {38; CHECK-LABEL: tdmmr:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: lxvp vsp34, 0(r3)41; CHECK-NEXT: lxvp vsp36, 32(r3)42; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 143; CHECK-NEXT: lxvp vsp34, 64(r3)44; CHECK-NEXT: lxvp vsp36, 96(r3)45; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 046; CHECK-NEXT: dmmr dmr0, dmr047; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 048; CHECK-NEXT: stxvp vsp34, 96(r4)49; CHECK-NEXT: stxvp vsp36, 64(r4)50; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 151; CHECK-NEXT: stxvp vsp34, 32(r4)52; CHECK-NEXT: stxvp vsp36, 0(r4)53; CHECK-NEXT: blr54;55; CHECK-BE-LABEL: tdmmr:56; CHECK-BE: # %bb.0: # %entry57; CHECK-BE-NEXT: lxvp vsp34, 96(r3)58; CHECK-BE-NEXT: lxvp vsp36, 64(r3)59; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 160; CHECK-BE-NEXT: lxvp vsp34, 32(r3)61; CHECK-BE-NEXT: lxvp vsp36, 0(r3)62; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 063; CHECK-BE-NEXT: dmmr dmr0, dmr064; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 165; CHECK-BE-NEXT: stxvp vsp36, 96(r4)66; CHECK-BE-NEXT: stxvp vsp34, 64(r4)67; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 068; CHECK-BE-NEXT: stxvp vsp36, 32(r4)69; CHECK-BE-NEXT: stxvp vsp34, 0(r4)70; CHECK-BE-NEXT: blr71entry:72 %l = load <1024 x i1>, ptr %vp1, align 3273 %c = call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> %l)74 store <1024 x i1> %c, ptr %resp, align 3275 ret void76}77 78define void @tdmxor(ptr nocapture readonly %vp1, ptr %vp2, ptr nocapture %resp) {79; CHECK-LABEL: tdmxor:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: lxvp vsp34, 0(r3)82; CHECK-NEXT: lxvp vsp36, 32(r3)83; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 184; CHECK-NEXT: lxvp vsp34, 64(r3)85; CHECK-NEXT: lxvp vsp36, 96(r3)86; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 087; CHECK-NEXT: lxvp vsp34, 0(r4)88; CHECK-NEXT: lxvp vsp36, 32(r4)89; CHECK-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 190; CHECK-NEXT: lxvp vsp34, 64(r4)91; CHECK-NEXT: lxvp vsp36, 96(r4)92; CHECK-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 093; CHECK-NEXT: dmxor dmr0, dmr194; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 095; CHECK-NEXT: stxvp vsp34, 96(r5)96; CHECK-NEXT: stxvp vsp36, 64(r5)97; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 198; CHECK-NEXT: stxvp vsp34, 32(r5)99; CHECK-NEXT: stxvp vsp36, 0(r5)100; CHECK-NEXT: blr101;102; CHECK-BE-LABEL: tdmxor:103; CHECK-BE: # %bb.0: # %entry104; CHECK-BE-NEXT: lxvp vsp34, 96(r3)105; CHECK-BE-NEXT: lxvp vsp36, 64(r3)106; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1107; CHECK-BE-NEXT: lxvp vsp34, 32(r3)108; CHECK-BE-NEXT: lxvp vsp36, 0(r3)109; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0110; CHECK-BE-NEXT: lxvp vsp34, 96(r4)111; CHECK-BE-NEXT: lxvp vsp36, 64(r4)112; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi1, vsp36, vsp34, 1113; CHECK-BE-NEXT: lxvp vsp34, 32(r4)114; CHECK-BE-NEXT: lxvp vsp36, 0(r4)115; CHECK-BE-NEXT: dmxxinstdmr512 wacc1, vsp36, vsp34, 0116; CHECK-BE-NEXT: dmxor dmr0, dmr1117; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1118; CHECK-BE-NEXT: stxvp vsp36, 96(r5)119; CHECK-BE-NEXT: stxvp vsp34, 64(r5)120; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0121; CHECK-BE-NEXT: stxvp vsp36, 32(r5)122; CHECK-BE-NEXT: stxvp vsp34, 0(r5)123; CHECK-BE-NEXT: blr124entry:125 %l = load <1024 x i1>, ptr %vp1, align 32126 %r = load <1024 x i1>, ptr %vp2, align 32127 %x = call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> %l, <1024 x i1> %r)128 store <1024 x i1> %x, ptr %resp, align 32129 ret void130}131 132define void @text512(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {133; CHECK-LABEL: text512:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: dmsetdmrz dmr0136; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0137; CHECK-NEXT: stxv v2, 16(r4)138; CHECK-NEXT: stxv v3, 0(r4)139; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1140; CHECK-NEXT: stxv v2, 16(r6)141; CHECK-NEXT: stxv v3, 0(r6)142; CHECK-NEXT: blr143;144; CHECK-BE-LABEL: text512:145; CHECK-BE: # %bb.0: # %entry146; CHECK-BE-NEXT: dmsetdmrz dmr0147; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0148; CHECK-BE-NEXT: stxv v3, 16(r4)149; CHECK-BE-NEXT: stxv v2, 0(r4)150; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1151; CHECK-BE-NEXT: stxv v3, 16(r6)152; CHECK-BE-NEXT: stxv v2, 0(r6)153; CHECK-BE-NEXT: blr154entry:155 %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()156 %x = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 0)157 %p = extractvalue { <256 x i1>, <256 x i1 > } %x, 0158 store <256 x i1> %p, ptr %rp1, align 16159 %y = call { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1> %z, i32 1)160 %q = extractvalue { <256 x i1>, <256 x i1 > } %y, 0161 store <256 x i1> %q, ptr %rp3, align 16162 ret void163}164 165define void @text256(ptr %vp1, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {166; CHECK-LABEL: text256:167; CHECK: # %bb.0: # %entry168; CHECK-NEXT: dmsetdmrz dmr0169; CHECK-NEXT: dmxxextfdmr256 vsp34, dmr0, 0170; CHECK-NEXT: stxv v2, 16(r4)171; CHECK-NEXT: stxv v3, 0(r4)172; CHECK-NEXT: dmxxextfdmr256 vsp34, dmr0, 1173; CHECK-NEXT: stxv v2, 16(r5)174; CHECK-NEXT: stxv v3, 0(r5)175; CHECK-NEXT: dmxxextfdmr256 vsp34, dmr0, 2176; CHECK-NEXT: stxv v2, 16(r6)177; CHECK-NEXT: stxv v3, 0(r6)178; CHECK-NEXT: dmxxextfdmr256 vsp34, dmr0, 3179; CHECK-NEXT: stxv v2, 16(r7)180; CHECK-NEXT: stxv v3, 0(r7)181; CHECK-NEXT: blr182;183; CHECK-BE-LABEL: text256:184; CHECK-BE: # %bb.0: # %entry185; CHECK-BE-NEXT: dmsetdmrz dmr0186; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmr0, 0187; CHECK-BE-NEXT: stxv v3, 16(r4)188; CHECK-BE-NEXT: stxv v2, 0(r4)189; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmr0, 1190; CHECK-BE-NEXT: stxv v3, 16(r5)191; CHECK-BE-NEXT: stxv v2, 0(r5)192; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmr0, 2193; CHECK-BE-NEXT: stxv v3, 16(r6)194; CHECK-BE-NEXT: stxv v2, 0(r6)195; CHECK-BE-NEXT: dmxxextfdmr256 vsp34, dmr0, 3196; CHECK-BE-NEXT: stxv v3, 16(r7)197; CHECK-BE-NEXT: stxv v2, 0(r7)198; CHECK-BE-NEXT: blr199entry:200 %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()201 %x = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 0)202 store <256 x i1> %x, ptr %rp1, align 16203 %q = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 1)204 store <256 x i1> %q, ptr %rp2, align 16205 %w = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 2)206 store <256 x i1> %w, ptr %rp3, align 16207 %y = call <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1> %z, i32 3)208 store <256 x i1> %y, ptr %rp4, align 16209 ret void210}211 212define void @tins512(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2) {213; CHECK-LABEL: tins512:214; CHECK: # %bb.0: # %entry215; CHECK-NEXT: lxv v2, 16(r3)216; CHECK-NEXT: lxv v3, 0(r3)217; CHECK-NEXT: lxv v4, 16(r4)218; CHECK-NEXT: lxv v5, 0(r4)219; CHECK-NEXT: dmsetdmrz dmr0220; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0221; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0222; CHECK-NEXT: stxvp vsp34, 96(r7)223; CHECK-NEXT: stxvp vsp36, 64(r7)224; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1225; CHECK-NEXT: stxvp vsp34, 32(r7)226; CHECK-NEXT: stxvp vsp36, 0(r7)227; CHECK-NEXT: lxv v2, 16(r5)228; CHECK-NEXT: lxv v4, 16(r6)229; CHECK-NEXT: lxv v3, 0(r5)230; CHECK-NEXT: lxv v5, 0(r6)231; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1232; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0233; CHECK-NEXT: stxvp vsp34, 96(r8)234; CHECK-NEXT: stxvp vsp36, 64(r8)235; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1236; CHECK-NEXT: stxvp vsp34, 32(r8)237; CHECK-NEXT: stxvp vsp36, 0(r8)238; CHECK-NEXT: blr239;240; CHECK-BE-LABEL: tins512:241; CHECK-BE: # %bb.0: # %entry242; CHECK-BE-NEXT: lxv v2, 0(r3)243; CHECK-BE-NEXT: lxv v3, 16(r3)244; CHECK-BE-NEXT: lxv v4, 0(r4)245; CHECK-BE-NEXT: lxv v5, 16(r4)246; CHECK-BE-NEXT: dmsetdmrz dmr0247; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0248; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1249; CHECK-BE-NEXT: stxvp vsp36, 96(r7)250; CHECK-BE-NEXT: stxvp vsp34, 64(r7)251; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0252; CHECK-BE-NEXT: stxvp vsp36, 32(r7)253; CHECK-BE-NEXT: stxvp vsp34, 0(r7)254; CHECK-BE-NEXT: lxv v2, 0(r5)255; CHECK-BE-NEXT: lxv v4, 0(r6)256; CHECK-BE-NEXT: lxv v3, 16(r5)257; CHECK-BE-NEXT: lxv v5, 16(r6)258; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp36, 1259; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1260; CHECK-BE-NEXT: stxvp vsp36, 96(r8)261; CHECK-BE-NEXT: stxvp vsp34, 64(r8)262; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0263; CHECK-BE-NEXT: stxvp vsp36, 32(r8)264; CHECK-BE-NEXT: stxvp vsp34, 0(r8)265; CHECK-BE-NEXT: blr266entry:267 %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()268 %l1 = load <256 x i1>, ptr %vp1, align 16269 %r1 = load <256 x i1>, ptr %vp2, align 16270 %a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %z, <256 x i1> %l1, <256 x i1> %r1, i32 0)271 store <1024 x i1> %a, ptr %rp1, align 16272 %l2 = load <256 x i1>, ptr %vp3, align 16273 %r2 = load <256 x i1>, ptr %vp4, align 16274 %b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1> %a, <256 x i1> %l2, <256 x i1> %r2, i32 1)275 store <1024 x i1> %b, ptr %rp2, align 16276 ret void277}278 279define void @tins256(ptr %vp1, ptr %vp2, ptr %vp3, ptr %vp4, ptr %rp1, ptr %rp2, ptr %rp3, ptr %rp4) {280; CHECK-LABEL: tins256:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: lxv v2, 16(r3)283; CHECK-NEXT: lxv v3, 0(r3)284; CHECK-NEXT: dmsetdmrz dmr0285; CHECK-NEXT: dmxxinstdmr256 dmr0, vsp34, 0286; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0287; CHECK-NEXT: stxvp vsp34, 96(r7)288; CHECK-NEXT: stxvp vsp36, 64(r7)289; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1290; CHECK-NEXT: stxvp vsp34, 32(r7)291; CHECK-NEXT: stxvp vsp36, 0(r7)292; CHECK-NEXT: lxv v2, 16(r4)293; CHECK-NEXT: lxv v3, 0(r4)294; CHECK-NEXT: dmxxinstdmr256 dmr0, vsp34, 1295; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0296; CHECK-NEXT: stxvp vsp36, 96(r8)297; CHECK-NEXT: stxvp vsp32, 64(r8)298; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1299; CHECK-NEXT: stxvp vsp36, 32(r8)300; CHECK-NEXT: stxvp vsp32, 0(r8)301; CHECK-NEXT: dmxxinstdmr256 dmr0, vsp34, 2302; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0303; CHECK-NEXT: stxvp vsp36, 96(r9)304; CHECK-NEXT: stxvp vsp32, 64(r9)305; CHECK-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1306; CHECK-NEXT: stxvp vsp36, 32(r9)307; CHECK-NEXT: stxvp vsp32, 0(r9)308; CHECK-NEXT: dmxxinstdmr256 dmr0, vsp34, 3309; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0310; CHECK-NEXT: stxvp vsp34, 96(r10)311; CHECK-NEXT: stxvp vsp36, 64(r10)312; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1313; CHECK-NEXT: stxvp vsp34, 32(r10)314; CHECK-NEXT: stxvp vsp36, 0(r10)315; CHECK-NEXT: blr316;317; CHECK-BE-LABEL: tins256:318; CHECK-BE: # %bb.0: # %entry319; CHECK-BE-NEXT: lxv v2, 0(r3)320; CHECK-BE-NEXT: lxv v3, 16(r3)321; CHECK-BE-NEXT: dmsetdmrz dmr0322; CHECK-BE-NEXT: dmxxinstdmr256 dmr0, vsp34, 0323; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1324; CHECK-BE-NEXT: stxvp vsp36, 96(r7)325; CHECK-BE-NEXT: stxvp vsp34, 64(r7)326; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0327; CHECK-BE-NEXT: stxvp vsp36, 32(r7)328; CHECK-BE-NEXT: stxvp vsp34, 0(r7)329; CHECK-BE-NEXT: lxv v2, 0(r4)330; CHECK-BE-NEXT: lxv v3, 16(r4)331; CHECK-BE-NEXT: dmxxinstdmr256 dmr0, vsp34, 1332; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1333; CHECK-BE-NEXT: stxvp vsp32, 96(r8)334; CHECK-BE-NEXT: stxvp vsp36, 64(r8)335; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0336; CHECK-BE-NEXT: stxvp vsp32, 32(r8)337; CHECK-BE-NEXT: stxvp vsp36, 0(r8)338; CHECK-BE-NEXT: dmxxinstdmr256 dmr0, vsp34, 2339; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc_hi0, 1340; CHECK-BE-NEXT: stxvp vsp32, 96(r9)341; CHECK-BE-NEXT: stxvp vsp36, 64(r9)342; CHECK-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0343; CHECK-BE-NEXT: stxvp vsp32, 32(r9)344; CHECK-BE-NEXT: stxvp vsp36, 0(r9)345; CHECK-BE-NEXT: dmxxinstdmr256 dmr0, vsp34, 3346; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1347; CHECK-BE-NEXT: stxvp vsp36, 96(r10)348; CHECK-BE-NEXT: stxvp vsp34, 64(r10)349; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0350; CHECK-BE-NEXT: stxvp vsp36, 32(r10)351; CHECK-BE-NEXT: stxvp vsp34, 0(r10)352; CHECK-BE-NEXT: blr353entry:354 %z = call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()355 %l1 = load <256 x i1>, ptr %vp1, align 16356 %a = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %z, <256 x i1> %l1, i32 0)357 store <1024 x i1> %a, ptr %rp1, align 16358 %l2 = load <256 x i1>, ptr %vp2, align 16359 %b = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %a, <256 x i1> %l2, i32 1)360 store <1024 x i1> %b, ptr %rp2, align 16361 %l3 = load <256 x i1>, ptr %vp3, align 16362 %c = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %b, <256 x i1> %l2, i32 2)363 store <1024 x i1> %c, ptr %rp3, align 16364 %l4 = load <256 x i1>, ptr %vp4, align 16365 %d = call <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1> %c, <256 x i1> %l2, i32 3)366 store <1024 x i1> %d, ptr %rp4, align 16367 ret void368}369 370define void @tbuild(ptr %p1, ptr %p2, ptr %res1, ptr %res2, ptr %v) {371; CHECK-LABEL: tbuild:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: lxv v3, 0(r7)374; CHECK-NEXT: vmr v2, v3375; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp34, 1376; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0377; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0378; CHECK-NEXT: stxvp vsp34, 96(r6)379; CHECK-NEXT: stxvp vsp36, 64(r6)380; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1381; CHECK-NEXT: stxvp vsp34, 32(r6)382; CHECK-NEXT: stxvp vsp36, 0(r6)383; CHECK-NEXT: lxvp vsp34, 0(r3)384; CHECK-NEXT: lxvp vsp36, 32(r3)385; CHECK-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1386; CHECK-NEXT: lxvp vsp34, 64(r3)387; CHECK-NEXT: lxvp vsp36, 96(r3)388; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0389; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0390; CHECK-NEXT: stxvp vsp34, 96(r5)391; CHECK-NEXT: stxvp vsp36, 64(r5)392; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1393; CHECK-NEXT: stxvp vsp34, 32(r5)394; CHECK-NEXT: stxvp vsp36, 0(r5)395; CHECK-NEXT: blr396;397; CHECK-BE-LABEL: tbuild:398; CHECK-BE: # %bb.0: # %entry399; CHECK-BE-NEXT: lxv v3, 0(r7)400; CHECK-BE-NEXT: vmr v2, v3401; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp34, vsp34, 1402; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0403; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1404; CHECK-BE-NEXT: stxvp vsp36, 96(r6)405; CHECK-BE-NEXT: stxvp vsp34, 64(r6)406; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0407; CHECK-BE-NEXT: stxvp vsp36, 32(r6)408; CHECK-BE-NEXT: stxvp vsp34, 0(r6)409; CHECK-BE-NEXT: lxvp vsp34, 96(r3)410; CHECK-BE-NEXT: lxvp vsp36, 64(r3)411; CHECK-BE-NEXT: dmxxinstdmr512 wacc_hi0, vsp36, vsp34, 1412; CHECK-BE-NEXT: lxvp vsp34, 32(r3)413; CHECK-BE-NEXT: lxvp vsp36, 0(r3)414; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0415; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc_hi0, 1416; CHECK-BE-NEXT: stxvp vsp36, 96(r5)417; CHECK-BE-NEXT: stxvp vsp34, 64(r5)418; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0419; CHECK-BE-NEXT: stxvp vsp36, 32(r5)420; CHECK-BE-NEXT: stxvp vsp34, 0(r5)421; CHECK-BE-NEXT: blr422entry:423 %0 = load <16 x i8>, ptr %v, align 16424 %1 = tail call <1024 x i1> @llvm.ppc.mma.build.dmr(<16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0, <16 x i8> %0)425 store <1024 x i1> %1, ptr %res2, align 128426 %2 = load <1024 x i1>, ptr %p1, align 128427 tail call void @llvm.ppc.mma.disassemble.dmr(ptr %res1, <1024 x i1> %2)428 ret void429}430 431declare <1024 x i1> @llvm.ppc.mma.build.dmr(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)432declare void @llvm.ppc.mma.disassemble.dmr(ptr, <1024 x i1>)433declare <1024 x i1> @llvm.ppc.mma.dmsetdmrz()434declare <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1>)435declare <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1>, <1024 x i1>)436declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr512(<1024 x i1>, <256 x i1>, <256 x i1>, i32)437declare <1024 x i1> @llvm.ppc.mma.dmxxinstdmr256(<1024 x i1>, <256 x i1>, i32)438declare { <256 x i1>, <256 x i1> } @llvm.ppc.mma.dmxxextfdmr512(<1024 x i1>, i32)439declare <256 x i1> @llvm.ppc.mma.dmxxextfdmr256(<1024 x i1>, i32)440