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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \3; RUN: -relocation-model=pic -ppc-asm-full-reg-names -verify-machineinstrs \4; RUN: < %s | FileCheck %s5; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown -ppc-vsr-nums-as-vr \6; RUN: -ppc-asm-full-reg-names -verify-machineinstrs \7; RUN: < %s | FileCheck %s -check-prefix=CHECK-BE8 9; Vector extract DWord and convert to quad precision.10 11@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 1612@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 1613 14; Function Attrs: norecurse nounwind15define void @sdwVecConv2qp(ptr nocapture %a, <2 x i64> %b) {16; CHECK-LABEL: sdwVecConv2qp:17; CHECK: # %bb.0: # %entry18; CHECK-NEXT: xxspltd v2, v2, 119; CHECK-NEXT: xscvsdqp v2, v220; CHECK-NEXT: stxv v2, 0(r3)21; CHECK-NEXT: blr22 23; CHECK-BE-LABEL: sdwVecConv2qp:24; CHECK-BE: xscvsdqp v2, v225; CHECK-BE-NEXT: stxv v2, 0(r3)26; CHECK-BE-NEXT: blr27entry:28 %vecext = extractelement <2 x i64> %b, i32 029 %conv = sitofp i64 %vecext to fp12830 store fp128 %conv, ptr %a, align 1631 ret void32}33 34; Function Attrs: norecurse nounwind35define void @sdwVecConv2qp1(ptr nocapture %a, <2 x i64> %b) {36; CHECK-LABEL: sdwVecConv2qp1:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: xscvsdqp v2, v239; CHECK-NEXT: stxv v2, 0(r3)40; CHECK-NEXT: blr41 42; CHECK-BE-LABEL: sdwVecConv2qp1:43; CHECK-BE: # %bb.0: # %entry44; CHECK-BE-NEXT: xxspltd v2, v2, 145; CHECK-BE-NEXT: xscvsdqp v2, v246; CHECK-BE-NEXT: stxv v2, 0(r3)47; CHECK-BE-NEXT: blr48entry:49 %vecext = extractelement <2 x i64> %b, i32 150 %conv = sitofp i64 %vecext to fp12851 store fp128 %conv, ptr %a, align 1652 ret void53}54 55; Function Attrs: norecurse nounwind56define void @sdwVecConv2qp_02(ptr nocapture %a) {57; CHECK-LABEL: sdwVecConv2qp_02:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: addis r4, r2, .LC0@toc@ha60; CHECK-NEXT: ld r4, .LC0@toc@l(r4)61; CHECK-NEXT: lxsd v2, 0(r4)62; CHECK-NEXT: xscvsdqp v2, v263; CHECK-NEXT: stxv v2, 0(r3)64; CHECK-NEXT: blr65entry:66 %0 = load <2 x i64>, ptr @sdwVecMem, align 1667 %vecext = extractelement <2 x i64> %0, i32 068 %conv = sitofp i64 %vecext to fp12869 store fp128 %conv, ptr %a, align 1670 ret void71}72 73; Function Attrs: norecurse nounwind74define void @sdwVecConv2qp1_03(ptr nocapture %a, ptr nocapture readonly %b) {75; CHECK-LABEL: sdwVecConv2qp1_03:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: lxsd v2, 8(r4)78; CHECK-NEXT: xscvsdqp v2, v279; CHECK-NEXT: stxv v2, 0(r3)80; CHECK-NEXT: blr81entry:82 %0 = load <2 x i64>, ptr %b, align 1683 %vecext = extractelement <2 x i64> %0, i32 184 %conv = sitofp i64 %vecext to fp12885 store fp128 %conv, ptr %a, align 1686 ret void87}88 89; Function Attrs: norecurse nounwind90define void @udwVecConv2qp(ptr nocapture %a, <2 x i64> %b) {91; CHECK-LABEL: udwVecConv2qp:92; CHECK: # %bb.0: # %entry93; CHECK-NEXT: xxspltd v2, v2, 194; CHECK-NEXT: xscvudqp v2, v295; CHECK-NEXT: stxv v2, 0(r3)96; CHECK-NEXT: blr97 98; CHECK-BE-LABEL: udwVecConv2qp:99; CHECK-BE: # %bb.0: # %entry100; CHECK-BE-NEXT: xscvudqp v2, v2101; CHECK-BE-NEXT: stxv v2, 0(r3)102; CHECK-BE-NEXT: blr103entry:104 %vecext = extractelement <2 x i64> %b, i32 0105 %conv = uitofp i64 %vecext to fp128106 store fp128 %conv, ptr %a, align 16107 ret void108}109 110; Function Attrs: norecurse nounwind111define void @udwVecConv2qp1(ptr nocapture %a, <2 x i64> %b) {112; CHECK-LABEL: udwVecConv2qp1:113; CHECK: # %bb.0: # %entry114; CHECK-NEXT: xscvudqp v2, v2115; CHECK-NEXT: stxv v2, 0(r3)116; CHECK-NEXT: blr117 118; CHECK-BE-LABEL: udwVecConv2qp1:119; CHECK-BE: # %bb.0: # %entry120; CHECK-BE-NEXT: xxspltd v2, v2, 1121; CHECK-BE-NEXT: xscvudqp v2, v2122; CHECK-BE-NEXT: stxv v2, 0(r3)123; CHECK-BE-NEXT: blr124entry:125 %vecext = extractelement <2 x i64> %b, i32 1126 %conv = uitofp i64 %vecext to fp128127 store fp128 %conv, ptr %a, align 16128 ret void129}130 131; Function Attrs: norecurse nounwind132define void @udwVecConv2qp1_02(ptr nocapture %a) {133; CHECK-LABEL: udwVecConv2qp1_02:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: addis r4, r2, .LC1@toc@ha136; CHECK-NEXT: ld r4, .LC1@toc@l(r4)137; CHECK-NEXT: lxsd v2, 8(r4)138; CHECK-NEXT: xscvudqp v2, v2139; CHECK-NEXT: stxv v2, 0(r3)140; CHECK-NEXT: blr141entry:142 %0 = load <2 x i64>, ptr @udwVecMem, align 16143 %vecext = extractelement <2 x i64> %0, i32 1144 %conv = uitofp i64 %vecext to fp128145 store fp128 %conv, ptr %a, align 16146 ret void147}148 149; Function Attrs: norecurse nounwind150define void @udwVecConv2qp_03(ptr nocapture %a, ptr nocapture readonly %b) {151; CHECK-LABEL: udwVecConv2qp_03:152; CHECK: # %bb.0: # %entry153; CHECK-NEXT: lxsd v2, 0(r4)154; CHECK-NEXT: xscvudqp v2, v2155; CHECK-NEXT: stxv v2, 0(r3)156; CHECK-NEXT: blr157entry:158 %0 = load <2 x i64>, ptr %b, align 16159 %vecext = extractelement <2 x i64> %0, i32 0160 %conv = uitofp i64 %vecext to fp128161 store fp128 %conv, ptr %a, align 16162 ret void163}164 165; Vector extract Word and convert to quad precision.166 167; Function Attrs: norecurse nounwind168define void @swVecConv2qp(ptr nocapture %a, <4 x i32> %b) {169; CHECK-LABEL: swVecConv2qp:170; CHECK: # %bb.0: # %entry171; CHECK-NEXT: vspltw v2, v2, 3172; CHECK-NEXT: vextsw2d v2, v2173; CHECK-NEXT: xscvsdqp v2, v2174; CHECK-NEXT: stxv v2, 0(r3)175; CHECK-NEXT: blr176 177; CHECK-BE-LABEL: swVecConv2qp:178; CHECK-BE: vspltw v2, v2, 0179; CHECK-BE-NEXT: vextsw2d v2, v2180; CHECK-BE-NEXT: xscvsdqp v2, v2181; CHECK-BE-NEXT: stxv v2, 0(r3)182; CHECK-BE-NEXT: blr183entry:184 %vecext = extractelement <4 x i32> %b, i32 0185 %conv = sitofp i32 %vecext to fp128186 store fp128 %conv, ptr %a, align 16187 ret void188}189 190; Function Attrs: norecurse nounwind191define void @swVecConv2qp1(ptr nocapture %a, <4 x i32> %b) {192; CHECK-LABEL: swVecConv2qp1:193; CHECK: # %bb.0: # %entry194; CHECK-NEXT: vspltw v2, v2, 2195; CHECK-NEXT: vextsw2d v2, v2196; CHECK-NEXT: xscvsdqp v2, v2197; CHECK-NEXT: stxv v2, 0(r3)198; CHECK-NEXT: blr199 200; CHECK-BE-LABEL: swVecConv2qp1:201; CHECK-BE: vextsw2d v2, v2202; CHECK-BE-NEXT: xscvsdqp v2, v2203; CHECK-BE-NEXT: stxv v2, 0(r3)204; CHECK-BE-NEXT: blr205entry:206 %vecext = extractelement <4 x i32> %b, i32 1207 %conv = sitofp i32 %vecext to fp128208 store fp128 %conv, ptr %a, align 16209 ret void210}211 212; Function Attrs: norecurse nounwind213define void @swVecConv2qp2(ptr nocapture %a, <4 x i32> %b) {214; CHECK-LABEL: swVecConv2qp2:215; CHECK: # %bb.0: # %entry216; CHECK-NEXT: vextsw2d v2, v2217; CHECK-NEXT: xscvsdqp v2, v2218; CHECK-NEXT: stxv v2, 0(r3)219; CHECK-NEXT: blr220 221; CHECK-BE-LABEL: swVecConv2qp2:222; CHECK-BE: vspltw v2, v2, 2223; CHECK-BE-NEXT: vextsw2d v2, v2224; CHECK-BE-NEXT: xscvsdqp v2, v2225; CHECK-BE-NEXT: stxv v2, 0(r3)226; CHECK-BE-NEXT: blr227entry:228 %vecext = extractelement <4 x i32> %b, i32 2229 %conv = sitofp i32 %vecext to fp128230 store fp128 %conv, ptr %a, align 16231 ret void232}233 234; Function Attrs: norecurse nounwind235define void @swVecConv2qp3(ptr nocapture %a, <4 x i32> %b) {236; CHECK-LABEL: swVecConv2qp3:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: vspltw v2, v2, 0239; CHECK-NEXT: vextsw2d v2, v2240; CHECK-NEXT: xscvsdqp v2, v2241; CHECK-NEXT: stxv v2, 0(r3)242; CHECK-NEXT: blr243 244; CHECK-BE-LABEL: swVecConv2qp3:245; CHECK-BE: vspltw v2, v2, 3246; CHECK-BE-NEXT: vextsw2d v2, v2247; CHECK-BE-NEXT: xscvsdqp v2, v2248; CHECK-BE-NEXT: stxv v2, 0(r3)249; CHECK-BE-NEXT: blr250entry:251 %vecext = extractelement <4 x i32> %b, i32 3252 %conv = sitofp i32 %vecext to fp128253 store fp128 %conv, ptr %a, align 16254 ret void255}256 257; Function Attrs: norecurse nounwind258define void @uwVecConv2qp(ptr nocapture %a, <4 x i32> %b) {259; CHECK-LABEL: uwVecConv2qp:260; CHECK: # %bb.0: # %entry261; CHECK-NEXT: xxextractuw v2, v2, 12262; CHECK-NEXT: xscvudqp v2, v2263; CHECK-NEXT: stxv v2, 0(r3)264; CHECK-NEXT: blr265 266; CHECK-BE-LABEL: uwVecConv2qp:267; CHECK-BE: xxextractuw v2, v2, 0268; CHECK-BE-NEXT: xscvudqp v2, v2269; CHECK-BE-NEXT: stxv v2, 0(r3)270; CHECK-BE-NEXT: blr271entry:272 %vecext = extractelement <4 x i32> %b, i32 0273 %conv = uitofp i32 %vecext to fp128274 store fp128 %conv, ptr %a, align 16275 ret void276}277 278; Function Attrs: norecurse nounwind279define void @uwVecConv2qp1(ptr nocapture %a, <4 x i32> %b) {280; CHECK-LABEL: uwVecConv2qp1:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: xxextractuw v2, v2, 8283; CHECK-NEXT: xscvudqp v2, v2284; CHECK-NEXT: stxv v2, 0(r3)285; CHECK-NEXT: blr286 287; CHECK-BE-LABEL: uwVecConv2qp1:288; CHECK-BE: xxextractuw v2, v2, 4289; CHECK-BE-NEXT: xscvudqp v2, v2290; CHECK-BE-NEXT: stxv v2, 0(r3)291; CHECK-BE-NEXT: blr292entry:293 %vecext = extractelement <4 x i32> %b, i32 1294 %conv = uitofp i32 %vecext to fp128295 store fp128 %conv, ptr %a, align 16296 ret void297}298 299; Function Attrs: norecurse nounwind300define void @uwVecConv2qp2(ptr nocapture %a, <4 x i32> %b) {301; CHECK-LABEL: uwVecConv2qp2:302; CHECK: # %bb.0: # %entry303; CHECK-NEXT: xxextractuw v2, v2, 4304; CHECK-NEXT: xscvudqp v2, v2305; CHECK-NEXT: stxv v2, 0(r3)306; CHECK-NEXT: blr307 308; CHECK-BE-LABEL: uwVecConv2qp2:309; CHECK-BE: xxextractuw v2, v2, 8310; CHECK-BE-NEXT: xscvudqp v2, v2311; CHECK-BE-NEXT: stxv v2, 0(r3)312; CHECK-BE-NEXT: blr313entry:314 %vecext = extractelement <4 x i32> %b, i32 2315 %conv = uitofp i32 %vecext to fp128316 store fp128 %conv, ptr %a, align 16317 ret void318}319 320; Function Attrs: norecurse nounwind321define void @uwVecConv2qp3(ptr nocapture %a, <4 x i32> %b) {322; CHECK-LABEL: uwVecConv2qp3:323; CHECK: # %bb.0: # %entry324; CHECK-NEXT: xxextractuw v2, v2, 0325; CHECK-NEXT: xscvudqp v2, v2326; CHECK-NEXT: stxv v2, 0(r3)327; CHECK-NEXT: blr328 329; CHECK-BE-LABEL: uwVecConv2qp3:330; CHECK-BE: xxextractuw v2, v2, 12331; CHECK-BE-NEXT: xscvudqp v2, v2332; CHECK-BE-NEXT: stxv v2, 0(r3)333; CHECK-BE-NEXT: blr334entry:335 %vecext = extractelement <4 x i32> %b, i32 3336 %conv = uitofp i32 %vecext to fp128337 store fp128 %conv, ptr %a, align 16338 ret void339}340 341; Vector extract HWord and convert to quad precision.342 343; Function Attrs: norecurse nounwind344define void @shwVecConv2qp(ptr nocapture %a, <8 x i16> %b) {345; CHECK-LABEL: shwVecConv2qp:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: vextractuh v2, v2, 14348; CHECK-NEXT: vextsh2d v2, v2349; CHECK-NEXT: xscvsdqp v2, v2350; CHECK-NEXT: stxv v2, 0(r3)351; CHECK-NEXT: blr352;353; CHECK-BE-LABEL: shwVecConv2qp:354; CHECK-BE: # %bb.0: # %entry355; CHECK-BE-NEXT: vextractuh v2, v2, 0356; CHECK-BE-NEXT: vextsh2d v2, v2357; CHECK-BE-NEXT: xscvsdqp v2, v2358; CHECK-BE-NEXT: stxv v2, 0(r3)359; CHECK-BE-NEXT: blr360entry:361 %vecext = extractelement <8 x i16> %b, i32 0362 %conv = sitofp i16 %vecext to fp128363 store fp128 %conv, ptr %a, align 16364 ret void365}366 367; Function Attrs: norecurse nounwind368define void @shwVecConv2qp1(ptr nocapture %a, <8 x i16> %b) {369; CHECK-LABEL: shwVecConv2qp1:370; CHECK: # %bb.0: # %entry371; CHECK-NEXT: vextractuh v2, v2, 12372; CHECK-NEXT: vextsh2d v2, v2373; CHECK-NEXT: xscvsdqp v2, v2374; CHECK-NEXT: stxv v2, 0(r3)375; CHECK-NEXT: blr376;377; CHECK-BE-LABEL: shwVecConv2qp1:378; CHECK-BE: # %bb.0: # %entry379; CHECK-BE-NEXT: vextractuh v2, v2, 2380; CHECK-BE-NEXT: vextsh2d v2, v2381; CHECK-BE-NEXT: xscvsdqp v2, v2382; CHECK-BE-NEXT: stxv v2, 0(r3)383; CHECK-BE-NEXT: blr384entry:385 %vecext = extractelement <8 x i16> %b, i32 1386 %conv = sitofp i16 %vecext to fp128387 store fp128 %conv, ptr %a, align 16388 ret void389}390 391; Function Attrs: norecurse nounwind392define void @shwVecConv2qp2(ptr nocapture %a, <8 x i16> %b) {393; CHECK-LABEL: shwVecConv2qp2:394; CHECK: # %bb.0: # %entry395; CHECK-NEXT: vextractuh v2, v2, 10396; CHECK-NEXT: vextsh2d v2, v2397; CHECK-NEXT: xscvsdqp v2, v2398; CHECK-NEXT: stxv v2, 0(r3)399; CHECK-NEXT: blr400;401; CHECK-BE-LABEL: shwVecConv2qp2:402; CHECK-BE: # %bb.0: # %entry403; CHECK-BE-NEXT: vextractuh v2, v2, 4404; CHECK-BE-NEXT: vextsh2d v2, v2405; CHECK-BE-NEXT: xscvsdqp v2, v2406; CHECK-BE-NEXT: stxv v2, 0(r3)407; CHECK-BE-NEXT: blr408entry:409 %vecext = extractelement <8 x i16> %b, i32 2410 %conv = sitofp i16 %vecext to fp128411 store fp128 %conv, ptr %a, align 16412 ret void413}414 415; Function Attrs: norecurse nounwind416define void @shwVecConv2qp3(ptr nocapture %a, <8 x i16> %b) {417; CHECK-LABEL: shwVecConv2qp3:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: vextractuh v2, v2, 8420; CHECK-NEXT: vextsh2d v2, v2421; CHECK-NEXT: xscvsdqp v2, v2422; CHECK-NEXT: stxv v2, 0(r3)423; CHECK-NEXT: blr424;425; CHECK-BE-LABEL: shwVecConv2qp3:426; CHECK-BE: # %bb.0: # %entry427; CHECK-BE-NEXT: vextractuh v2, v2, 6428; CHECK-BE-NEXT: vextsh2d v2, v2429; CHECK-BE-NEXT: xscvsdqp v2, v2430; CHECK-BE-NEXT: stxv v2, 0(r3)431; CHECK-BE-NEXT: blr432entry:433 %vecext = extractelement <8 x i16> %b, i32 3434 %conv = sitofp i16 %vecext to fp128435 store fp128 %conv, ptr %a, align 16436 ret void437}438 439; Function Attrs: norecurse nounwind440define void @shwVecConv2qp4(ptr nocapture %a, <8 x i16> %b) {441; CHECK-LABEL: shwVecConv2qp4:442; CHECK: # %bb.0: # %entry443; CHECK-NEXT: vextractuh v2, v2, 6444; CHECK-NEXT: vextsh2d v2, v2445; CHECK-NEXT: xscvsdqp v2, v2446; CHECK-NEXT: stxv v2, 0(r3)447; CHECK-NEXT: blr448;449; CHECK-BE-LABEL: shwVecConv2qp4:450; CHECK-BE: # %bb.0: # %entry451; CHECK-BE-NEXT: vextractuh v2, v2, 8452; CHECK-BE-NEXT: vextsh2d v2, v2453; CHECK-BE-NEXT: xscvsdqp v2, v2454; CHECK-BE-NEXT: stxv v2, 0(r3)455; CHECK-BE-NEXT: blr456entry:457 %vecext = extractelement <8 x i16> %b, i32 4458 %conv = sitofp i16 %vecext to fp128459 store fp128 %conv, ptr %a, align 16460 ret void461}462 463; Function Attrs: norecurse nounwind464define void @shwVecConv2qp5(ptr nocapture %a, <8 x i16> %b) {465; CHECK-LABEL: shwVecConv2qp5:466; CHECK: # %bb.0: # %entry467; CHECK-NEXT: vextractuh v2, v2, 4468; CHECK-NEXT: vextsh2d v2, v2469; CHECK-NEXT: xscvsdqp v2, v2470; CHECK-NEXT: stxv v2, 0(r3)471; CHECK-NEXT: blr472;473; CHECK-BE-LABEL: shwVecConv2qp5:474; CHECK-BE: # %bb.0: # %entry475; CHECK-BE-NEXT: vextractuh v2, v2, 10476; CHECK-BE-NEXT: vextsh2d v2, v2477; CHECK-BE-NEXT: xscvsdqp v2, v2478; CHECK-BE-NEXT: stxv v2, 0(r3)479; CHECK-BE-NEXT: blr480entry:481 %vecext = extractelement <8 x i16> %b, i32 5482 %conv = sitofp i16 %vecext to fp128483 store fp128 %conv, ptr %a, align 16484 ret void485}486 487; Function Attrs: norecurse nounwind488define void @shwVecConv2qp6(ptr nocapture %a, <8 x i16> %b) {489; CHECK-LABEL: shwVecConv2qp6:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: vextractuh v2, v2, 2492; CHECK-NEXT: vextsh2d v2, v2493; CHECK-NEXT: xscvsdqp v2, v2494; CHECK-NEXT: stxv v2, 0(r3)495; CHECK-NEXT: blr496;497; CHECK-BE-LABEL: shwVecConv2qp6:498; CHECK-BE: # %bb.0: # %entry499; CHECK-BE-NEXT: vextractuh v2, v2, 12500; CHECK-BE-NEXT: vextsh2d v2, v2501; CHECK-BE-NEXT: xscvsdqp v2, v2502; CHECK-BE-NEXT: stxv v2, 0(r3)503; CHECK-BE-NEXT: blr504entry:505 %vecext = extractelement <8 x i16> %b, i32 6506 %conv = sitofp i16 %vecext to fp128507 store fp128 %conv, ptr %a, align 16508 ret void509}510 511; Function Attrs: norecurse nounwind512define void @shwVecConv2qp7(ptr nocapture %a, <8 x i16> %b) {513; CHECK-LABEL: shwVecConv2qp7:514; CHECK: # %bb.0: # %entry515; CHECK-NEXT: vextractuh v2, v2, 0516; CHECK-NEXT: vextsh2d v2, v2517; CHECK-NEXT: xscvsdqp v2, v2518; CHECK-NEXT: stxv v2, 0(r3)519; CHECK-NEXT: blr520;521; CHECK-BE-LABEL: shwVecConv2qp7:522; CHECK-BE: # %bb.0: # %entry523; CHECK-BE-NEXT: vextractuh v2, v2, 14524; CHECK-BE-NEXT: vextsh2d v2, v2525; CHECK-BE-NEXT: xscvsdqp v2, v2526; CHECK-BE-NEXT: stxv v2, 0(r3)527; CHECK-BE-NEXT: blr528entry:529 %vecext = extractelement <8 x i16> %b, i32 7530 %conv = sitofp i16 %vecext to fp128531 store fp128 %conv, ptr %a, align 16532 ret void533}534 535; Function Attrs: norecurse nounwind536define void @uhwVecConv2qp(ptr nocapture %a, <8 x i16> %b) {537; CHECK-LABEL: uhwVecConv2qp:538; CHECK: # %bb.0: # %entry539; CHECK-NEXT: vextractuh v2, v2, 14540; CHECK-NEXT: xscvudqp v2, v2541; CHECK-NEXT: stxv v2, 0(r3)542; CHECK-NEXT: blr543;544; CHECK-BE-LABEL: uhwVecConv2qp:545; CHECK-BE: # %bb.0: # %entry546; CHECK-BE-NEXT: vextractuh v2, v2, 0547; CHECK-BE-NEXT: xscvudqp v2, v2548; CHECK-BE-NEXT: stxv v2, 0(r3)549; CHECK-BE-NEXT: blr550entry:551 %vecext = extractelement <8 x i16> %b, i32 0552 %conv = uitofp i16 %vecext to fp128553 store fp128 %conv, ptr %a, align 16554 ret void555}556 557; Function Attrs: norecurse nounwind558define void @uhwVecConv2qp1(ptr nocapture %a, <8 x i16> %b) {559; CHECK-LABEL: uhwVecConv2qp1:560; CHECK: # %bb.0: # %entry561; CHECK-NEXT: vextractuh v2, v2, 12562; CHECK-NEXT: xscvudqp v2, v2563; CHECK-NEXT: stxv v2, 0(r3)564; CHECK-NEXT: blr565;566; CHECK-BE-LABEL: uhwVecConv2qp1:567; CHECK-BE: # %bb.0: # %entry568; CHECK-BE-NEXT: vextractuh v2, v2, 2569; CHECK-BE-NEXT: xscvudqp v2, v2570; CHECK-BE-NEXT: stxv v2, 0(r3)571; CHECK-BE-NEXT: blr572entry:573 %vecext = extractelement <8 x i16> %b, i32 1574 %conv = uitofp i16 %vecext to fp128575 store fp128 %conv, ptr %a, align 16576 ret void577}578 579; Function Attrs: norecurse nounwind580define void @uhwVecConv2qp2(ptr nocapture %a, <8 x i16> %b) {581; CHECK-LABEL: uhwVecConv2qp2:582; CHECK: # %bb.0: # %entry583; CHECK-NEXT: vextractuh v2, v2, 10584; CHECK-NEXT: xscvudqp v2, v2585; CHECK-NEXT: stxv v2, 0(r3)586; CHECK-NEXT: blr587;588; CHECK-BE-LABEL: uhwVecConv2qp2:589; CHECK-BE: # %bb.0: # %entry590; CHECK-BE-NEXT: vextractuh v2, v2, 4591; CHECK-BE-NEXT: xscvudqp v2, v2592; CHECK-BE-NEXT: stxv v2, 0(r3)593; CHECK-BE-NEXT: blr594entry:595 %vecext = extractelement <8 x i16> %b, i32 2596 %conv = uitofp i16 %vecext to fp128597 store fp128 %conv, ptr %a, align 16598 ret void599}600 601; Function Attrs: norecurse nounwind602define void @uhwVecConv2qp3(ptr nocapture %a, <8 x i16> %b) {603; CHECK-LABEL: uhwVecConv2qp3:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: vextractuh v2, v2, 8606; CHECK-NEXT: xscvudqp v2, v2607; CHECK-NEXT: stxv v2, 0(r3)608; CHECK-NEXT: blr609;610; CHECK-BE-LABEL: uhwVecConv2qp3:611; CHECK-BE: # %bb.0: # %entry612; CHECK-BE-NEXT: vextractuh v2, v2, 6613; CHECK-BE-NEXT: xscvudqp v2, v2614; CHECK-BE-NEXT: stxv v2, 0(r3)615; CHECK-BE-NEXT: blr616entry:617 %vecext = extractelement <8 x i16> %b, i32 3618 %conv = uitofp i16 %vecext to fp128619 store fp128 %conv, ptr %a, align 16620 ret void621}622 623; Function Attrs: norecurse nounwind624define void @uhwVecConv2qp4(ptr nocapture %a, <8 x i16> %b) {625; CHECK-LABEL: uhwVecConv2qp4:626; CHECK: # %bb.0: # %entry627; CHECK-NEXT: vextractuh v2, v2, 6628; CHECK-NEXT: xscvudqp v2, v2629; CHECK-NEXT: stxv v2, 0(r3)630; CHECK-NEXT: blr631;632; CHECK-BE-LABEL: uhwVecConv2qp4:633; CHECK-BE: # %bb.0: # %entry634; CHECK-BE-NEXT: vextractuh v2, v2, 8635; CHECK-BE-NEXT: xscvudqp v2, v2636; CHECK-BE-NEXT: stxv v2, 0(r3)637; CHECK-BE-NEXT: blr638entry:639 %vecext = extractelement <8 x i16> %b, i32 4640 %conv = uitofp i16 %vecext to fp128641 store fp128 %conv, ptr %a, align 16642 ret void643}644 645; Function Attrs: norecurse nounwind646define void @uhwVecConv2qp5(ptr nocapture %a, <8 x i16> %b) {647; CHECK-LABEL: uhwVecConv2qp5:648; CHECK: # %bb.0: # %entry649; CHECK-NEXT: vextractuh v2, v2, 4650; CHECK-NEXT: xscvudqp v2, v2651; CHECK-NEXT: stxv v2, 0(r3)652; CHECK-NEXT: blr653;654; CHECK-BE-LABEL: uhwVecConv2qp5:655; CHECK-BE: # %bb.0: # %entry656; CHECK-BE-NEXT: vextractuh v2, v2, 10657; CHECK-BE-NEXT: xscvudqp v2, v2658; CHECK-BE-NEXT: stxv v2, 0(r3)659; CHECK-BE-NEXT: blr660entry:661 %vecext = extractelement <8 x i16> %b, i32 5662 %conv = uitofp i16 %vecext to fp128663 store fp128 %conv, ptr %a, align 16664 ret void665}666 667; Function Attrs: norecurse nounwind668define void @uhwVecConv2qp6(ptr nocapture %a, <8 x i16> %b) {669; CHECK-LABEL: uhwVecConv2qp6:670; CHECK: # %bb.0: # %entry671; CHECK-NEXT: vextractuh v2, v2, 2672; CHECK-NEXT: xscvudqp v2, v2673; CHECK-NEXT: stxv v2, 0(r3)674; CHECK-NEXT: blr675;676; CHECK-BE-LABEL: uhwVecConv2qp6:677; CHECK-BE: # %bb.0: # %entry678; CHECK-BE-NEXT: vextractuh v2, v2, 12679; CHECK-BE-NEXT: xscvudqp v2, v2680; CHECK-BE-NEXT: stxv v2, 0(r3)681; CHECK-BE-NEXT: blr682entry:683 %vecext = extractelement <8 x i16> %b, i32 6684 %conv = uitofp i16 %vecext to fp128685 store fp128 %conv, ptr %a, align 16686 ret void687}688 689; Function Attrs: norecurse nounwind690define void @uhwVecConv2qp7(ptr nocapture %a, <8 x i16> %b) {691; CHECK-LABEL: uhwVecConv2qp7:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: vextractuh v2, v2, 0694; CHECK-NEXT: xscvudqp v2, v2695; CHECK-NEXT: stxv v2, 0(r3)696; CHECK-NEXT: blr697;698; CHECK-BE-LABEL: uhwVecConv2qp7:699; CHECK-BE: # %bb.0: # %entry700; CHECK-BE-NEXT: vextractuh v2, v2, 14701; CHECK-BE-NEXT: xscvudqp v2, v2702; CHECK-BE-NEXT: stxv v2, 0(r3)703; CHECK-BE-NEXT: blr704entry:705 %vecext = extractelement <8 x i16> %b, i32 7706 %conv = uitofp i16 %vecext to fp128707 store fp128 %conv, ptr %a, align 16708 ret void709}710 711; Vector extract Byte and convert to quad precision.712 713; Function Attrs: norecurse nounwind714define void @sbVecConv2qp(ptr nocapture %a, <16 x i8> %b) {715; CHECK-LABEL: sbVecConv2qp:716; CHECK: # %bb.0: # %entry717; CHECK-NEXT: vextractub v2, v2, 15718; CHECK-NEXT: vextsb2d v2, v2719; CHECK-NEXT: xscvsdqp v2, v2720; CHECK-NEXT: stxv v2, 0(r3)721; CHECK-NEXT: blr722;723; CHECK-BE-LABEL: sbVecConv2qp:724; CHECK-BE: # %bb.0: # %entry725; CHECK-BE-NEXT: vextractub v2, v2, 0726; CHECK-BE-NEXT: vextsb2d v2, v2727; CHECK-BE-NEXT: xscvsdqp v2, v2728; CHECK-BE-NEXT: stxv v2, 0(r3)729; CHECK-BE-NEXT: blr730entry:731 %vecext = extractelement <16 x i8> %b, i32 0732 %conv = sitofp i8 %vecext to fp128733 store fp128 %conv, ptr %a, align 16734 ret void735}736 737; Function Attrs: norecurse nounwind738define void @sbVecConv2qp1(ptr nocapture %a, <16 x i8> %b) {739; CHECK-LABEL: sbVecConv2qp1:740; CHECK: # %bb.0: # %entry741; CHECK-NEXT: vextractub v2, v2, 14742; CHECK-NEXT: vextsb2d v2, v2743; CHECK-NEXT: xscvsdqp v2, v2744; CHECK-NEXT: stxv v2, 0(r3)745; CHECK-NEXT: blr746;747; CHECK-BE-LABEL: sbVecConv2qp1:748; CHECK-BE: # %bb.0: # %entry749; CHECK-BE-NEXT: vextractub v2, v2, 1750; CHECK-BE-NEXT: vextsb2d v2, v2751; CHECK-BE-NEXT: xscvsdqp v2, v2752; CHECK-BE-NEXT: stxv v2, 0(r3)753; CHECK-BE-NEXT: blr754entry:755 %vecext = extractelement <16 x i8> %b, i32 1756 %conv = sitofp i8 %vecext to fp128757 store fp128 %conv, ptr %a, align 16758 ret void759}760 761; Function Attrs: norecurse nounwind762define void @sbVecConv2qp2(ptr nocapture %a, <16 x i8> %b) {763; CHECK-LABEL: sbVecConv2qp2:764; CHECK: # %bb.0: # %entry765; CHECK-NEXT: vextractub v2, v2, 13766; CHECK-NEXT: vextsb2d v2, v2767; CHECK-NEXT: xscvsdqp v2, v2768; CHECK-NEXT: stxv v2, 0(r3)769; CHECK-NEXT: blr770;771; CHECK-BE-LABEL: sbVecConv2qp2:772; CHECK-BE: # %bb.0: # %entry773; CHECK-BE-NEXT: vextractub v2, v2, 2774; CHECK-BE-NEXT: vextsb2d v2, v2775; CHECK-BE-NEXT: xscvsdqp v2, v2776; CHECK-BE-NEXT: stxv v2, 0(r3)777; CHECK-BE-NEXT: blr778entry:779 %vecext = extractelement <16 x i8> %b, i32 2780 %conv = sitofp i8 %vecext to fp128781 store fp128 %conv, ptr %a, align 16782 ret void783}784 785; Function Attrs: norecurse nounwind786define void @sbVecConv2qp3(ptr nocapture %a, <16 x i8> %b) {787; CHECK-LABEL: sbVecConv2qp3:788; CHECK: # %bb.0: # %entry789; CHECK-NEXT: vextractub v2, v2, 12790; CHECK-NEXT: vextsb2d v2, v2791; CHECK-NEXT: xscvsdqp v2, v2792; CHECK-NEXT: stxv v2, 0(r3)793; CHECK-NEXT: blr794;795; CHECK-BE-LABEL: sbVecConv2qp3:796; CHECK-BE: # %bb.0: # %entry797; CHECK-BE-NEXT: vextractub v2, v2, 3798; CHECK-BE-NEXT: vextsb2d v2, v2799; CHECK-BE-NEXT: xscvsdqp v2, v2800; CHECK-BE-NEXT: stxv v2, 0(r3)801; CHECK-BE-NEXT: blr802entry:803 %vecext = extractelement <16 x i8> %b, i32 3804 %conv = sitofp i8 %vecext to fp128805 store fp128 %conv, ptr %a, align 16806 ret void807}808 809; Function Attrs: norecurse nounwind810define void @sbVecConv2qp4(ptr nocapture %a, <16 x i8> %b) {811; CHECK-LABEL: sbVecConv2qp4:812; CHECK: # %bb.0: # %entry813; CHECK-NEXT: vextractub v2, v2, 11814; CHECK-NEXT: vextsb2d v2, v2815; CHECK-NEXT: xscvsdqp v2, v2816; CHECK-NEXT: stxv v2, 0(r3)817; CHECK-NEXT: blr818;819; CHECK-BE-LABEL: sbVecConv2qp4:820; CHECK-BE: # %bb.0: # %entry821; CHECK-BE-NEXT: vextractub v2, v2, 4822; CHECK-BE-NEXT: vextsb2d v2, v2823; CHECK-BE-NEXT: xscvsdqp v2, v2824; CHECK-BE-NEXT: stxv v2, 0(r3)825; CHECK-BE-NEXT: blr826entry:827 %vecext = extractelement <16 x i8> %b, i32 4828 %conv = sitofp i8 %vecext to fp128829 store fp128 %conv, ptr %a, align 16830 ret void831}832 833; Function Attrs: norecurse nounwind834define void @sbVecConv2qp5(ptr nocapture %a, <16 x i8> %b) {835; CHECK-LABEL: sbVecConv2qp5:836; CHECK: # %bb.0: # %entry837; CHECK-NEXT: vextractub v2, v2, 10838; CHECK-NEXT: vextsb2d v2, v2839; CHECK-NEXT: xscvsdqp v2, v2840; CHECK-NEXT: stxv v2, 0(r3)841; CHECK-NEXT: blr842;843; CHECK-BE-LABEL: sbVecConv2qp5:844; CHECK-BE: # %bb.0: # %entry845; CHECK-BE-NEXT: vextractub v2, v2, 5846; CHECK-BE-NEXT: vextsb2d v2, v2847; CHECK-BE-NEXT: xscvsdqp v2, v2848; CHECK-BE-NEXT: stxv v2, 0(r3)849; CHECK-BE-NEXT: blr850entry:851 %vecext = extractelement <16 x i8> %b, i32 5852 %conv = sitofp i8 %vecext to fp128853 store fp128 %conv, ptr %a, align 16854 ret void855}856 857; Function Attrs: norecurse nounwind858define void @sbVecConv2qp6(ptr nocapture %a, <16 x i8> %b) {859; CHECK-LABEL: sbVecConv2qp6:860; CHECK: # %bb.0: # %entry861; CHECK-NEXT: vextractub v2, v2, 9862; CHECK-NEXT: vextsb2d v2, v2863; CHECK-NEXT: xscvsdqp v2, v2864; CHECK-NEXT: stxv v2, 0(r3)865; CHECK-NEXT: blr866;867; CHECK-BE-LABEL: sbVecConv2qp6:868; CHECK-BE: # %bb.0: # %entry869; CHECK-BE-NEXT: vextractub v2, v2, 6870; CHECK-BE-NEXT: vextsb2d v2, v2871; CHECK-BE-NEXT: xscvsdqp v2, v2872; CHECK-BE-NEXT: stxv v2, 0(r3)873; CHECK-BE-NEXT: blr874entry:875 %vecext = extractelement <16 x i8> %b, i32 6876 %conv = sitofp i8 %vecext to fp128877 store fp128 %conv, ptr %a, align 16878 ret void879}880 881; Function Attrs: norecurse nounwind882define void @sbVecConv2qp7(ptr nocapture %a, <16 x i8> %b) {883; CHECK-LABEL: sbVecConv2qp7:884; CHECK: # %bb.0: # %entry885; CHECK-NEXT: vextractub v2, v2, 8886; CHECK-NEXT: vextsb2d v2, v2887; CHECK-NEXT: xscvsdqp v2, v2888; CHECK-NEXT: stxv v2, 0(r3)889; CHECK-NEXT: blr890;891; CHECK-BE-LABEL: sbVecConv2qp7:892; CHECK-BE: # %bb.0: # %entry893; CHECK-BE-NEXT: vextractub v2, v2, 7894; CHECK-BE-NEXT: vextsb2d v2, v2895; CHECK-BE-NEXT: xscvsdqp v2, v2896; CHECK-BE-NEXT: stxv v2, 0(r3)897; CHECK-BE-NEXT: blr898entry:899 %vecext = extractelement <16 x i8> %b, i32 7900 %conv = sitofp i8 %vecext to fp128901 store fp128 %conv, ptr %a, align 16902 ret void903}904 905; Function Attrs: norecurse nounwind906define void @sbVecConv2qp8(ptr nocapture %a, <16 x i8> %b) {907; CHECK-LABEL: sbVecConv2qp8:908; CHECK: # %bb.0: # %entry909; CHECK-NEXT: vextractub v2, v2, 7910; CHECK-NEXT: vextsb2d v2, v2911; CHECK-NEXT: xscvsdqp v2, v2912; CHECK-NEXT: stxv v2, 0(r3)913; CHECK-NEXT: blr914;915; CHECK-BE-LABEL: sbVecConv2qp8:916; CHECK-BE: # %bb.0: # %entry917; CHECK-BE-NEXT: vextractub v2, v2, 8918; CHECK-BE-NEXT: vextsb2d v2, v2919; CHECK-BE-NEXT: xscvsdqp v2, v2920; CHECK-BE-NEXT: stxv v2, 0(r3)921; CHECK-BE-NEXT: blr922entry:923 %vecext = extractelement <16 x i8> %b, i32 8924 %conv = sitofp i8 %vecext to fp128925 store fp128 %conv, ptr %a, align 16926 ret void927}928 929; Function Attrs: norecurse nounwind930define void @sbVecConv2qp9(ptr nocapture %a, <16 x i8> %b) {931; CHECK-LABEL: sbVecConv2qp9:932; CHECK: # %bb.0: # %entry933; CHECK-NEXT: vextractub v2, v2, 6934; CHECK-NEXT: vextsb2d v2, v2935; CHECK-NEXT: xscvsdqp v2, v2936; CHECK-NEXT: stxv v2, 0(r3)937; CHECK-NEXT: blr938;939; CHECK-BE-LABEL: sbVecConv2qp9:940; CHECK-BE: # %bb.0: # %entry941; CHECK-BE-NEXT: vextractub v2, v2, 9942; CHECK-BE-NEXT: vextsb2d v2, v2943; CHECK-BE-NEXT: xscvsdqp v2, v2944; CHECK-BE-NEXT: stxv v2, 0(r3)945; CHECK-BE-NEXT: blr946entry:947 %vecext = extractelement <16 x i8> %b, i32 9948 %conv = sitofp i8 %vecext to fp128949 store fp128 %conv, ptr %a, align 16950 ret void951}952 953; Function Attrs: norecurse nounwind954define void @sbVecConv2qp10(ptr nocapture %a, <16 x i8> %b) {955; CHECK-LABEL: sbVecConv2qp10:956; CHECK: # %bb.0: # %entry957; CHECK-NEXT: vextractub v2, v2, 5958; CHECK-NEXT: vextsb2d v2, v2959; CHECK-NEXT: xscvsdqp v2, v2960; CHECK-NEXT: stxv v2, 0(r3)961; CHECK-NEXT: blr962;963; CHECK-BE-LABEL: sbVecConv2qp10:964; CHECK-BE: # %bb.0: # %entry965; CHECK-BE-NEXT: vextractub v2, v2, 10966; CHECK-BE-NEXT: vextsb2d v2, v2967; CHECK-BE-NEXT: xscvsdqp v2, v2968; CHECK-BE-NEXT: stxv v2, 0(r3)969; CHECK-BE-NEXT: blr970entry:971 %vecext = extractelement <16 x i8> %b, i32 10972 %conv = sitofp i8 %vecext to fp128973 store fp128 %conv, ptr %a, align 16974 ret void975}976 977; Function Attrs: norecurse nounwind978define void @sbVecConv2qp11(ptr nocapture %a, <16 x i8> %b) {979; CHECK-LABEL: sbVecConv2qp11:980; CHECK: # %bb.0: # %entry981; CHECK-NEXT: vextractub v2, v2, 4982; CHECK-NEXT: vextsb2d v2, v2983; CHECK-NEXT: xscvsdqp v2, v2984; CHECK-NEXT: stxv v2, 0(r3)985; CHECK-NEXT: blr986;987; CHECK-BE-LABEL: sbVecConv2qp11:988; CHECK-BE: # %bb.0: # %entry989; CHECK-BE-NEXT: vextractub v2, v2, 11990; CHECK-BE-NEXT: vextsb2d v2, v2991; CHECK-BE-NEXT: xscvsdqp v2, v2992; CHECK-BE-NEXT: stxv v2, 0(r3)993; CHECK-BE-NEXT: blr994entry:995 %vecext = extractelement <16 x i8> %b, i32 11996 %conv = sitofp i8 %vecext to fp128997 store fp128 %conv, ptr %a, align 16998 ret void999}1000 1001; Function Attrs: norecurse nounwind1002define void @sbVecConv2qp12(ptr nocapture %a, <16 x i8> %b) {1003; CHECK-LABEL: sbVecConv2qp12:1004; CHECK: # %bb.0: # %entry1005; CHECK-NEXT: vextractub v2, v2, 31006; CHECK-NEXT: vextsb2d v2, v21007; CHECK-NEXT: xscvsdqp v2, v21008; CHECK-NEXT: stxv v2, 0(r3)1009; CHECK-NEXT: blr1010;1011; CHECK-BE-LABEL: sbVecConv2qp12:1012; CHECK-BE: # %bb.0: # %entry1013; CHECK-BE-NEXT: vextractub v2, v2, 121014; CHECK-BE-NEXT: vextsb2d v2, v21015; CHECK-BE-NEXT: xscvsdqp v2, v21016; CHECK-BE-NEXT: stxv v2, 0(r3)1017; CHECK-BE-NEXT: blr1018entry:1019 %vecext = extractelement <16 x i8> %b, i32 121020 %conv = sitofp i8 %vecext to fp1281021 store fp128 %conv, ptr %a, align 161022 ret void1023}1024 1025; Function Attrs: norecurse nounwind1026define void @sbVecConv2qp13(ptr nocapture %a, <16 x i8> %b) {1027; CHECK-LABEL: sbVecConv2qp13:1028; CHECK: # %bb.0: # %entry1029; CHECK-NEXT: vextractub v2, v2, 21030; CHECK-NEXT: vextsb2d v2, v21031; CHECK-NEXT: xscvsdqp v2, v21032; CHECK-NEXT: stxv v2, 0(r3)1033; CHECK-NEXT: blr1034;1035; CHECK-BE-LABEL: sbVecConv2qp13:1036; CHECK-BE: # %bb.0: # %entry1037; CHECK-BE-NEXT: vextractub v2, v2, 131038; CHECK-BE-NEXT: vextsb2d v2, v21039; CHECK-BE-NEXT: xscvsdqp v2, v21040; CHECK-BE-NEXT: stxv v2, 0(r3)1041; CHECK-BE-NEXT: blr1042entry:1043 %vecext = extractelement <16 x i8> %b, i32 131044 %conv = sitofp i8 %vecext to fp1281045 store fp128 %conv, ptr %a, align 161046 ret void1047}1048 1049; Function Attrs: norecurse nounwind1050define void @sbVecConv2qp14(ptr nocapture %a, <16 x i8> %b) {1051; CHECK-LABEL: sbVecConv2qp14:1052; CHECK: # %bb.0: # %entry1053; CHECK-NEXT: vextractub v2, v2, 11054; CHECK-NEXT: vextsb2d v2, v21055; CHECK-NEXT: xscvsdqp v2, v21056; CHECK-NEXT: stxv v2, 0(r3)1057; CHECK-NEXT: blr1058;1059; CHECK-BE-LABEL: sbVecConv2qp14:1060; CHECK-BE: # %bb.0: # %entry1061; CHECK-BE-NEXT: vextractub v2, v2, 141062; CHECK-BE-NEXT: vextsb2d v2, v21063; CHECK-BE-NEXT: xscvsdqp v2, v21064; CHECK-BE-NEXT: stxv v2, 0(r3)1065; CHECK-BE-NEXT: blr1066entry:1067 %vecext = extractelement <16 x i8> %b, i32 141068 %conv = sitofp i8 %vecext to fp1281069 store fp128 %conv, ptr %a, align 161070 ret void1071}1072 1073; Function Attrs: norecurse nounwind1074define void @sbVecConv2qp15(ptr nocapture %a, <16 x i8> %b) {1075; CHECK-LABEL: sbVecConv2qp15:1076; CHECK: # %bb.0: # %entry1077; CHECK-NEXT: vextractub v2, v2, 01078; CHECK-NEXT: vextsb2d v2, v21079; CHECK-NEXT: xscvsdqp v2, v21080; CHECK-NEXT: stxv v2, 0(r3)1081; CHECK-NEXT: blr1082;1083; CHECK-BE-LABEL: sbVecConv2qp15:1084; CHECK-BE: # %bb.0: # %entry1085; CHECK-BE-NEXT: vextractub v2, v2, 151086; CHECK-BE-NEXT: vextsb2d v2, v21087; CHECK-BE-NEXT: xscvsdqp v2, v21088; CHECK-BE-NEXT: stxv v2, 0(r3)1089; CHECK-BE-NEXT: blr1090entry:1091 %vecext = extractelement <16 x i8> %b, i32 151092 %conv = sitofp i8 %vecext to fp1281093 store fp128 %conv, ptr %a, align 161094 ret void1095}1096 1097; Function Attrs: norecurse nounwind1098define void @ubVecConv2qp(ptr nocapture %a, <16 x i8> %b) {1099; CHECK-LABEL: ubVecConv2qp:1100; CHECK: # %bb.0: # %entry1101; CHECK-NEXT: vextractub v2, v2, 151102; CHECK-NEXT: xscvudqp v2, v21103; CHECK-NEXT: stxv v2, 0(r3)1104; CHECK-NEXT: blr1105;1106; CHECK-BE-LABEL: ubVecConv2qp:1107; CHECK-BE: # %bb.0: # %entry1108; CHECK-BE-NEXT: vextractub v2, v2, 01109; CHECK-BE-NEXT: xscvudqp v2, v21110; CHECK-BE-NEXT: stxv v2, 0(r3)1111; CHECK-BE-NEXT: blr1112entry:1113 %vecext = extractelement <16 x i8> %b, i32 01114 %conv = uitofp i8 %vecext to fp1281115 store fp128 %conv, ptr %a, align 161116 ret void1117}1118 1119; Function Attrs: norecurse nounwind1120define void @ubVecConv2qp1(ptr nocapture %a, <16 x i8> %b) {1121; CHECK-LABEL: ubVecConv2qp1:1122; CHECK: # %bb.0: # %entry1123; CHECK-NEXT: vextractub v2, v2, 141124; CHECK-NEXT: xscvudqp v2, v21125; CHECK-NEXT: stxv v2, 0(r3)1126; CHECK-NEXT: blr1127;1128; CHECK-BE-LABEL: ubVecConv2qp1:1129; CHECK-BE: # %bb.0: # %entry1130; CHECK-BE-NEXT: vextractub v2, v2, 11131; CHECK-BE-NEXT: xscvudqp v2, v21132; CHECK-BE-NEXT: stxv v2, 0(r3)1133; CHECK-BE-NEXT: blr1134entry:1135 %vecext = extractelement <16 x i8> %b, i32 11136 %conv = uitofp i8 %vecext to fp1281137 store fp128 %conv, ptr %a, align 161138 ret void1139}1140 1141; Function Attrs: norecurse nounwind1142define void @ubVecConv2qp2(ptr nocapture %a, <16 x i8> %b) {1143; CHECK-LABEL: ubVecConv2qp2:1144; CHECK: # %bb.0: # %entry1145; CHECK-NEXT: vextractub v2, v2, 131146; CHECK-NEXT: xscvudqp v2, v21147; CHECK-NEXT: stxv v2, 0(r3)1148; CHECK-NEXT: blr1149;1150; CHECK-BE-LABEL: ubVecConv2qp2:1151; CHECK-BE: # %bb.0: # %entry1152; CHECK-BE-NEXT: vextractub v2, v2, 21153; CHECK-BE-NEXT: xscvudqp v2, v21154; CHECK-BE-NEXT: stxv v2, 0(r3)1155; CHECK-BE-NEXT: blr1156entry:1157 %vecext = extractelement <16 x i8> %b, i32 21158 %conv = uitofp i8 %vecext to fp1281159 store fp128 %conv, ptr %a, align 161160 ret void1161}1162 1163; Function Attrs: norecurse nounwind1164define void @ubVecConv2qp3(ptr nocapture %a, <16 x i8> %b) {1165; CHECK-LABEL: ubVecConv2qp3:1166; CHECK: # %bb.0: # %entry1167; CHECK-NEXT: vextractub v2, v2, 121168; CHECK-NEXT: xscvudqp v2, v21169; CHECK-NEXT: stxv v2, 0(r3)1170; CHECK-NEXT: blr1171;1172; CHECK-BE-LABEL: ubVecConv2qp3:1173; CHECK-BE: # %bb.0: # %entry1174; CHECK-BE-NEXT: vextractub v2, v2, 31175; CHECK-BE-NEXT: xscvudqp v2, v21176; CHECK-BE-NEXT: stxv v2, 0(r3)1177; CHECK-BE-NEXT: blr1178entry:1179 %vecext = extractelement <16 x i8> %b, i32 31180 %conv = uitofp i8 %vecext to fp1281181 store fp128 %conv, ptr %a, align 161182 ret void1183}1184 1185; Function Attrs: norecurse nounwind1186define void @ubVecConv2qp4(ptr nocapture %a, <16 x i8> %b) {1187; CHECK-LABEL: ubVecConv2qp4:1188; CHECK: # %bb.0: # %entry1189; CHECK-NEXT: vextractub v2, v2, 111190; CHECK-NEXT: xscvudqp v2, v21191; CHECK-NEXT: stxv v2, 0(r3)1192; CHECK-NEXT: blr1193;1194; CHECK-BE-LABEL: ubVecConv2qp4:1195; CHECK-BE: # %bb.0: # %entry1196; CHECK-BE-NEXT: vextractub v2, v2, 41197; CHECK-BE-NEXT: xscvudqp v2, v21198; CHECK-BE-NEXT: stxv v2, 0(r3)1199; CHECK-BE-NEXT: blr1200entry:1201 %vecext = extractelement <16 x i8> %b, i32 41202 %conv = uitofp i8 %vecext to fp1281203 store fp128 %conv, ptr %a, align 161204 ret void1205}1206 1207; Function Attrs: norecurse nounwind1208define void @ubVecConv2qp5(ptr nocapture %a, <16 x i8> %b) {1209; CHECK-LABEL: ubVecConv2qp5:1210; CHECK: # %bb.0: # %entry1211; CHECK-NEXT: vextractub v2, v2, 101212; CHECK-NEXT: xscvudqp v2, v21213; CHECK-NEXT: stxv v2, 0(r3)1214; CHECK-NEXT: blr1215;1216; CHECK-BE-LABEL: ubVecConv2qp5:1217; CHECK-BE: # %bb.0: # %entry1218; CHECK-BE-NEXT: vextractub v2, v2, 51219; CHECK-BE-NEXT: xscvudqp v2, v21220; CHECK-BE-NEXT: stxv v2, 0(r3)1221; CHECK-BE-NEXT: blr1222entry:1223 %vecext = extractelement <16 x i8> %b, i32 51224 %conv = uitofp i8 %vecext to fp1281225 store fp128 %conv, ptr %a, align 161226 ret void1227}1228 1229; Function Attrs: norecurse nounwind1230define void @ubVecConv2qp6(ptr nocapture %a, <16 x i8> %b) {1231; CHECK-LABEL: ubVecConv2qp6:1232; CHECK: # %bb.0: # %entry1233; CHECK-NEXT: vextractub v2, v2, 91234; CHECK-NEXT: xscvudqp v2, v21235; CHECK-NEXT: stxv v2, 0(r3)1236; CHECK-NEXT: blr1237;1238; CHECK-BE-LABEL: ubVecConv2qp6:1239; CHECK-BE: # %bb.0: # %entry1240; CHECK-BE-NEXT: vextractub v2, v2, 61241; CHECK-BE-NEXT: xscvudqp v2, v21242; CHECK-BE-NEXT: stxv v2, 0(r3)1243; CHECK-BE-NEXT: blr1244entry:1245 %vecext = extractelement <16 x i8> %b, i32 61246 %conv = uitofp i8 %vecext to fp1281247 store fp128 %conv, ptr %a, align 161248 ret void1249}1250 1251; Function Attrs: norecurse nounwind1252define void @ubVecConv2qp7(ptr nocapture %a, <16 x i8> %b) {1253; CHECK-LABEL: ubVecConv2qp7:1254; CHECK: # %bb.0: # %entry1255; CHECK-NEXT: vextractub v2, v2, 81256; CHECK-NEXT: xscvudqp v2, v21257; CHECK-NEXT: stxv v2, 0(r3)1258; CHECK-NEXT: blr1259;1260; CHECK-BE-LABEL: ubVecConv2qp7:1261; CHECK-BE: # %bb.0: # %entry1262; CHECK-BE-NEXT: vextractub v2, v2, 71263; CHECK-BE-NEXT: xscvudqp v2, v21264; CHECK-BE-NEXT: stxv v2, 0(r3)1265; CHECK-BE-NEXT: blr1266entry:1267 %vecext = extractelement <16 x i8> %b, i32 71268 %conv = uitofp i8 %vecext to fp1281269 store fp128 %conv, ptr %a, align 161270 ret void1271}1272 1273; Function Attrs: norecurse nounwind1274define void @ubVecConv2qp8(ptr nocapture %a, <16 x i8> %b) {1275; CHECK-LABEL: ubVecConv2qp8:1276; CHECK: # %bb.0: # %entry1277; CHECK-NEXT: vextractub v2, v2, 71278; CHECK-NEXT: xscvudqp v2, v21279; CHECK-NEXT: stxv v2, 0(r3)1280; CHECK-NEXT: blr1281;1282; CHECK-BE-LABEL: ubVecConv2qp8:1283; CHECK-BE: # %bb.0: # %entry1284; CHECK-BE-NEXT: vextractub v2, v2, 81285; CHECK-BE-NEXT: xscvudqp v2, v21286; CHECK-BE-NEXT: stxv v2, 0(r3)1287; CHECK-BE-NEXT: blr1288entry:1289 %vecext = extractelement <16 x i8> %b, i32 81290 %conv = uitofp i8 %vecext to fp1281291 store fp128 %conv, ptr %a, align 161292 ret void1293}1294 1295; Function Attrs: norecurse nounwind1296define void @ubVecConv2qp9(ptr nocapture %a, <16 x i8> %b) {1297; CHECK-LABEL: ubVecConv2qp9:1298; CHECK: # %bb.0: # %entry1299; CHECK-NEXT: vextractub v2, v2, 61300; CHECK-NEXT: xscvudqp v2, v21301; CHECK-NEXT: stxv v2, 0(r3)1302; CHECK-NEXT: blr1303;1304; CHECK-BE-LABEL: ubVecConv2qp9:1305; CHECK-BE: # %bb.0: # %entry1306; CHECK-BE-NEXT: vextractub v2, v2, 91307; CHECK-BE-NEXT: xscvudqp v2, v21308; CHECK-BE-NEXT: stxv v2, 0(r3)1309; CHECK-BE-NEXT: blr1310entry:1311 %vecext = extractelement <16 x i8> %b, i32 91312 %conv = uitofp i8 %vecext to fp1281313 store fp128 %conv, ptr %a, align 161314 ret void1315}1316 1317; Function Attrs: norecurse nounwind1318define void @ubVecConv2qp10(ptr nocapture %a, <16 x i8> %b) {1319; CHECK-LABEL: ubVecConv2qp10:1320; CHECK: # %bb.0: # %entry1321; CHECK-NEXT: vextractub v2, v2, 51322; CHECK-NEXT: xscvudqp v2, v21323; CHECK-NEXT: stxv v2, 0(r3)1324; CHECK-NEXT: blr1325;1326; CHECK-BE-LABEL: ubVecConv2qp10:1327; CHECK-BE: # %bb.0: # %entry1328; CHECK-BE-NEXT: vextractub v2, v2, 101329; CHECK-BE-NEXT: xscvudqp v2, v21330; CHECK-BE-NEXT: stxv v2, 0(r3)1331; CHECK-BE-NEXT: blr1332entry:1333 %vecext = extractelement <16 x i8> %b, i32 101334 %conv = uitofp i8 %vecext to fp1281335 store fp128 %conv, ptr %a, align 161336 ret void1337}1338 1339; Function Attrs: norecurse nounwind1340define void @ubVecConv2qp11(ptr nocapture %a, <16 x i8> %b) {1341; CHECK-LABEL: ubVecConv2qp11:1342; CHECK: # %bb.0: # %entry1343; CHECK-NEXT: vextractub v2, v2, 41344; CHECK-NEXT: xscvudqp v2, v21345; CHECK-NEXT: stxv v2, 0(r3)1346; CHECK-NEXT: blr1347;1348; CHECK-BE-LABEL: ubVecConv2qp11:1349; CHECK-BE: # %bb.0: # %entry1350; CHECK-BE-NEXT: vextractub v2, v2, 111351; CHECK-BE-NEXT: xscvudqp v2, v21352; CHECK-BE-NEXT: stxv v2, 0(r3)1353; CHECK-BE-NEXT: blr1354entry:1355 %vecext = extractelement <16 x i8> %b, i32 111356 %conv = uitofp i8 %vecext to fp1281357 store fp128 %conv, ptr %a, align 161358 ret void1359}1360 1361; Function Attrs: norecurse nounwind1362define void @ubVecConv2qp12(ptr nocapture %a, <16 x i8> %b) {1363; CHECK-LABEL: ubVecConv2qp12:1364; CHECK: # %bb.0: # %entry1365; CHECK-NEXT: vextractub v2, v2, 31366; CHECK-NEXT: xscvudqp v2, v21367; CHECK-NEXT: stxv v2, 0(r3)1368; CHECK-NEXT: blr1369;1370; CHECK-BE-LABEL: ubVecConv2qp12:1371; CHECK-BE: # %bb.0: # %entry1372; CHECK-BE-NEXT: vextractub v2, v2, 121373; CHECK-BE-NEXT: xscvudqp v2, v21374; CHECK-BE-NEXT: stxv v2, 0(r3)1375; CHECK-BE-NEXT: blr1376entry:1377 %vecext = extractelement <16 x i8> %b, i32 121378 %conv = uitofp i8 %vecext to fp1281379 store fp128 %conv, ptr %a, align 161380 ret void1381}1382 1383; Function Attrs: norecurse nounwind1384define void @ubVecConv2qp13(ptr nocapture %a, <16 x i8> %b) {1385; CHECK-LABEL: ubVecConv2qp13:1386; CHECK: # %bb.0: # %entry1387; CHECK-NEXT: vextractub v2, v2, 21388; CHECK-NEXT: xscvudqp v2, v21389; CHECK-NEXT: stxv v2, 0(r3)1390; CHECK-NEXT: blr1391;1392; CHECK-BE-LABEL: ubVecConv2qp13:1393; CHECK-BE: # %bb.0: # %entry1394; CHECK-BE-NEXT: vextractub v2, v2, 131395; CHECK-BE-NEXT: xscvudqp v2, v21396; CHECK-BE-NEXT: stxv v2, 0(r3)1397; CHECK-BE-NEXT: blr1398entry:1399 %vecext = extractelement <16 x i8> %b, i32 131400 %conv = uitofp i8 %vecext to fp1281401 store fp128 %conv, ptr %a, align 161402 ret void1403}1404 1405; Function Attrs: norecurse nounwind1406define void @ubVecConv2qp14(ptr nocapture %a, <16 x i8> %b) {1407; CHECK-LABEL: ubVecConv2qp14:1408; CHECK: # %bb.0: # %entry1409; CHECK-NEXT: vextractub v2, v2, 11410; CHECK-NEXT: xscvudqp v2, v21411; CHECK-NEXT: stxv v2, 0(r3)1412; CHECK-NEXT: blr1413;1414; CHECK-BE-LABEL: ubVecConv2qp14:1415; CHECK-BE: # %bb.0: # %entry1416; CHECK-BE-NEXT: vextractub v2, v2, 141417; CHECK-BE-NEXT: xscvudqp v2, v21418; CHECK-BE-NEXT: stxv v2, 0(r3)1419; CHECK-BE-NEXT: blr1420entry:1421 %vecext = extractelement <16 x i8> %b, i32 141422 %conv = uitofp i8 %vecext to fp1281423 store fp128 %conv, ptr %a, align 161424 ret void1425}1426 1427; Function Attrs: norecurse nounwind1428define void @ubVecConv2qp15(ptr nocapture %a, <16 x i8> %b) {1429; CHECK-LABEL: ubVecConv2qp15:1430; CHECK: # %bb.0: # %entry1431; CHECK-NEXT: vextractub v2, v2, 01432; CHECK-NEXT: xscvudqp v2, v21433; CHECK-NEXT: stxv v2, 0(r3)1434; CHECK-NEXT: blr1435;1436; CHECK-BE-LABEL: ubVecConv2qp15:1437; CHECK-BE: # %bb.0: # %entry1438; CHECK-BE-NEXT: vextractub v2, v2, 151439; CHECK-BE-NEXT: xscvudqp v2, v21440; CHECK-BE-NEXT: stxv v2, 0(r3)1441; CHECK-BE-NEXT: blr1442entry:1443 %vecext = extractelement <16 x i8> %b, i32 151444 %conv = uitofp i8 %vecext to fp1281445 store fp128 %conv, ptr %a, align 161446 ret void1447}1448