448 lines · plain
1; FIXME: FastISel currently returns false if it hits code that uses VSX2; registers and with -fast-isel-abort=1 turned on the test case will then fail.3; When fastisel better supports VSX fix up this test case.4;5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s7; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC9708; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE9 10;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt11;; to SelectionDAG in some cases.12 13; Test sitofp14 15define void @sitofp_single_i64(i64 %a, float %b) nounwind {16entry:17; CHECK: sitofp_single_i6418; PPC970: sitofp_single_i6419 %b.addr = alloca float, align 420 %conv = sitofp i64 %a to float21; CHECK: std22; CHECK: lfd23; CHECK: fcfids24; PPC970: std25; PPC970: lfd26; PPC970: fcfid27; PPC970: frsp28 store float %conv, ptr %b.addr, align 429 ret void30}31 32define void @sitofp_single_i32(i32 %a, float %b) nounwind {33entry:34; CHECK: sitofp_single_i3235; PPC970: sitofp_single_i3236 %b.addr = alloca float, align 437 %conv = sitofp i32 %a to float38; CHECK: std39; CHECK-NEXT: li40; CHECK-NEXT: lfiwax41; CHECK-NEXT: fcfids42; PPC970: std43; PPC970: lfd44; PPC970: fcfid45; PPC970: frsp46; SPE: efscfsi47 store float %conv, ptr %b.addr, align 448 ret void49}50 51define void @sitofp_single_i16(i16 %a, float %b) nounwind {52entry:53; CHECK: sitofp_single_i1654; PPC970: sitofp_single_i1655 %b.addr = alloca float, align 456 %conv = sitofp i16 %a to float57; CHECK: extsh58; CHECK: std59; CHECK: lfd60; CHECK: fcfids61; PPC970: extsh62; PPC970: std63; PPC970: lfd64; PPC970: fcfid65; PPC970: frsp66; SPE: extsh67; SPE: efscfsi68 store float %conv, ptr %b.addr, align 469 ret void70}71 72define void @sitofp_single_i8(i8 %a) nounwind {73entry:74; CHECK: sitofp_single_i875; PPC970: sitofp_single_i876 %b.addr = alloca float, align 477 %conv = sitofp i8 %a to float78; CHECK: extsb79; CHECK: std80; CHECK: lfd81; CHECK: fcfids82; PPC970: extsb83; PPC970: std84; PPC970: lfd85; PPC970: fcfid86; PPC970: frsp87; SPE: extsb88; SPE: efscfsi89 store float %conv, ptr %b.addr, align 490 ret void91}92 93define void @sitofp_double_i32(i32 %a, double %b) nounwind {94entry:95; CHECK: sitofp_double_i3296; PPC970: sitofp_double_i3297 %b.addr = alloca double, align 898 %conv = sitofp i32 %a to double99; CHECK: std100; CHECK-NOT: ori101; CHECK: li102; CHECK-NOT: ori103; CHECK: lfiwax104; CHECK: fcfid105; PPC970: std106; PPC970: lfd107; PPC970: fcfid108; SPE: efdcfsi109 store double %conv, ptr %b.addr, align 8110 ret void111}112 113define void @sitofp_double_i64(i64 %a, double %b) nounwind {114entry:115; CHECK: sitofp_double_i64116; PPC970: sitofp_double_i64117 %b.addr = alloca double, align 8118 %conv = sitofp i64 %a to double119; CHECK: std120; CHECK: lfd121; CHECK: fcfid122; PPC970: std123; PPC970: lfd124; PPC970: fcfid125 store double %conv, ptr %b.addr, align 8126 ret void127}128 129define void @sitofp_double_i16(i16 %a, double %b) nounwind {130entry:131; CHECK: sitofp_double_i16132; PPC970: sitofp_double_i16133 %b.addr = alloca double, align 8134 %conv = sitofp i16 %a to double135; CHECK: extsh136; CHECK: std137; CHECK: lfd138; CHECK: fcfid139; PPC970: extsh140; PPC970: std141; PPC970: lfd142; PPC970: fcfid143; SPE: extsh144; SPE: efdcfsi145 store double %conv, ptr %b.addr, align 8146 ret void147}148 149define void @sitofp_double_i8(i8 %a, double %b) nounwind {150entry:151; CHECK: sitofp_double_i8152; PPC970: sitofp_double_i8153 %b.addr = alloca double, align 8154 %conv = sitofp i8 %a to double155; CHECK: extsb156; CHECK: std157; CHECK: lfd158; CHECK: fcfid159; PPC970: extsb160; PPC970: std161; PPC970: lfd162; PPC970: fcfid163; SPE: extsb164; SPE: efdcfsi165 store double %conv, ptr %b.addr, align 8166 ret void167}168 169; Test uitofp170 171define void @uitofp_single_i64(i64 %a, float %b) nounwind {172entry:173; CHECK: uitofp_single_i64174; PPC970: uitofp_single_i64175 %b.addr = alloca float, align 4176 %conv = uitofp i64 %a to float177; CHECK: std178; CHECK: lfd179; CHECK: fcfidus180; PPC970-NOT: fcfidus181 store float %conv, ptr %b.addr, align 4182 ret void183}184 185define void @uitofp_single_i32(i32 %a, float %b) nounwind {186entry:187; CHECK: uitofp_single_i32188; PPC970: uitofp_single_i32189 %b.addr = alloca float, align 4190 %conv = uitofp i32 %a to float191; CHECK: std192; CHECK-NOT: ori193; CHECK: li194; CHECK-NOT: ori195; CHECK: lfiwzx196; CHECK: fcfidus197; PPC970-NOT: lfiwzx198; PPC970-NOT: fcfidus199; SPE: efscfui200 store float %conv, ptr %b.addr, align 4201 ret void202}203 204define void @uitofp_single_i16(i16 %a, float %b) nounwind {205entry:206; CHECK: uitofp_single_i16207; PPC970: uitofp_single_i16208 %b.addr = alloca float, align 4209 %conv = uitofp i16 %a to float210; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48211; CHECK: std212; CHECK: lfd213; CHECK: fcfidus214; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16215; PPC970: std216; PPC970: lfd217; PPC970: fcfid218; PPC970: frsp219; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16220; SPE: efscfui221 store float %conv, ptr %b.addr, align 4222 ret void223}224 225define void @uitofp_single_i8(i8 %a) nounwind {226entry:227; CHECK: uitofp_single_i8228; PPC970: uitofp_single_i8229 %b.addr = alloca float, align 4230 %conv = uitofp i8 %a to float231; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56232; CHECK: std233; CHECK: lfd234; CHECK: fcfidus235; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24236; PPC970: std237; PPC970: lfd238; PPC970: fcfid239; PPC970: frsp240; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24241; SPE: efscfui242 store float %conv, ptr %b.addr, align 4243 ret void244}245 246define void @uitofp_double_i64(i64 %a, double %b) nounwind {247entry:248; CHECK: uitofp_double_i64249; PPC970: uitofp_double_i64250 %b.addr = alloca double, align 8251 %conv = uitofp i64 %a to double252; CHECK: std253; CHECK: lfd254; CHECK: fcfidu255; PPC970-NOT: fcfidu256 store double %conv, ptr %b.addr, align 8257 ret void258}259 260define void @uitofp_double_i32(i32 %a, double %b) nounwind {261entry:262; CHECK: uitofp_double_i32263; PPC970: uitofp_double_i32264 %b.addr = alloca double, align 8265 %conv = uitofp i32 %a to double266; CHECK: std267; CHECK-NEXT: li268; CHECK-NEXT: lfiwzx269; CHECK-NEXT: fcfidu270; PPC970-NOT: lfiwzx271; PPC970-NOT: fcfidu272; SPE: efdcfui273 store double %conv, ptr %b.addr, align 8274 ret void275}276 277define void @uitofp_double_i16(i16 %a, double %b) nounwind {278entry:279; CHECK: uitofp_double_i16280; PPC970: uitofp_double_i16281 %b.addr = alloca double, align 8282 %conv = uitofp i16 %a to double283; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48284; CHECK: std285; CHECK: lfd286; CHECK: fcfidu287; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16288; PPC970: std289; PPC970: lfd290; PPC970: fcfid291; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16292; SPE: efdcfui293 store double %conv, ptr %b.addr, align 8294 ret void295}296 297define void @uitofp_double_i8(i8 %a, double %b) nounwind {298entry:299; CHECK: uitofp_double_i8300; PPC970: uitofp_double_i8301 %b.addr = alloca double, align 8302 %conv = uitofp i8 %a to double303; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56304; CHECK: std305; CHECK: lfd306; CHECK: fcfidu307; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24308; PPC970: std309; PPC970: lfd310; PPC970: fcfid311; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24312; SPE: efdcfui313 store double %conv, ptr %b.addr, align 8314 ret void315}316 317; Test fptosi318 319define void @fptosi_float_i32(float %a) nounwind {320entry:321; CHECK: fptosi_float_i32322; PPC970: fptosi_float_i32323 %b.addr = alloca i32, align 4324 %conv = fptosi float %a to i32325; CHECK: fctiwz326; CHECK: stfd327; CHECK: lwa328; PPC970: fctiwz329; PPC970: stfd330; PPC970: lwa331; SPE: efsctsi332 store i32 %conv, ptr %b.addr, align 4333 ret void334}335 336define void @fptosi_float_i64(float %a) nounwind {337entry:338; CHECK: fptosi_float_i64339; PPC970: fptosi_float_i64340 %b.addr = alloca i64, align 4341 %conv = fptosi float %a to i64342; CHECK: fctidz343; CHECK: stfd344; CHECK: ld345; PPC970: fctidz346; PPC970: stfd347; PPC970: ld348 store i64 %conv, ptr %b.addr, align 4349 ret void350}351 352define void @fptosi_double_i32(double %a) nounwind {353entry:354; CHECK: fptosi_double_i32355; PPC970: fptosi_double_i32356 %b.addr = alloca i32, align 8357 %conv = fptosi double %a to i32358; CHECK: fctiwz359; CHECK: stfd360; CHECK: lwa361; PPC970: fctiwz362; PPC970: stfd363; PPC970: lwa364; SPE: efdctsi365 store i32 %conv, ptr %b.addr, align 8366 ret void367}368 369define void @fptosi_double_i64(double %a) nounwind {370entry:371; CHECK: fptosi_double_i64372; PPC970: fptosi_double_i64373 %b.addr = alloca i64, align 8374 %conv = fptosi double %a to i64375; CHECK: fctidz376; CHECK: stfd377; CHECK: ld378; PPC970: fctidz379; PPC970: stfd380; PPC970: ld381 store i64 %conv, ptr %b.addr, align 8382 ret void383}384 385; Test fptoui386 387define void @fptoui_float_i32(float %a) nounwind {388entry:389; CHECK: fptoui_float_i32390; PPC970: fptoui_float_i32391 %b.addr = alloca i32, align 4392 %conv = fptoui float %a to i32393; CHECK: fctiwuz394; CHECK: stfd395; CHECK: lwz396; PPC970: fctidz397; PPC970: stfd398; PPC970: lwz399; SPE: efsctui400 store i32 %conv, ptr %b.addr, align 4401 ret void402}403 404define void @fptoui_float_i64(float %a) nounwind {405entry:406; CHECK: fptoui_float_i64407; PPC970: fptoui_float_i64408 %b.addr = alloca i64, align 4409 %conv = fptoui float %a to i64410; CHECK: fctiduz411; CHECK: stfd412; CHECK: ld413; PPC970-NOT: fctiduz414 store i64 %conv, ptr %b.addr, align 4415 ret void416}417 418define void @fptoui_double_i32(double %a) nounwind {419entry:420; CHECK: fptoui_double_i32421; PPC970: fptoui_double_i32422 %b.addr = alloca i32, align 8423 %conv = fptoui double %a to i32424; CHECK: fctiwuz425; CHECK: stfd426; CHECK: lwz427; PPC970: fctidz428; PPC970: stfd429; PPC970: lwz430; SPE: efdctui431 store i32 %conv, ptr %b.addr, align 8432 ret void433}434 435define void @fptoui_double_i64(double %a) nounwind {436entry:437; CHECK: fptoui_double_i64438; PPC970: fptoui_double_i64439 %b.addr = alloca i64, align 8440 %conv = fptoui double %a to i64441; CHECK: fctiduz442; CHECK: stfd443; CHECK: ld444; PPC970-NOT: fctiduz445 store i64 %conv, ptr %b.addr, align 8446 ret void447}448