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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \3; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s4 5define float @absf(float %a) {6; CHECK-LABEL: absf:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: xsabsdp f1, f19; CHECK-NEXT: blr10entry:11 %conv = bitcast float %a to i3212 %and = and i32 %conv, 214748364713 %conv1 = bitcast i32 %and to float14 ret float %conv115}16 17define double @absd(double %a) {18; CHECK-LABEL: absd:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: xsabsdp f1, f121; CHECK-NEXT: blr22entry:23 %conv = bitcast double %a to i6424 %and = and i64 %conv, 922337203685477580725 %conv1 = bitcast i64 %and to double26 ret double %conv127}28 29define <4 x float> @absv4f32(<4 x float> %a) {30; CHECK-LABEL: absv4f32:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: xvabssp vs34, vs3433; CHECK-NEXT: blr34entry:35 %conv = bitcast <4 x float> %a to <4 x i32>36 %and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>37 %conv1 = bitcast <4 x i32> %and to <4 x float>38 ret <4 x float> %conv139}40 41define <4 x float> @absv4f32_wundef(<4 x float> %a) {42; CHECK-LABEL: absv4f32_wundef:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: xvabssp vs34, vs3445; CHECK-NEXT: blr46entry:47 %conv = bitcast <4 x float> %a to <4 x i32>48 %and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647>49 %conv1 = bitcast <4 x i32> %and to <4 x float>50 ret <4 x float> %conv151}52 53define <4 x float> @absv4f32_invalid(<4 x float> %a) {54; CHECK-LABEL: absv4f32_invalid:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha57; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l58; CHECK-NEXT: lxvd2x vs0, 0, r359; CHECK-NEXT: xxswapd vs35, vs060; CHECK-NEXT: xxland vs34, vs34, vs3561; CHECK-NEXT: blr62entry:63 %conv = bitcast <4 x float> %a to <4 x i32>64 %and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647>65 %conv1 = bitcast <4 x i32> %and to <4 x float>66 ret <4 x float> %conv167}68 69define <2 x double> @absv2f64(<2 x double> %a) {70; CHECK-LABEL: absv2f64:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: xvabsdp vs34, vs3473; CHECK-NEXT: blr74entry:75 %conv = bitcast <2 x double> %a to <2 x i64>76 %and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807>77 %conv1 = bitcast <2 x i64> %and to <2 x double>78 ret <2 x double> %conv179}80 81define float @negf(float %a) {82; CHECK-LABEL: negf:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: xsnegdp f1, f185; CHECK-NEXT: blr86entry:87 %conv = bitcast float %a to i3288 %and = xor i32 %conv, -214748364889 %conv1 = bitcast i32 %and to float90 ret float %conv191}92 93define double @negd(double %a) {94; CHECK-LABEL: negd:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: xsnegdp f1, f197; CHECK-NEXT: blr98entry:99 %conv = bitcast double %a to i64100 %and = xor i64 %conv, -9223372036854775808101 %conv1 = bitcast i64 %and to double102 ret double %conv1103}104 105define <4 x float> @negv4f32(<4 x float> %a) {106; CHECK-LABEL: negv4f32:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: xvnegsp vs34, vs34109; CHECK-NEXT: blr110entry:111 %conv = bitcast <4 x float> %a to <4 x i32>112 %and = xor <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>113 %conv1 = bitcast <4 x i32> %and to <4 x float>114 ret <4 x float> %conv1115}116 117define <2 x double> @negv2d64(<2 x double> %a) {118; CHECK-LABEL: negv2d64:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: xvnegdp vs34, vs34121; CHECK-NEXT: blr122entry:123 %conv = bitcast <2 x double> %a to <2 x i64>124 %and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>125 %conv1 = bitcast <2 x i64> %and to <2 x double>126 ret <2 x double> %conv1127}128define float @nabsf(float %a) {129; CHECK-LABEL: nabsf:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: xsnabsdp f1, f1132; CHECK-NEXT: blr133entry:134 %conv = bitcast float %a to i32135 %and = or i32 %conv, -2147483648136 %conv1 = bitcast i32 %and to float137 ret float %conv1138}139 140define double @nabsd(double %a) {141; CHECK-LABEL: nabsd:142; CHECK: # %bb.0: # %entry143; CHECK-NEXT: xsnabsdp f1, f1144; CHECK-NEXT: blr145entry:146 %conv = bitcast double %a to i64147 %and = or i64 %conv, -9223372036854775808148 %conv1 = bitcast i64 %and to double149 ret double %conv1150}151 152define <4 x float> @nabsv4f32(<4 x float> %a) {153; CHECK-LABEL: nabsv4f32:154; CHECK: # %bb.0: # %entry155; CHECK-NEXT: xvnabssp vs34, vs34156; CHECK-NEXT: blr157entry:158 %conv = bitcast <4 x float> %a to <4 x i32>159 %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>160 %conv1 = bitcast <4 x i32> %and to <4 x float>161 ret <4 x float> %conv1162}163 164define <2 x double> @nabsv2d64(<2 x double> %a) {165; CHECK-LABEL: nabsv2d64:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: xvnabsdp vs34, vs34168; CHECK-NEXT: blr169entry:170 %conv = bitcast <2 x double> %a to <2 x i64>171 %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808>172 %conv1 = bitcast <2 x i64> %and to <2 x double>173 ret <2 x double> %conv1174}175 176