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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \2; RUN: -mcpu=a2 | FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \4; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s5; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=g57; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \8; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck -check-prefix=CHECK-P9 %s9target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"10target triple = "powerpc64-unknown-linux-gnu"11 12define i64 @foo(float %a) nounwind {13 %x = fptosi float %a to i6414 ret i64 %x15 16; CHECK: @foo17; CHECK: fctidz [[REG:[0-9]+]], 118; CHECK: stfd [[REG]],19; CHECK: ld 3,20; CHECK: blr21 22; CHECK-VSX: @foo23; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 124; CHECK-VSX: stfd [[REG]],25; CHECK-VSX: ld 3,26; CHECK-VSX: blr27 28; CHECK-P9-LABEL: @foo29; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 130; CHECK-P9: stfd [[REG]],31; CHECK-P9: ld 3,32; CHECK-P9: blr33}34 35define i64 @foo2(double %a) nounwind {36 %x = fptosi double %a to i6437 ret i64 %x38 39; CHECK: @foo240; CHECK: fctidz [[REG:[0-9]+]], 141; CHECK: stfd [[REG]],42; CHECK: ld 3,43; CHECK: blr44 45; CHECK-VSX: @foo246; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 147; CHECK-VSX: stfd [[REG]],48; CHECK-VSX: ld 3,49; CHECK-VSX: blr50 51; CHECK-P9-LABEL: @foo252; CHECK-P9: xscvdpsxds [[REG:[0-9]+]], 153; CHECK-P9: stfd [[REG]],54; CHECK-P9: ld 3,55; CHECK-P9: blr56}57 58define i64 @foo3(float %a) nounwind {59 %x = fptoui float %a to i6460 ret i64 %x61 62; CHECK: @foo363; CHECK: fctiduz [[REG:[0-9]+]], 164; CHECK: stfd [[REG]],65; CHECK: ld 3,66; CHECK: blr67 68; CHECK-VSX: @foo369; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 170; CHECK-VSX: stfd [[REG]],71; CHECK-VSX: ld 3,72; CHECK-VSX: blr73 74; CHECK-P9-LABEL: @foo375; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 176; CHECK-P9: stfd [[REG]],77; CHECK-P9: ld 3,78; CHECK-P9: blr79}80 81define i64 @foo4(double %a) nounwind {82 %x = fptoui double %a to i6483 ret i64 %x84 85; CHECK: @foo486; CHECK: fctiduz [[REG:[0-9]+]], 187; CHECK: stfd [[REG]],88; CHECK: ld 3,89; CHECK: blr90 91; CHECK-VSX: @foo492; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 193; CHECK-VSX: stfd [[REG]],94; CHECK-VSX: ld 3,95; CHECK-VSX: blr96 97; CHECK-P9-LABEL: @foo498; CHECK-P9: xscvdpuxds [[REG:[0-9]+]], 199; CHECK-P9: stfd [[REG]],100; CHECK-P9: ld 3,101; CHECK-P9: blr102}103 104define i32 @goo(float %a) nounwind {105 %x = fptosi float %a to i32106 ret i32 %x107 108; CHECK: @goo109; CHECK: fctiwz [[REG:[0-9]+]], 1110; CHECK: stfiwx [[REG]],111; CHECK: lwz 3,112; CHECK: blr113 114; CHECK-VSX: @goo115; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1116; CHECK-VSX: stfiwx [[REG]],117; CHECK-VSX: lwz 3,118; CHECK-VSX: blr119}120 121define i32 @goo2(double %a) nounwind {122 %x = fptosi double %a to i32123 ret i32 %x124 125; CHECK: @goo2126; CHECK: fctiwz [[REG:[0-9]+]], 1127; CHECK: stfiwx [[REG]],128; CHECK: lwz 3,129; CHECK: blr130 131; CHECK-VSX: @goo2132; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1133; CHECK-VSX: stfiwx [[REG]],134; CHECK-VSX: lwz 3,135; CHECK-VSX: blr136}137 138define i32 @goo3(float %a) nounwind {139 %x = fptoui float %a to i32140 ret i32 %x141 142; CHECK: @goo3143; CHECK: fctiwuz [[REG:[0-9]+]], 1144; CHECK: stfiwx [[REG]],145; CHECK: lwz 3,146; CHECK: blr147 148; CHECK-VSX: @goo3149; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1150; CHECK-VSX: stfiwx [[REG]],151; CHECK-VSX: lwz 3,152; CHECK-VSX: blr153}154 155define i32 @goo4(double %a) nounwind {156 %x = fptoui double %a to i32157 ret i32 %x158 159; CHECK: @goo4160; CHECK: fctiwuz [[REG:[0-9]+]], 1161; CHECK: stfiwx [[REG]],162; CHECK: lwz 3,163; CHECK: blr164 165; CHECK-VSX: @goo4166; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1167; CHECK-VSX: stfiwx [[REG]],168; CHECK-VSX: lwz 3,169; CHECK-VSX: blr170}171 172