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1; NOTE: This test ensures that, for both Big and Little Endian cases, a set of2; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \4; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \5; RUN: | FileCheck %s -check-prefix=CHECK-LE6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \7; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \8; RUN: | FileCheck %s -check-prefix=CHECK-BE9; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \10; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff < %s \11; RUN: | FileCheck %s -check-prefix=CHECK-BE12; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \13; RUN: -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff < %s \14; RUN: | FileCheck %s -check-prefix=CHECK-BE-AIX-3215define dso_local <4 x float> @vector_gatherf(ptr nocapture readonly %a,16ptr nocapture readonly %b, ptr nocapture readonly %c,17ptr nocapture readonly %d) {18; C code from which this IR test case was generated:19; vector float test(ptr a, ptr b, ptr c, ptr d) {20; return (vector float) { *a, *b, *c, *d };21; }22; CHECK-LE-LABEL: vector_gatherf:23; CHECK-LE: # %bb.0: # %entry24; CHECK-LE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r625; CHECK-LE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r526; CHECK-LE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r427; CHECK-LE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r328; CHECK-LE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]29; CHECK-LE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]30; CHECK-LE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]31; CHECK-LE-NEXT: blr32 33; CHECK-BE-LABEL: vector_gatherf:34; CHECK-BE: # %bb.0: # %entry35; CHECK-BE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r336; CHECK-BE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r437; CHECK-BE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r538; CHECK-BE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r639; CHECK-BE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]40; CHECK-BE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]41; CHECK-BE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]42; CHECK-BE-NEXT: blr43 44; CHECK-BE-AIX-32-LABEL: vector_gatherf:45; CHECK-BE-AIX-32-LABEL: # %bb.0: # %entry46; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG0:[0-9]+]]47; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG1:[0-9]+]]48; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG2:[0-9]+]]49; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG3:[0-9]+]]50; CHECK-BE-AIX-32-DAG: vmrgow v[[REG0]], v[[REG1]], v[[REG0]]51; CHECK-BE-AIX-32-DAG: vmrgow v[[REG3]], v[[REG2]], v[[REG3]]52; CHECK-BE-AIX-32-NEXT: xxmrghd v[[REG0]], v[[REG3]], v[[REG0]]53; CHECK-BE-AIX-32-NEXT: blr54entry:55 %0 = load float, ptr %a, align 456 %vecinit = insertelement <4 x float> undef, float %0, i32 057 %1 = load float, ptr %b, align 458 %vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 159 %2 = load float, ptr %c, align 460 %vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 261 %3 = load float, ptr %d, align 462 %vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 363 ret <4 x float> %vecinit364}65 66