992 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast \3; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -fp-contract=fast \5; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s6; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \8; RUN: -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s9; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff \10; RUN: -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \11; RUN: -mcpu=pwr7 -vec-extabi | FileCheck -check-prefix=CHECK-VSX %s12; RUN: llc -verify-machineinstrs < %s -mtriple=powerpcspe-linux-unknown-gnu \13; RUN: | FileCheck -check-prefix=CHECK-SPE %s14 15define double @test_FMADD_ASSOC1(double %A, double %B, double %C,16; CHECK-LABEL: test_FMADD_ASSOC1:17; CHECK: # %bb.0:18; CHECK-NEXT: fmul 0, 3, 419; CHECK-NEXT: fmadd 0, 1, 2, 020; CHECK-NEXT: fadd 1, 0, 521; CHECK-NEXT: blr22;23; CHECK-VSX-LABEL: test_FMADD_ASSOC1:24; CHECK-VSX: # %bb.0:25; CHECK-VSX-NEXT: xsmuldp 0, 3, 426; CHECK-VSX-NEXT: xsmaddadp 0, 1, 227; CHECK-VSX-NEXT: xsadddp 1, 0, 528; CHECK-VSX-NEXT: blr29;30; CHECK-SPE-LABEL: test_FMADD_ASSOC1:31; CHECK-SPE: # %bb.0:32; CHECK-SPE-NEXT: evmergelo 9, 9, 1033; CHECK-SPE-NEXT: evmergelo 7, 7, 834; CHECK-SPE-NEXT: evmergelo 5, 5, 635; CHECK-SPE-NEXT: evmergelo 3, 3, 436; CHECK-SPE-NEXT: efdmul 4, 7, 937; CHECK-SPE-NEXT: efdmul 3, 3, 538; CHECK-SPE-NEXT: evldd 5, 8(1)39; CHECK-SPE-NEXT: efdadd 3, 3, 440; CHECK-SPE-NEXT: efdadd 4, 3, 541; CHECK-SPE-NEXT: evmergehi 3, 4, 442; CHECK-SPE-NEXT: blr43 double %D, double %E) {44 %F = fmul double %A, %B ; <double> [#uses=1]45 %G = fmul double %C, %D ; <double> [#uses=1]46 %H = fadd double %F, %G ; <double> [#uses=1]47 %I = fadd double %H, %E ; <double> [#uses=1]48 ret double %I49}50 51define double @test_FMADD_ASSOC2(double %A, double %B, double %C,52; CHECK-LABEL: test_FMADD_ASSOC2:53; CHECK: # %bb.0:54; CHECK-NEXT: fmul 0, 3, 455; CHECK-NEXT: fmadd 0, 1, 2, 056; CHECK-NEXT: fadd 1, 5, 057; CHECK-NEXT: blr58;59; CHECK-VSX-LABEL: test_FMADD_ASSOC2:60; CHECK-VSX: # %bb.0:61; CHECK-VSX-NEXT: xsmuldp 0, 3, 462; CHECK-VSX-NEXT: xsmaddadp 0, 1, 263; CHECK-VSX-NEXT: xsadddp 1, 5, 064; CHECK-VSX-NEXT: blr65;66; CHECK-SPE-LABEL: test_FMADD_ASSOC2:67; CHECK-SPE: # %bb.0:68; CHECK-SPE-NEXT: evmergelo 9, 9, 1069; CHECK-SPE-NEXT: evmergelo 7, 7, 870; CHECK-SPE-NEXT: evmergelo 5, 5, 671; CHECK-SPE-NEXT: evmergelo 3, 3, 472; CHECK-SPE-NEXT: efdmul 4, 7, 973; CHECK-SPE-NEXT: efdmul 3, 3, 574; CHECK-SPE-NEXT: evldd 5, 8(1)75; CHECK-SPE-NEXT: efdadd 3, 3, 476; CHECK-SPE-NEXT: efdadd 4, 5, 377; CHECK-SPE-NEXT: evmergehi 3, 4, 478; CHECK-SPE-NEXT: blr79 double %D, double %E) {80 %F = fmul double %A, %B ; <double> [#uses=1]81 %G = fmul double %C, %D ; <double> [#uses=1]82 %H = fadd double %F, %G ; <double> [#uses=1]83 %I = fadd double %E, %H ; <double> [#uses=1]84 ret double %I85}86 87define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,88; CHECK-LABEL: test_FMSUB_ASSOC1:89; CHECK: # %bb.0:90; CHECK-NEXT: fmul 0, 3, 491; CHECK-NEXT: fmadd 0, 1, 2, 092; CHECK-NEXT: fsub 1, 0, 593; CHECK-NEXT: blr94;95; CHECK-VSX-LABEL: test_FMSUB_ASSOC1:96; CHECK-VSX: # %bb.0:97; CHECK-VSX-NEXT: xsmuldp 0, 3, 498; CHECK-VSX-NEXT: xsmaddadp 0, 1, 299; CHECK-VSX-NEXT: xssubdp 1, 0, 5100; CHECK-VSX-NEXT: blr101;102; CHECK-SPE-LABEL: test_FMSUB_ASSOC1:103; CHECK-SPE: # %bb.0:104; CHECK-SPE-NEXT: evmergelo 9, 9, 10105; CHECK-SPE-NEXT: evmergelo 7, 7, 8106; CHECK-SPE-NEXT: evmergelo 5, 5, 6107; CHECK-SPE-NEXT: evmergelo 3, 3, 4108; CHECK-SPE-NEXT: efdmul 4, 7, 9109; CHECK-SPE-NEXT: efdmul 3, 3, 5110; CHECK-SPE-NEXT: evldd 5, 8(1)111; CHECK-SPE-NEXT: efdadd 3, 3, 4112; CHECK-SPE-NEXT: efdsub 4, 3, 5113; CHECK-SPE-NEXT: evmergehi 3, 4, 4114; CHECK-SPE-NEXT: blr115 double %D, double %E) {116 %F = fmul double %A, %B ; <double> [#uses=1]117 %G = fmul double %C, %D ; <double> [#uses=1]118 %H = fadd double %F, %G ; <double> [#uses=1]119 %I = fsub double %H, %E ; <double> [#uses=1]120 ret double %I121}122 123define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,124; CHECK-LABEL: test_FMSUB_ASSOC2:125; CHECK: # %bb.0:126; CHECK-NEXT: fmul 0, 3, 4127; CHECK-NEXT: fmadd 0, 1, 2, 0128; CHECK-NEXT: fsub 1, 5, 0129; CHECK-NEXT: blr130;131; CHECK-VSX-LABEL: test_FMSUB_ASSOC2:132; CHECK-VSX: # %bb.0:133; CHECK-VSX-NEXT: xsmuldp 0, 3, 4134; CHECK-VSX-NEXT: xsmaddadp 0, 1, 2135; CHECK-VSX-NEXT: xssubdp 1, 5, 0136; CHECK-VSX-NEXT: blr137;138; CHECK-SPE-LABEL: test_FMSUB_ASSOC2:139; CHECK-SPE: # %bb.0:140; CHECK-SPE-NEXT: evmergelo 9, 9, 10141; CHECK-SPE-NEXT: evmergelo 7, 7, 8142; CHECK-SPE-NEXT: evmergelo 5, 5, 6143; CHECK-SPE-NEXT: evmergelo 3, 3, 4144; CHECK-SPE-NEXT: efdmul 4, 7, 9145; CHECK-SPE-NEXT: efdmul 3, 3, 5146; CHECK-SPE-NEXT: evldd 5, 8(1)147; CHECK-SPE-NEXT: efdadd 3, 3, 4148; CHECK-SPE-NEXT: efdsub 4, 5, 3149; CHECK-SPE-NEXT: evmergehi 3, 4, 4150; CHECK-SPE-NEXT: blr151 double %D, double %E) {152 %F = fmul double %A, %B ; <double> [#uses=1]153 %G = fmul double %C, %D ; <double> [#uses=1]154 %H = fadd double %F, %G ; <double> [#uses=1]155 %I = fsub double %E, %H ; <double> [#uses=1]156 ret double %I157}158 159define double @test_FMADD_ASSOC_EXT1(float %A, float %B, double %C,160; CHECK-LABEL: test_FMADD_ASSOC_EXT1:161; CHECK: # %bb.0:162; CHECK-NEXT: fmadd 0, 1, 2, 5163; CHECK-NEXT: fmadd 1, 3, 4, 0164; CHECK-NEXT: blr165;166; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT1:167; CHECK-VSX: # %bb.0:168; CHECK-VSX-NEXT: xsmaddmdp 1, 2, 5169; CHECK-VSX-NEXT: xsmaddadp 1, 3, 4170; CHECK-VSX-NEXT: blr171;172; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT1:173; CHECK-SPE: # %bb.0:174; CHECK-SPE-NEXT: efsmul 3, 3, 4175; CHECK-SPE-NEXT: evmergelo 4, 9, 10176; CHECK-SPE-NEXT: evmergelo 7, 7, 8177; CHECK-SPE-NEXT: efdcfs 3, 3178; CHECK-SPE-NEXT: evmergelo 5, 5, 6179; CHECK-SPE-NEXT: efdmul 5, 5, 7180; CHECK-SPE-NEXT: efdadd 3, 5, 3181; CHECK-SPE-NEXT: efdadd 4, 3, 4182; CHECK-SPE-NEXT: evmergehi 3, 4, 4183; CHECK-SPE-NEXT: blr184 double %D, double %E) {185 %F = fmul float %A, %B ; <float> [#uses=1]186 %G = fpext float %F to double ; <double> [#uses=1]187 %H = fmul double %C, %D ; <double> [#uses=1]188 %I = fadd double %H, %G ; <double> [#uses=1]189 %J = fadd double %I, %E ; <double> [#uses=1]190 ret double %J191}192 193define double @test_FMADD_ASSOC_EXT2(float %A, float %B, float %C,194; CHECK-LABEL: test_FMADD_ASSOC_EXT2:195; CHECK: # %bb.0:196; CHECK-NEXT: fmadd 0, 3, 4, 5197; CHECK-NEXT: fmadd 1, 1, 2, 0198; CHECK-NEXT: blr199;200; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT2:201; CHECK-VSX: # %bb.0:202; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5203; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2204; CHECK-VSX-NEXT: fmr 1, 3205; CHECK-VSX-NEXT: blr206;207; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT2:208; CHECK-SPE: # %bb.0:209; CHECK-SPE-NEXT: efsmul 3, 3, 4210; CHECK-SPE-NEXT: efsmul 4, 5, 6211; CHECK-SPE-NEXT: efsadd 3, 3, 4212; CHECK-SPE-NEXT: evmergelo 4, 7, 8213; CHECK-SPE-NEXT: efdcfs 3, 3214; CHECK-SPE-NEXT: efdadd 4, 3, 4215; CHECK-SPE-NEXT: evmergehi 3, 4, 4216; CHECK-SPE-NEXT: blr217 float %D, double %E) {218 %F = fmul float %A, %B ; <float> [#uses=1]219 %G = fmul float %C, %D ; <float> [#uses=1]220 %H = fadd float %F, %G ; <float> [#uses=1]221 %I = fpext float %H to double ; <double> [#uses=1]222 %J = fadd double %I, %E ; <double> [#uses=1]223 ret double %J224}225 226define double @test_FMADD_ASSOC_EXT3(float %A, float %B, double %C,227; CHECK-LABEL: test_FMADD_ASSOC_EXT3:228; CHECK: # %bb.0:229; CHECK-NEXT: fmadd 0, 1, 2, 5230; CHECK-NEXT: fmadd 1, 3, 4, 0231; CHECK-NEXT: blr232;233; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT3:234; CHECK-VSX: # %bb.0:235; CHECK-VSX-NEXT: xsmaddmdp 1, 2, 5236; CHECK-VSX-NEXT: xsmaddadp 1, 3, 4237; CHECK-VSX-NEXT: blr238;239; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT3:240; CHECK-SPE: # %bb.0:241; CHECK-SPE-NEXT: efsmul 3, 3, 4242; CHECK-SPE-NEXT: evmergelo 4, 9, 10243; CHECK-SPE-NEXT: evmergelo 7, 7, 8244; CHECK-SPE-NEXT: efdcfs 3, 3245; CHECK-SPE-NEXT: evmergelo 5, 5, 6246; CHECK-SPE-NEXT: efdmul 5, 5, 7247; CHECK-SPE-NEXT: efdadd 3, 5, 3248; CHECK-SPE-NEXT: efdadd 4, 4, 3249; CHECK-SPE-NEXT: evmergehi 3, 4, 4250; CHECK-SPE-NEXT: blr251 double %D, double %E) {252 %F = fmul float %A, %B ; <float> [#uses=1]253 %G = fpext float %F to double ; <double> [#uses=1]254 %H = fmul double %C, %D ; <double> [#uses=1]255 %I = fadd double %H, %G ; <double> [#uses=1]256 %J = fadd double %E, %I ; <double> [#uses=1]257 ret double %J258}259 260define double @test_FMADD_ASSOC_EXT4(float %A, float %B, float %C,261; CHECK-LABEL: test_FMADD_ASSOC_EXT4:262; CHECK: # %bb.0:263; CHECK-NEXT: fmadd 0, 3, 4, 5264; CHECK-NEXT: fmadd 1, 1, 2, 0265; CHECK-NEXT: blr266;267; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT4:268; CHECK-VSX: # %bb.0:269; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5270; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2271; CHECK-VSX-NEXT: fmr 1, 3272; CHECK-VSX-NEXT: blr273;274; CHECK-SPE-LABEL: test_FMADD_ASSOC_EXT4:275; CHECK-SPE: # %bb.0:276; CHECK-SPE-NEXT: efsmul 3, 3, 4277; CHECK-SPE-NEXT: efsmul 4, 5, 6278; CHECK-SPE-NEXT: efsadd 3, 3, 4279; CHECK-SPE-NEXT: evmergelo 4, 7, 8280; CHECK-SPE-NEXT: efdcfs 3, 3281; CHECK-SPE-NEXT: efdadd 4, 4, 3282; CHECK-SPE-NEXT: evmergehi 3, 4, 4283; CHECK-SPE-NEXT: blr284 float %D, double %E) {285 %F = fmul float %A, %B ; <float> [#uses=1]286 %G = fmul float %C, %D ; <float> [#uses=1]287 %H = fadd float %F, %G ; <float> [#uses=1]288 %I = fpext float %H to double ; <double> [#uses=1]289 %J = fadd double %E, %I ; <double> [#uses=1]290 ret double %J291}292 293define double @test_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,294; CHECK-LABEL: test_FMSUB_ASSOC_EXT1:295; CHECK: # %bb.0:296; CHECK-NEXT: fmuls 0, 1, 2297; CHECK-NEXT: fmadd 0, 3, 4, 0298; CHECK-NEXT: fsub 1, 0, 5299; CHECK-NEXT: blr300;301; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT1:302; CHECK-VSX: # %bb.0:303; CHECK-VSX-NEXT: fmuls 0, 1, 2304; CHECK-VSX-NEXT: xsmaddadp 0, 3, 4305; CHECK-VSX-NEXT: xssubdp 1, 0, 5306; CHECK-VSX-NEXT: blr307;308; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT1:309; CHECK-SPE: # %bb.0:310; CHECK-SPE-NEXT: efsmul 3, 3, 4311; CHECK-SPE-NEXT: evmergelo 4, 9, 10312; CHECK-SPE-NEXT: evmergelo 7, 7, 8313; CHECK-SPE-NEXT: efdcfs 3, 3314; CHECK-SPE-NEXT: evmergelo 5, 5, 6315; CHECK-SPE-NEXT: efdmul 5, 5, 7316; CHECK-SPE-NEXT: efdadd 3, 5, 3317; CHECK-SPE-NEXT: efdsub 4, 3, 4318; CHECK-SPE-NEXT: evmergehi 3, 4, 4319; CHECK-SPE-NEXT: blr320 double %D, double %E) {321 %F = fmul float %A, %B ; <float> [#uses=1]322 %G = fpext float %F to double ; <double> [#uses=1]323 %H = fmul double %C, %D ; <double> [#uses=1]324 %I = fadd double %H, %G ; <double> [#uses=1]325 %J = fsub double %I, %E ; <double> [#uses=1]326 ret double %J327}328 329define double @test_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,330; CHECK-LABEL: test_FMSUB_ASSOC_EXT2:331; CHECK: # %bb.0:332; CHECK-NEXT: fmuls 0, 3, 4333; CHECK-NEXT: fmadds 0, 1, 2, 0334; CHECK-NEXT: fsub 1, 0, 5335; CHECK-NEXT: blr336;337; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT2:338; CHECK-VSX: # %bb.0:339; CHECK-VSX-NEXT: fmuls 0, 3, 4340; CHECK-VSX-NEXT: fmadds 0, 1, 2, 0341; CHECK-VSX-NEXT: xssubdp 1, 0, 5342; CHECK-VSX-NEXT: blr343;344; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT2:345; CHECK-SPE: # %bb.0:346; CHECK-SPE-NEXT: efsmul 3, 3, 4347; CHECK-SPE-NEXT: efsmul 4, 5, 6348; CHECK-SPE-NEXT: efsadd 3, 3, 4349; CHECK-SPE-NEXT: evmergelo 4, 7, 8350; CHECK-SPE-NEXT: efdcfs 3, 3351; CHECK-SPE-NEXT: efdsub 4, 3, 4352; CHECK-SPE-NEXT: evmergehi 3, 4, 4353; CHECK-SPE-NEXT: blr354 float %D, double %E) {355 %F = fmul float %A, %B ; <float> [#uses=1]356 %G = fmul float %C, %D ; <float> [#uses=1]357 %H = fadd float %F, %G ; <float> [#uses=1]358 %I = fpext float %H to double ; <double> [#uses=1]359 %J = fsub double %I, %E ; <double> [#uses=1]360 ret double %J361}362 363define double @test_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,364; CHECK-LABEL: test_FMSUB_ASSOC_EXT3:365; CHECK: # %bb.0:366; CHECK-NEXT: fmuls 0, 1, 2367; CHECK-NEXT: fmadd 0, 3, 4, 0368; CHECK-NEXT: fsub 1, 5, 0369; CHECK-NEXT: blr370;371; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT3:372; CHECK-VSX: # %bb.0:373; CHECK-VSX-NEXT: fmuls 0, 1, 2374; CHECK-VSX-NEXT: xsmaddadp 0, 3, 4375; CHECK-VSX-NEXT: xssubdp 1, 5, 0376; CHECK-VSX-NEXT: blr377;378; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT3:379; CHECK-SPE: # %bb.0:380; CHECK-SPE-NEXT: efsmul 3, 3, 4381; CHECK-SPE-NEXT: evmergelo 4, 9, 10382; CHECK-SPE-NEXT: evmergelo 7, 7, 8383; CHECK-SPE-NEXT: efdcfs 3, 3384; CHECK-SPE-NEXT: evmergelo 5, 5, 6385; CHECK-SPE-NEXT: efdmul 5, 5, 7386; CHECK-SPE-NEXT: efdadd 3, 5, 3387; CHECK-SPE-NEXT: efdsub 4, 4, 3388; CHECK-SPE-NEXT: evmergehi 3, 4, 4389; CHECK-SPE-NEXT: blr390 double %D, double %E) {391 %F = fmul float %A, %B ; <float> [#uses=1]392 %G = fpext float %F to double ; <double> [#uses=1]393 %H = fmul double %C, %D ; <double> [#uses=1]394 %I = fadd double %H, %G ; <double> [#uses=1]395 %J = fsub double %E, %I ; <double> [#uses=1]396 ret double %J397}398 399define double @test_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,400; CHECK-LABEL: test_FMSUB_ASSOC_EXT4:401; CHECK: # %bb.0:402; CHECK-NEXT: fmuls 0, 3, 4403; CHECK-NEXT: fmadds 0, 1, 2, 0404; CHECK-NEXT: fsub 1, 5, 0405; CHECK-NEXT: blr406;407; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT4:408; CHECK-VSX: # %bb.0:409; CHECK-VSX-NEXT: fmuls 0, 3, 4410; CHECK-VSX-NEXT: fmadds 0, 1, 2, 0411; CHECK-VSX-NEXT: xssubdp 1, 5, 0412; CHECK-VSX-NEXT: blr413;414; CHECK-SPE-LABEL: test_FMSUB_ASSOC_EXT4:415; CHECK-SPE: # %bb.0:416; CHECK-SPE-NEXT: efsmul 3, 3, 4417; CHECK-SPE-NEXT: efsmul 4, 5, 6418; CHECK-SPE-NEXT: efsadd 3, 3, 4419; CHECK-SPE-NEXT: evmergelo 4, 7, 8420; CHECK-SPE-NEXT: efdcfs 3, 3421; CHECK-SPE-NEXT: efdsub 4, 4, 3422; CHECK-SPE-NEXT: evmergehi 3, 4, 4423; CHECK-SPE-NEXT: blr424 float %D, double %E) {425 %F = fmul float %A, %B ; <float> [#uses=1]426 %G = fmul float %C, %D ; <float> [#uses=1]427 %H = fadd float %F, %G ; <float> [#uses=1]428 %I = fpext float %H to double ; <double> [#uses=1]429 %J = fsub double %E, %I ; <double> [#uses=1]430 ret double %J431}432 433define double @test_reassoc_FMADD_ASSOC1(double %A, double %B, double %C,434; CHECK-LABEL: test_reassoc_FMADD_ASSOC1:435; CHECK: # %bb.0:436; CHECK-NEXT: fmadd 0, 3, 4, 5437; CHECK-NEXT: fmadd 1, 1, 2, 0438; CHECK-NEXT: blr439;440; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC1:441; CHECK-VSX: # %bb.0:442; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5443; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2444; CHECK-VSX-NEXT: fmr 1, 3445; CHECK-VSX-NEXT: blr446;447; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC1:448; CHECK-SPE: # %bb.0:449; CHECK-SPE-NEXT: evmergelo 9, 9, 10450; CHECK-SPE-NEXT: evmergelo 7, 7, 8451; CHECK-SPE-NEXT: evmergelo 5, 5, 6452; CHECK-SPE-NEXT: evmergelo 3, 3, 4453; CHECK-SPE-NEXT: efdmul 4, 7, 9454; CHECK-SPE-NEXT: efdmul 3, 3, 5455; CHECK-SPE-NEXT: evldd 5, 8(1)456; CHECK-SPE-NEXT: efdadd 3, 3, 4457; CHECK-SPE-NEXT: efdadd 4, 3, 5458; CHECK-SPE-NEXT: evmergehi 3, 4, 4459; CHECK-SPE-NEXT: blr460 double %D, double %E) {461 %F = fmul reassoc double %A, %B ; <double> [#uses=1]462 %G = fmul reassoc double %C, %D ; <double> [#uses=1]463 %H = fadd reassoc double %F, %G ; <double> [#uses=1]464 %I = fadd reassoc double %H, %E ; <double> [#uses=1]465 ret double %I466}467 468define double @test_reassoc_FMADD_ASSOC2(double %A, double %B, double %C,469; CHECK-LABEL: test_reassoc_FMADD_ASSOC2:470; CHECK: # %bb.0:471; CHECK-NEXT: fmadd 0, 3, 4, 5472; CHECK-NEXT: fmadd 1, 1, 2, 0473; CHECK-NEXT: blr474;475; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC2:476; CHECK-VSX: # %bb.0:477; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5478; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2479; CHECK-VSX-NEXT: fmr 1, 3480; CHECK-VSX-NEXT: blr481;482; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC2:483; CHECK-SPE: # %bb.0:484; CHECK-SPE-NEXT: evmergelo 9, 9, 10485; CHECK-SPE-NEXT: evmergelo 7, 7, 8486; CHECK-SPE-NEXT: evmergelo 5, 5, 6487; CHECK-SPE-NEXT: evmergelo 3, 3, 4488; CHECK-SPE-NEXT: efdmul 4, 7, 9489; CHECK-SPE-NEXT: efdmul 3, 3, 5490; CHECK-SPE-NEXT: evldd 5, 8(1)491; CHECK-SPE-NEXT: efdadd 3, 3, 4492; CHECK-SPE-NEXT: efdadd 4, 5, 3493; CHECK-SPE-NEXT: evmergehi 3, 4, 4494; CHECK-SPE-NEXT: blr495 double %D, double %E) {496 %F = fmul reassoc double %A, %B ; <double> [#uses=1]497 %G = fmul reassoc double %C, %D ; <double> [#uses=1]498 %H = fadd reassoc double %F, %G ; <double> [#uses=1]499 %I = fadd reassoc double %E, %H ; <double> [#uses=1]500 ret double %I501}502 503; FIXME: -ffp-contract=fast does NOT work here?504define double @test_reassoc_FMSUB_ASSOC1(double %A, double %B, double %C,505; CHECK-LABEL: test_reassoc_FMSUB_ASSOC1:506; CHECK: # %bb.0:507; CHECK-NEXT: fmul 0, 3, 4508; CHECK-NEXT: fmadd 0, 1, 2, 0509; CHECK-NEXT: fsub 1, 0, 5510; CHECK-NEXT: blr511;512; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC1:513; CHECK-VSX: # %bb.0:514; CHECK-VSX-NEXT: xsmuldp 0, 3, 4515; CHECK-VSX-NEXT: xsmaddadp 0, 1, 2516; CHECK-VSX-NEXT: xssubdp 1, 0, 5517; CHECK-VSX-NEXT: blr518;519; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC1:520; CHECK-SPE: # %bb.0:521; CHECK-SPE-NEXT: evmergelo 9, 9, 10522; CHECK-SPE-NEXT: evmergelo 7, 7, 8523; CHECK-SPE-NEXT: evmergelo 5, 5, 6524; CHECK-SPE-NEXT: evmergelo 3, 3, 4525; CHECK-SPE-NEXT: efdmul 4, 7, 9526; CHECK-SPE-NEXT: efdmul 3, 3, 5527; CHECK-SPE-NEXT: evldd 5, 8(1)528; CHECK-SPE-NEXT: efdadd 3, 3, 4529; CHECK-SPE-NEXT: efdsub 4, 3, 5530; CHECK-SPE-NEXT: evmergehi 3, 4, 4531; CHECK-SPE-NEXT: blr532 double %D, double %E) {533 %F = fmul reassoc double %A, %B ; <double> [#uses=1]534 %G = fmul reassoc double %C, %D ; <double> [#uses=1]535 %H = fadd reassoc double %F, %G ; <double> [#uses=1]536 %I = fsub reassoc double %H, %E ; <double> [#uses=1]537 ret double %I538}539 540define double @test_reassoc_FMSUB_ASSOC11(double %A, double %B, double %C,541; CHECK-LABEL: test_reassoc_FMSUB_ASSOC11:542; CHECK: # %bb.0:543; CHECK-NEXT: fmsub 0, 3, 4, 5544; CHECK-NEXT: fmadd 1, 1, 2, 0545; CHECK-NEXT: blr546;547; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC11:548; CHECK-VSX: # %bb.0:549; CHECK-VSX-NEXT: xsmsubmdp 3, 4, 5550; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2551; CHECK-VSX-NEXT: fmr 1, 3552; CHECK-VSX-NEXT: blr553;554; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC11:555; CHECK-SPE: # %bb.0:556; CHECK-SPE-NEXT: evmergelo 9, 9, 10557; CHECK-SPE-NEXT: evmergelo 7, 7, 8558; CHECK-SPE-NEXT: evmergelo 5, 5, 6559; CHECK-SPE-NEXT: evmergelo 3, 3, 4560; CHECK-SPE-NEXT: efdmul 4, 7, 9561; CHECK-SPE-NEXT: efdmul 3, 3, 5562; CHECK-SPE-NEXT: evldd 5, 8(1)563; CHECK-SPE-NEXT: efdadd 3, 3, 4564; CHECK-SPE-NEXT: efdsub 4, 3, 5565; CHECK-SPE-NEXT: evmergehi 3, 4, 4566; CHECK-SPE-NEXT: blr567 double %D, double %E) {568 %F = fmul contract reassoc double %A, %B ; <double> [#uses=1]569 %G = fmul contract reassoc double %C, %D ; <double> [#uses=1]570 %H = fadd contract reassoc double %F, %G ; <double> [#uses=1]571 %I = fsub contract reassoc double %H, %E ; <double> [#uses=1]572 ret double %I573}574 575 576define double @test_reassoc_FMSUB_ASSOC2(double %A, double %B, double %C,577; CHECK-LABEL: test_reassoc_FMSUB_ASSOC2:578; CHECK: # %bb.0:579; CHECK-NEXT: fmul 0, 3, 4580; CHECK-NEXT: fmadd 0, 1, 2, 0581; CHECK-NEXT: fsub 1, 5, 0582; CHECK-NEXT: blr583;584; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC2:585; CHECK-VSX: # %bb.0:586; CHECK-VSX-NEXT: xsmuldp 0, 3, 4587; CHECK-VSX-NEXT: xsmaddadp 0, 1, 2588; CHECK-VSX-NEXT: xssubdp 1, 5, 0589; CHECK-VSX-NEXT: blr590;591; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC2:592; CHECK-SPE: # %bb.0:593; CHECK-SPE-NEXT: evmergelo 9, 9, 10594; CHECK-SPE-NEXT: evmergelo 7, 7, 8595; CHECK-SPE-NEXT: evmergelo 5, 5, 6596; CHECK-SPE-NEXT: evmergelo 3, 3, 4597; CHECK-SPE-NEXT: efdmul 4, 7, 9598; CHECK-SPE-NEXT: efdmul 3, 3, 5599; CHECK-SPE-NEXT: evldd 5, 8(1)600; CHECK-SPE-NEXT: efdadd 3, 3, 4601; CHECK-SPE-NEXT: efdsub 4, 5, 3602; CHECK-SPE-NEXT: evmergehi 3, 4, 4603; CHECK-SPE-NEXT: blr604 double %D, double %E) {605 %F = fmul reassoc double %A, %B ; <double> [#uses=1]606 %G = fmul reassoc double %C, %D ; <double> [#uses=1]607 %H = fadd reassoc double %F, %G ; <double> [#uses=1]608 %I = fsub reassoc double %E, %H ; <double> [#uses=1]609 ret double %I610}611 612define double @test_fast_FMSUB_ASSOC2(double %A, double %B, double %C,613; CHECK-LABEL: test_fast_FMSUB_ASSOC2:614; CHECK: # %bb.0:615; CHECK-NEXT: fmul 0, 3, 4616; CHECK-NEXT: fmadd 0, 1, 2, 0617; CHECK-NEXT: fsub 1, 5, 0618; CHECK-NEXT: blr619;620; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC2:621; CHECK-VSX: # %bb.0:622; CHECK-VSX-NEXT: xsmuldp 0, 3, 4623; CHECK-VSX-NEXT: xsmaddadp 0, 1, 2624; CHECK-VSX-NEXT: xssubdp 1, 5, 0625; CHECK-VSX-NEXT: blr626;627; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC2:628; CHECK-SPE: # %bb.0:629; CHECK-SPE-NEXT: evmergelo 9, 9, 10630; CHECK-SPE-NEXT: evmergelo 7, 7, 8631; CHECK-SPE-NEXT: evmergelo 5, 5, 6632; CHECK-SPE-NEXT: evmergelo 3, 3, 4633; CHECK-SPE-NEXT: efdmul 4, 7, 9634; CHECK-SPE-NEXT: efdmul 3, 3, 5635; CHECK-SPE-NEXT: evldd 5, 8(1)636; CHECK-SPE-NEXT: efdadd 3, 3, 4637; CHECK-SPE-NEXT: efdsub 4, 5, 3638; CHECK-SPE-NEXT: evmergehi 3, 4, 4639; CHECK-SPE-NEXT: blr640 double %D, double %E) {641 %F = fmul reassoc double %A, %B ; <double> [#uses=1]642 %G = fmul reassoc double %C, %D ; <double> [#uses=1]643 %H = fadd reassoc double %F, %G ; <double> [#uses=1]644 %I = fsub reassoc nsz double %E, %H ; <double> [#uses=1]645 ret double %I646}647 648define double @test_reassoc_FMADD_ASSOC_EXT1(float %A, float %B, double %C,649; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT1:650; CHECK: # %bb.0:651; CHECK-NEXT: fmadd 0, 1, 2, 5652; CHECK-NEXT: fmadd 1, 3, 4, 0653; CHECK-NEXT: blr654;655; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT1:656; CHECK-VSX: # %bb.0:657; CHECK-VSX-NEXT: xsmaddmdp 1, 2, 5658; CHECK-VSX-NEXT: xsmaddadp 1, 3, 4659; CHECK-VSX-NEXT: blr660;661; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT1:662; CHECK-SPE: # %bb.0:663; CHECK-SPE-NEXT: efsmul 3, 3, 4664; CHECK-SPE-NEXT: evmergelo 4, 9, 10665; CHECK-SPE-NEXT: evmergelo 7, 7, 8666; CHECK-SPE-NEXT: efdcfs 3, 3667; CHECK-SPE-NEXT: evmergelo 5, 5, 6668; CHECK-SPE-NEXT: efdmul 5, 5, 7669; CHECK-SPE-NEXT: efdadd 3, 5, 3670; CHECK-SPE-NEXT: efdadd 4, 3, 4671; CHECK-SPE-NEXT: evmergehi 3, 4, 4672; CHECK-SPE-NEXT: blr673 double %D, double %E) {674 %F = fmul reassoc float %A, %B ; <float> [#uses=1]675 %G = fpext float %F to double ; <double> [#uses=1]676 %H = fmul reassoc double %C, %D ; <double> [#uses=1]677 %I = fadd reassoc double %H, %G ; <double> [#uses=1]678 %J = fadd reassoc double %I, %E ; <double> [#uses=1]679 ret double %J680}681 682define double @test_reassoc_FMADD_ASSOC_EXT2(float %A, float %B, float %C,683; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT2:684; CHECK: # %bb.0:685; CHECK-NEXT: fmadd 0, 3, 4, 5686; CHECK-NEXT: fmadd 1, 1, 2, 0687; CHECK-NEXT: blr688;689; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT2:690; CHECK-VSX: # %bb.0:691; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5692; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2693; CHECK-VSX-NEXT: fmr 1, 3694; CHECK-VSX-NEXT: blr695;696; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT2:697; CHECK-SPE: # %bb.0:698; CHECK-SPE-NEXT: efsmul 3, 3, 4699; CHECK-SPE-NEXT: efsmul 4, 5, 6700; CHECK-SPE-NEXT: efsadd 3, 3, 4701; CHECK-SPE-NEXT: evmergelo 4, 7, 8702; CHECK-SPE-NEXT: efdcfs 3, 3703; CHECK-SPE-NEXT: efdadd 4, 3, 4704; CHECK-SPE-NEXT: evmergehi 3, 4, 4705; CHECK-SPE-NEXT: blr706 float %D, double %E) {707 %F = fmul reassoc float %A, %B ; <float> [#uses=1]708 %G = fmul reassoc float %C, %D ; <float> [#uses=1]709 %H = fadd reassoc float %F, %G ; <float> [#uses=1]710 %I = fpext float %H to double ; <double> [#uses=1]711 %J = fadd reassoc double %I, %E ; <double> [#uses=1]712 ret double %J713}714 715define double @test_reassoc_FMADD_ASSOC_EXT3(float %A, float %B, double %C,716; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT3:717; CHECK: # %bb.0:718; CHECK-NEXT: fmadd 0, 1, 2, 5719; CHECK-NEXT: fmadd 1, 3, 4, 0720; CHECK-NEXT: blr721;722; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT3:723; CHECK-VSX: # %bb.0:724; CHECK-VSX-NEXT: xsmaddmdp 1, 2, 5725; CHECK-VSX-NEXT: xsmaddadp 1, 3, 4726; CHECK-VSX-NEXT: blr727;728; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT3:729; CHECK-SPE: # %bb.0:730; CHECK-SPE-NEXT: efsmul 3, 3, 4731; CHECK-SPE-NEXT: evmergelo 4, 9, 10732; CHECK-SPE-NEXT: evmergelo 7, 7, 8733; CHECK-SPE-NEXT: efdcfs 3, 3734; CHECK-SPE-NEXT: evmergelo 5, 5, 6735; CHECK-SPE-NEXT: efdmul 5, 5, 7736; CHECK-SPE-NEXT: efdadd 3, 5, 3737; CHECK-SPE-NEXT: efdadd 4, 4, 3738; CHECK-SPE-NEXT: evmergehi 3, 4, 4739; CHECK-SPE-NEXT: blr740 double %D, double %E) {741 %F = fmul reassoc float %A, %B ; <float> [#uses=1]742 %G = fpext float %F to double ; <double> [#uses=1]743 %H = fmul reassoc double %C, %D ; <double> [#uses=1]744 %I = fadd reassoc double %H, %G ; <double> [#uses=1]745 %J = fadd reassoc double %E, %I ; <double> [#uses=1]746 ret double %J747}748 749define double @test_reassoc_FMADD_ASSOC_EXT4(float %A, float %B, float %C,750; CHECK-LABEL: test_reassoc_FMADD_ASSOC_EXT4:751; CHECK: # %bb.0:752; CHECK-NEXT: fmadd 0, 3, 4, 5753; CHECK-NEXT: fmadd 1, 1, 2, 0754; CHECK-NEXT: blr755;756; CHECK-VSX-LABEL: test_reassoc_FMADD_ASSOC_EXT4:757; CHECK-VSX: # %bb.0:758; CHECK-VSX-NEXT: xsmaddmdp 3, 4, 5759; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2760; CHECK-VSX-NEXT: fmr 1, 3761; CHECK-VSX-NEXT: blr762;763; CHECK-SPE-LABEL: test_reassoc_FMADD_ASSOC_EXT4:764; CHECK-SPE: # %bb.0:765; CHECK-SPE-NEXT: efsmul 3, 3, 4766; CHECK-SPE-NEXT: efsmul 4, 5, 6767; CHECK-SPE-NEXT: efsadd 3, 3, 4768; CHECK-SPE-NEXT: evmergelo 4, 7, 8769; CHECK-SPE-NEXT: efdcfs 3, 3770; CHECK-SPE-NEXT: efdadd 4, 4, 3771; CHECK-SPE-NEXT: evmergehi 3, 4, 4772; CHECK-SPE-NEXT: blr773 float %D, double %E) {774 %F = fmul reassoc float %A, %B ; <float> [#uses=1]775 %G = fmul reassoc float %C, %D ; <float> [#uses=1]776 %H = fadd reassoc float %F, %G ; <float> [#uses=1]777 %I = fpext float %H to double ; <double> [#uses=1]778 %J = fadd reassoc double %E, %I ; <double> [#uses=1]779 ret double %J780}781 782define double @test_reassoc_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,783; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:784; CHECK: # %bb.0:785; CHECK-NEXT: fmsub 0, 1, 2, 5786; CHECK-NEXT: fmadd 1, 3, 4, 0787; CHECK-NEXT: blr788;789; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:790; CHECK-VSX: # %bb.0:791; CHECK-VSX-NEXT: xsmsubmdp 1, 2, 5792; CHECK-VSX-NEXT: xsmaddadp 1, 3, 4793; CHECK-VSX-NEXT: blr794;795; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT1:796; CHECK-SPE: # %bb.0:797; CHECK-SPE-NEXT: efsmul 3, 3, 4798; CHECK-SPE-NEXT: evmergelo 4, 9, 10799; CHECK-SPE-NEXT: evmergelo 7, 7, 8800; CHECK-SPE-NEXT: efdcfs 3, 3801; CHECK-SPE-NEXT: evmergelo 5, 5, 6802; CHECK-SPE-NEXT: efdmul 5, 5, 7803; CHECK-SPE-NEXT: efdadd 3, 5, 3804; CHECK-SPE-NEXT: efdsub 4, 3, 4805; CHECK-SPE-NEXT: evmergehi 3, 4, 4806; CHECK-SPE-NEXT: blr807 double %D, double %E) {808 %F = fmul reassoc float %A, %B ; <float> [#uses=1]809 %G = fpext float %F to double ; <double> [#uses=1]810 %H = fmul reassoc double %C, %D ; <double> [#uses=1]811 %I = fadd reassoc double %H, %G ; <double> [#uses=1]812 %J = fsub reassoc double %I, %E ; <double> [#uses=1]813 ret double %J814}815 816define double @test_reassoc_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,817; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:818; CHECK: # %bb.0:819; CHECK-NEXT: fmsub 0, 3, 4, 5820; CHECK-NEXT: fmadd 1, 1, 2, 0821; CHECK-NEXT: blr822;823; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:824; CHECK-VSX: # %bb.0:825; CHECK-VSX-NEXT: xsmsubmdp 3, 4, 5826; CHECK-VSX-NEXT: xsmaddadp 3, 1, 2827; CHECK-VSX-NEXT: fmr 1, 3828; CHECK-VSX-NEXT: blr829;830; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT2:831; CHECK-SPE: # %bb.0:832; CHECK-SPE-NEXT: efsmul 3, 3, 4833; CHECK-SPE-NEXT: efsmul 4, 5, 6834; CHECK-SPE-NEXT: efsadd 3, 3, 4835; CHECK-SPE-NEXT: evmergelo 4, 7, 8836; CHECK-SPE-NEXT: efdcfs 3, 3837; CHECK-SPE-NEXT: efdsub 4, 3, 4838; CHECK-SPE-NEXT: evmergehi 3, 4, 4839; CHECK-SPE-NEXT: blr840 float %D, double %E) {841 %F = fmul reassoc float %A, %B ; <float> [#uses=1]842 %G = fmul reassoc float %C, %D ; <float> [#uses=1]843 %H = fadd reassoc float %F, %G ; <float> [#uses=1]844 %I = fpext float %H to double ; <double> [#uses=1]845 %J = fsub reassoc double %I, %E ; <double> [#uses=1]846 ret double %J847}848 849define double @test_reassoc_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,850; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:851; CHECK: # %bb.0:852; CHECK-NEXT: fneg 0, 1853; CHECK-NEXT: fmadd 0, 0, 2, 5854; CHECK-NEXT: fneg 1, 3855; CHECK-NEXT: fmadd 1, 1, 4, 0856; CHECK-NEXT: blr857;858; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:859; CHECK-VSX: # %bb.0:860; CHECK-VSX-NEXT: xsnegdp 1, 1861; CHECK-VSX-NEXT: xsnegdp 0, 3862; CHECK-VSX-NEXT: xsmaddmdp 1, 2, 5863; CHECK-VSX-NEXT: xsmaddadp 1, 0, 4864; CHECK-VSX-NEXT: blr865;866; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT3:867; CHECK-SPE: # %bb.0:868; CHECK-SPE-NEXT: efsmul 3, 3, 4869; CHECK-SPE-NEXT: evmergelo 4, 9, 10870; CHECK-SPE-NEXT: evmergelo 7, 7, 8871; CHECK-SPE-NEXT: efdcfs 3, 3872; CHECK-SPE-NEXT: evmergelo 5, 5, 6873; CHECK-SPE-NEXT: efdmul 5, 5, 7874; CHECK-SPE-NEXT: efdadd 3, 5, 3875; CHECK-SPE-NEXT: efdsub 4, 4, 3876; CHECK-SPE-NEXT: evmergehi 3, 4, 4877; CHECK-SPE-NEXT: blr878 double %D, double %E) {879 %F = fmul reassoc float %A, %B ; <float> [#uses=1]880 %G = fpext float %F to double ; <double> [#uses=1]881 %H = fmul reassoc double %C, %D ; <double> [#uses=1]882 %I = fadd reassoc double %H, %G ; <double> [#uses=1]883 %J = fsub reassoc double %E, %I ; <double> [#uses=1]884 ret double %J885}886 887; fnmsub/xsnmsubadp may affect the sign of zero, we need nsz flag888; to ensure generating them889define double @test_fast_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,890; CHECK-LABEL: test_fast_FMSUB_ASSOC_EXT3:891; CHECK: # %bb.0:892; CHECK-NEXT: fnmsub 0, 1, 2, 5893; CHECK-NEXT: fnmsub 1, 3, 4, 0894; CHECK-NEXT: blr895;896; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC_EXT3:897; CHECK-VSX: # %bb.0:898; CHECK-VSX-NEXT: xsnmsubmdp 1, 2, 5899; CHECK-VSX-NEXT: xsnmsubadp 1, 3, 4900; CHECK-VSX-NEXT: blr901;902; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC_EXT3:903; CHECK-SPE: # %bb.0:904; CHECK-SPE-NEXT: efsmul 3, 3, 4905; CHECK-SPE-NEXT: evmergelo 4, 9, 10906; CHECK-SPE-NEXT: evmergelo 7, 7, 8907; CHECK-SPE-NEXT: efdcfs 3, 3908; CHECK-SPE-NEXT: evmergelo 5, 5, 6909; CHECK-SPE-NEXT: efdmul 5, 5, 7910; CHECK-SPE-NEXT: efdadd 3, 5, 3911; CHECK-SPE-NEXT: efdsub 4, 4, 3912; CHECK-SPE-NEXT: evmergehi 3, 4, 4913; CHECK-SPE-NEXT: blr914 double %D, double %E) {915 %F = fmul reassoc float %A, %B916 %G = fpext float %F to double917 %H = fmul reassoc double %C, %D918 %I = fadd reassoc nsz double %H, %G919 %J = fsub reassoc nsz double %E, %I920 ret double %J921}922 923define double @test_reassoc_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,924; CHECK-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:925; CHECK: # %bb.0:926; CHECK-NEXT: fneg 0, 3927; CHECK-NEXT: fmadd 0, 0, 4, 5928; CHECK-NEXT: fneg 1, 1929; CHECK-NEXT: fmadd 1, 1, 2, 0930; CHECK-NEXT: blr931;932; CHECK-VSX-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:933; CHECK-VSX: # %bb.0:934; CHECK-VSX-NEXT: xsnegdp 0, 3935; CHECK-VSX-NEXT: xsnegdp 1, 1936; CHECK-VSX-NEXT: xsmaddmdp 0, 4, 5937; CHECK-VSX-NEXT: xsmaddadp 0, 1, 2938; CHECK-VSX-NEXT: fmr 1, 0939; CHECK-VSX-NEXT: blr940;941; CHECK-SPE-LABEL: test_reassoc_FMSUB_ASSOC_EXT4:942; CHECK-SPE: # %bb.0:943; CHECK-SPE-NEXT: efsmul 3, 3, 4944; CHECK-SPE-NEXT: efsmul 4, 5, 6945; CHECK-SPE-NEXT: efsadd 3, 3, 4946; CHECK-SPE-NEXT: evmergelo 4, 7, 8947; CHECK-SPE-NEXT: efdcfs 3, 3948; CHECK-SPE-NEXT: efdsub 4, 4, 3949; CHECK-SPE-NEXT: evmergehi 3, 4, 4950; CHECK-SPE-NEXT: blr951 float %D, double %E) {952 %F = fmul reassoc float %A, %B ; <float> [#uses=1]953 %G = fmul reassoc float %C, %D ; <float> [#uses=1]954 %H = fadd reassoc float %F, %G ; <float> [#uses=1]955 %I = fpext float %H to double ; <double> [#uses=1]956 %J = fsub reassoc double %E, %I ; <double> [#uses=1]957 ret double %J958}959 960define double @test_fast_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,961; CHECK-LABEL: test_fast_FMSUB_ASSOC_EXT4:962; CHECK: # %bb.0:963; CHECK-NEXT: fnmsub 0, 3, 4, 5964; CHECK-NEXT: fnmsub 1, 1, 2, 0965; CHECK-NEXT: blr966;967; CHECK-VSX-LABEL: test_fast_FMSUB_ASSOC_EXT4:968; CHECK-VSX: # %bb.0:969; CHECK-VSX-NEXT: xsnmsubmdp 3, 4, 5970; CHECK-VSX-NEXT: xsnmsubadp 3, 1, 2971; CHECK-VSX-NEXT: fmr 1, 3972; CHECK-VSX-NEXT: blr973;974; CHECK-SPE-LABEL: test_fast_FMSUB_ASSOC_EXT4:975; CHECK-SPE: # %bb.0:976; CHECK-SPE-NEXT: efsmul 3, 3, 4977; CHECK-SPE-NEXT: efsmul 4, 5, 6978; CHECK-SPE-NEXT: efsadd 3, 3, 4979; CHECK-SPE-NEXT: evmergelo 4, 7, 8980; CHECK-SPE-NEXT: efdcfs 3, 3981; CHECK-SPE-NEXT: efdsub 4, 4, 3982; CHECK-SPE-NEXT: evmergehi 3, 4, 4983; CHECK-SPE-NEXT: blr984 float %D, double %E) {985 %F = fmul reassoc float %A, %B986 %G = fmul reassoc float %C, %D987 %H = fadd reassoc nsz float %F, %G988 %I = fpext float %H to double989 %J = fsub reassoc nsz double %E, %I990 ret double %J991}992