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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple powerpc64le -verify-machineinstrs \3; RUN: | FileCheck -check-prefix=VSX %s4; RUN: llc < %s -mtriple powerpc64le -verify-machineinstrs -mattr=-vsx \5; RUN: | FileCheck -check-prefix=NO-VSX %s6 7define double @test_mul_sub_f64(double %a, double %b, double %c) {8; VSX-LABEL: test_mul_sub_f64:9; VSX: # %bb.0: # %entry10; VSX-NEXT: xsnegdp 0, 211; VSX-NEXT: xsmaddadp 1, 0, 312; VSX-NEXT: blr13;14; NO-VSX-LABEL: test_mul_sub_f64:15; NO-VSX: # %bb.0: # %entry16; NO-VSX-NEXT: fneg 0, 217; NO-VSX-NEXT: fmadd 1, 0, 3, 118; NO-VSX-NEXT: blr19entry:20 %0 = fmul contract reassoc double %b, %c21 %1 = fsub contract reassoc double %a, %022 ret double %123}24 25define double @test_2mul_sub_f64(double %a, double %b, double %c, double %d) {26; VSX-LABEL: test_2mul_sub_f64:27; VSX: # %bb.0: # %entry28; VSX-NEXT: xsmuldp 0, 3, 429; VSX-NEXT: xsmsubadp 0, 1, 230; VSX-NEXT: fmr 1, 031; VSX-NEXT: blr32;33; NO-VSX-LABEL: test_2mul_sub_f64:34; NO-VSX: # %bb.0: # %entry35; NO-VSX-NEXT: fmul 0, 3, 436; NO-VSX-NEXT: fmsub 1, 1, 2, 037; NO-VSX-NEXT: blr38entry:39 %0 = fmul contract reassoc double %a, %b40 %1 = fmul contract reassoc double %c, %d41 %2 = fsub contract reassoc double %0, %142 ret double %243}44 45define double @test_neg_fma_f64(double %a, double %b, double %c) {46; VSX-LABEL: test_neg_fma_f64:47; VSX: # %bb.0: # %entry48; VSX-NEXT: xsnegdp 0, 149; VSX-NEXT: xsmaddadp 3, 0, 250; VSX-NEXT: fmr 1, 351; VSX-NEXT: blr52;53; NO-VSX-LABEL: test_neg_fma_f64:54; NO-VSX: # %bb.0: # %entry55; NO-VSX-NEXT: fneg 0, 156; NO-VSX-NEXT: fmadd 1, 0, 2, 357; NO-VSX-NEXT: blr58entry:59 %0 = fsub contract reassoc double -0.0, %a60 %1 = call contract reassoc double @llvm.fma.f64(double %0, double %b,61 double %c)62 ret double %163}64 65define float @test_mul_sub_f32(float %a, float %b, float %c) {66; VSX-LABEL: test_mul_sub_f32:67; VSX: # %bb.0: # %entry68; VSX-NEXT: xsnegdp 0, 269; VSX-NEXT: xsmaddasp 1, 0, 370; VSX-NEXT: blr71;72; NO-VSX-LABEL: test_mul_sub_f32:73; NO-VSX: # %bb.0: # %entry74; NO-VSX-NEXT: fneg 0, 275; NO-VSX-NEXT: fmadds 1, 0, 3, 176; NO-VSX-NEXT: blr77entry:78 %0 = fmul contract reassoc float %b, %c79 %1 = fsub contract reassoc float %a, %080 ret float %181}82 83define float @test_2mul_sub_f32(float %a, float %b, float %c, float %d) {84; VSX-LABEL: test_2mul_sub_f32:85; VSX: # %bb.0: # %entry86; VSX-NEXT: xsmulsp 0, 3, 487; VSX-NEXT: xsmsubasp 0, 1, 288; VSX-NEXT: fmr 1, 089; VSX-NEXT: blr90;91; NO-VSX-LABEL: test_2mul_sub_f32:92; NO-VSX: # %bb.0: # %entry93; NO-VSX-NEXT: fmuls 0, 3, 494; NO-VSX-NEXT: fmsubs 1, 1, 2, 095; NO-VSX-NEXT: blr96entry:97 %0 = fmul contract reassoc float %a, %b98 %1 = fmul contract reassoc float %c, %d99 %2 = fsub contract reassoc float %0, %1100 ret float %2101}102 103define float @test_neg_fma_f32(float %a, float %b, float %c) {104; VSX-LABEL: test_neg_fma_f32:105; VSX: # %bb.0: # %entry106; VSX-NEXT: xsnegdp 0, 1107; VSX-NEXT: xsmaddasp 3, 0, 2108; VSX-NEXT: fmr 1, 3109; VSX-NEXT: blr110;111; NO-VSX-LABEL: test_neg_fma_f32:112; NO-VSX: # %bb.0: # %entry113; NO-VSX-NEXT: fneg 0, 1114; NO-VSX-NEXT: fmadds 1, 0, 2, 3115; NO-VSX-NEXT: blr116entry:117 %0 = fsub contract reassoc float -0.0, %a118 %1 = call contract reassoc float @llvm.fma.f32(float %0, float %b, float %c)119 ret float %1120}121 122define <2 x double> @test_neg_fma_v2f64(<2 x double> %a, <2 x double> %b,123; VSX-LABEL: test_neg_fma_v2f64:124; VSX: # %bb.0: # %entry125; VSX-NEXT: xvnegdp 0, 34126; VSX-NEXT: xvmaddadp 36, 0, 35127; VSX-NEXT: vmr 2, 4128; VSX-NEXT: blr129;130; NO-VSX-LABEL: test_neg_fma_v2f64:131; NO-VSX: # %bb.0: # %entry132; NO-VSX-NEXT: fneg 0, 2133; NO-VSX-NEXT: fneg 1, 1134; NO-VSX-NEXT: fmadd 1, 1, 3, 5135; NO-VSX-NEXT: fmadd 2, 0, 4, 6136; NO-VSX-NEXT: blr137 <2 x double> %c) {138entry:139 %0 = fsub contract reassoc <2 x double> <double -0.0, double -0.0>, %a140 %1 = call contract reassoc <2 x double> @llvm.fma.v2f64(<2 x double> %0,141 <2 x double> %b,142 <2 x double> %c)143 ret <2 x double> %1144}145 146define <4 x float> @test_neg_fma_v4f32(<4 x float> %a, <4 x float> %b,147; VSX-LABEL: test_neg_fma_v4f32:148; VSX: # %bb.0: # %entry149; VSX-NEXT: xvnegsp 0, 34150; VSX-NEXT: xvmaddasp 36, 0, 35151; VSX-NEXT: vmr 2, 4152; VSX-NEXT: blr153;154; NO-VSX-LABEL: test_neg_fma_v4f32:155; NO-VSX: # %bb.0: # %entry156; NO-VSX-NEXT: vspltisb 5, -1157; NO-VSX-NEXT: vslw 5, 5, 5158; NO-VSX-NEXT: vxor 2, 2, 5159; NO-VSX-NEXT: vmaddfp 2, 2, 3, 4160; NO-VSX-NEXT: blr161 <4 x float> %c) {162entry:163 %0 = fsub contract reassoc <4 x float> <float -0.0, float -0.0, float -0.0,164 float -0.0>, %a165 %1 = call contract reassoc <4 x float> @llvm.fma.v4f32(<4 x float> %0,166 <4 x float> %b,167 <4 x float> %c)168 ret <4 x float> %1169}170 171define double @test_fast_mul_sub_f64(double %a, double %b, double %c) {172; VSX-LABEL: test_fast_mul_sub_f64:173; VSX: # %bb.0: # %entry174; VSX-NEXT: xsnmsubadp 1, 2, 3175; VSX-NEXT: blr176;177; NO-VSX-LABEL: test_fast_mul_sub_f64:178; NO-VSX: # %bb.0: # %entry179; NO-VSX-NEXT: fnmsub 1, 2, 3, 1180; NO-VSX-NEXT: blr181entry:182 %0 = fmul contract reassoc nsz double %b, %c183 %1 = fsub contract reassoc nsz double %a, %0184 ret double %1185}186 187define double @test_fast_2mul_sub_f64(double %a, double %b, double %c,188; VSX-LABEL: test_fast_2mul_sub_f64:189; VSX: # %bb.0: # %entry190; VSX-NEXT: xsmuldp 0, 3, 4191; VSX-NEXT: xsmsubadp 0, 1, 2192; VSX-NEXT: fmr 1, 0193; VSX-NEXT: blr194;195; NO-VSX-LABEL: test_fast_2mul_sub_f64:196; NO-VSX: # %bb.0: # %entry197; NO-VSX-NEXT: fmul 0, 3, 4198; NO-VSX-NEXT: fmsub 1, 1, 2, 0199; NO-VSX-NEXT: blr200 double %d) {201entry:202 %0 = fmul contract reassoc double %a, %b203 %1 = fmul contract reassoc double %c, %d204 %2 = fsub contract reassoc double %0, %1205 ret double %2206}207 208define double @test_fast_neg_fma_f64(double %a, double %b, double %c) {209; VSX-LABEL: test_fast_neg_fma_f64:210; VSX: # %bb.0: # %entry211; VSX-NEXT: xsnmsubadp 3, 1, 2212; VSX-NEXT: fmr 1, 3213; VSX-NEXT: blr214;215; NO-VSX-LABEL: test_fast_neg_fma_f64:216; NO-VSX: # %bb.0: # %entry217; NO-VSX-NEXT: fnmsub 1, 1, 2, 3218; NO-VSX-NEXT: blr219entry:220 %0 = fsub reassoc double -0.0, %a221 %1 = call reassoc nsz double @llvm.fma.f64(double %0, double %b, double %c)222 ret double %1223}224 225define float @test_fast_mul_sub_f32(float %a, float %b, float %c) {226; VSX-LABEL: test_fast_mul_sub_f32:227; VSX: # %bb.0: # %entry228; VSX-NEXT: xsnmsubasp 1, 2, 3229; VSX-NEXT: blr230;231; NO-VSX-LABEL: test_fast_mul_sub_f32:232; NO-VSX: # %bb.0: # %entry233; NO-VSX-NEXT: fnmsubs 1, 2, 3, 1234; NO-VSX-NEXT: blr235entry:236 %0 = fmul contract reassoc float %b, %c237 %1 = fsub contract reassoc nsz float %a, %0238 ret float %1239}240 241define float @test_fast_2mul_sub_f32(float %a, float %b, float %c, float %d) {242; VSX-LABEL: test_fast_2mul_sub_f32:243; VSX: # %bb.0: # %entry244; VSX-NEXT: xsmulsp 0, 3, 4245; VSX-NEXT: xsmsubasp 0, 1, 2246; VSX-NEXT: fmr 1, 0247; VSX-NEXT: blr248;249; NO-VSX-LABEL: test_fast_2mul_sub_f32:250; NO-VSX: # %bb.0: # %entry251; NO-VSX-NEXT: fmuls 0, 3, 4252; NO-VSX-NEXT: fmsubs 1, 1, 2, 0253; NO-VSX-NEXT: blr254entry:255 %0 = fmul contract reassoc float %a, %b256 %1 = fmul contract reassoc float %c, %d257 %2 = fsub contract reassoc nsz float %0, %1258 ret float %2259}260 261define float @test_fast_neg_fma_f32(float %a, float %b, float %c) {262; VSX-LABEL: test_fast_neg_fma_f32:263; VSX: # %bb.0: # %entry264; VSX-NEXT: xsnmsubasp 3, 1, 2265; VSX-NEXT: fmr 1, 3266; VSX-NEXT: blr267;268; NO-VSX-LABEL: test_fast_neg_fma_f32:269; NO-VSX: # %bb.0: # %entry270; NO-VSX-NEXT: fnmsubs 1, 1, 2, 3271; NO-VSX-NEXT: blr272entry:273 %0 = fsub reassoc float -0.0, %a274 %1 = call reassoc nsz float @llvm.fma.f32(float %0, float %b, float %c)275 ret float %1276}277 278define <2 x double> @test_fast_neg_fma_v2f64(<2 x double> %a, <2 x double> %b,279; VSX-LABEL: test_fast_neg_fma_v2f64:280; VSX: # %bb.0: # %entry281; VSX-NEXT: xvnmsubadp 36, 34, 35282; VSX-NEXT: vmr 2, 4283; VSX-NEXT: blr284;285; NO-VSX-LABEL: test_fast_neg_fma_v2f64:286; NO-VSX: # %bb.0: # %entry287; NO-VSX-NEXT: fnmsub 1, 1, 3, 5288; NO-VSX-NEXT: fnmsub 2, 2, 4, 6289; NO-VSX-NEXT: blr290 <2 x double> %c) {291entry:292 %0 = fsub reassoc <2 x double> <double -0.0, double -0.0>, %a293 %1 = call reassoc nsz <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %b,294 <2 x double> %c)295 ret <2 x double> %1296}297 298define <4 x float> @test_fast_neg_fma_v4f32(<4 x float> %a, <4 x float> %b,299; VSX-LABEL: test_fast_neg_fma_v4f32:300; VSX: # %bb.0: # %entry301; VSX-NEXT: xvnmsubasp 36, 34, 35302; VSX-NEXT: vmr 2, 4303; VSX-NEXT: blr304;305; NO-VSX-LABEL: test_fast_neg_fma_v4f32:306; NO-VSX: # %bb.0: # %entry307; NO-VSX-NEXT: vnmsubfp 2, 2, 3, 4308; NO-VSX-NEXT: blr309 <4 x float> %c) {310entry:311 %0 = fsub reassoc <4 x float> <float -0.0, float -0.0, float -0.0,312 float -0.0>, %a313 %1 = call reassoc nsz <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %b,314 <4 x float> %c)315 ret <4 x float> %1316}317 318declare float @llvm.fma.f32(float %a, float %b, float %c)319declare double @llvm.fma.f64(double %a, double %b, double %c)320declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b,321 <4 x float> %c)322declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,323 <2 x double> %c)324