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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -ppc-asm-full-reg-names | FileCheck %s3 4define double @test1(double %a, double %b, double %c, double %d) {5; CHECK-LABEL: test1:6; CHECK: # %bb.0:7; CHECK-NEXT: fmul f0, f3, f48; CHECK-NEXT: fmul f1, f1, f29; CHECK-NEXT: fadd f1, f1, f010; CHECK-NEXT: blr11 %tmp2 = fsub double -0.000000e+00, %c12 %tmp4 = fmul double %tmp2, %d13 %tmp7 = fmul double %a, %b14 %tmp9 = fsub double %tmp7, %tmp415 ret double %tmp916}17 18declare float @llvm.fmuladd.f32(float, float, float) #419 20define float @fma_fneg_fneg(float %x, float %y, float %z) {21; CHECK-LABEL: fma_fneg_fneg:22; CHECK: # %bb.0:23; CHECK-NEXT: fmadds f1, f1, f2, f324; CHECK-NEXT: blr25 %negx = fneg float %x26 %negy = fneg float %y27 %r = call float @llvm.fmuladd.f32(float %negx, float %negy, float %z)28 ret float %r29}30 31define float @fma_fneg_fsub(float %x, float %y0, float %y1, float %z) {32; CHECK-LABEL: fma_fneg_fsub:33; CHECK: # %bb.0:34; CHECK-NEXT: fsubs f0, f3, f235; CHECK-NEXT: fmadds f1, f1, f0, f436; CHECK-NEXT: blr37 %negx = fneg float %x38 %negy = fsub nsz float %y0, %y139 %r = call float @llvm.fmuladd.f32(float %negx, float %negy, float %z)40 ret float %r41}42 43; Verify that we didn't hit assertion for this case.44define double @fneg_no_ice(float %x) {45; CHECK-LABEL: fneg_no_ice:46; CHECK: # %bb.0:47; CHECK-NEXT: lis r3, .LCPI3_0@ha48; CHECK-NEXT: lfs f0, .LCPI3_0@l(r3)49; CHECK-NEXT: fsubs f0, f0, f150; CHECK-NEXT: fmul f1, f0, f051; CHECK-NEXT: fmul f1, f0, f152; CHECK-NEXT: blr53 %y = fsub fast float 1.0, %x54 %e = fpext float %y to double55 %e2 = fmul double %e, %e56 %e3 = fmul double %e, %e257 ret double %e358}59 60define double @fneg_fmul_const(double %x) {61; CHECK-LABEL: fneg_fmul_const:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: lis r3, .LCPI4_0@ha64; CHECK-NEXT: lfd f0, .LCPI4_0@l(r3)65; CHECK-NEXT: fmul f1, f1, f066; CHECK-NEXT: blr67entry:68 %f = fmul double %x, 1.234569 %s = fneg double %f70 ret double %s71}72