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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s4 5@val = external local_unnamed_addr global i32, align 46declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>)7 8define dso_local signext i32 @xvtsqrtdp_and_1_eq(<2 x double> %input) {9; CHECK-LABEL: xvtsqrtdp_and_1_eq:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: xvtsqrtdp cr0, v212; CHECK-NEXT: bnu cr0, .LBB0_213; CHECK-NEXT: # %bb.1: # %if.then14; CHECK-NEXT: addis r3, r2, .LC0@toc@ha15; CHECK-NEXT: li r4, 10016; CHECK-NEXT: ld r3, .LC0@toc@l(r3)17; CHECK-NEXT: stw r4, 0(r3)18; CHECK-NEXT: .LBB0_2: # %if.end19; CHECK-NEXT: li r3, 120; CHECK-NEXT: blr21entry:22 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)23 %1 = and i32 %0, 124 %cmp.not = icmp eq i32 %1, 025 br i1 %cmp.not, label %if.end, label %if.then26 27if.then: ; preds = %entry28 store i32 100, ptr @val, align 429 br label %if.end30 31if.end: ; preds = %if.then, %entry32 ret i32 133}34 35define dso_local signext i32 @xvtsqrtdp_and_2_eq(<2 x double> %input) {36; CHECK-LABEL: xvtsqrtdp_and_2_eq:37; CHECK: # %bb.0: # %entry38; CHECK-NEXT: xvtsqrtdp cr0, v239; CHECK-NEXT: bne cr0, .LBB1_240; CHECK-NEXT: # %bb.1: # %if.then41; CHECK-NEXT: addis r3, r2, .LC0@toc@ha42; CHECK-NEXT: li r4, 10043; CHECK-NEXT: ld r3, .LC0@toc@l(r3)44; CHECK-NEXT: stw r4, 0(r3)45; CHECK-NEXT: .LBB1_2: # %if.end46; CHECK-NEXT: li r3, 147; CHECK-NEXT: blr48entry:49 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)50 %1 = and i32 %0, 251 %cmp.not = icmp eq i32 %1, 052 br i1 %cmp.not, label %if.end, label %if.then53 54if.then: ; preds = %entry55 store i32 100, ptr @val, align 456 br label %if.end57 58if.end: ; preds = %if.then, %entry59 ret i32 160}61 62define dso_local signext i32 @xvtsqrtdp_and_4_eq(<2 x double> %input) {63; CHECK-LABEL: xvtsqrtdp_and_4_eq:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: xvtsqrtdp cr0, v266; CHECK-NEXT: ble cr0, .LBB2_267; CHECK-NEXT: # %bb.1: # %if.then68; CHECK-NEXT: addis r3, r2, .LC0@toc@ha69; CHECK-NEXT: li r4, 10070; CHECK-NEXT: ld r3, .LC0@toc@l(r3)71; CHECK-NEXT: stw r4, 0(r3)72; CHECK-NEXT: .LBB2_2: # %if.end73; CHECK-NEXT: li r3, 174; CHECK-NEXT: blr75entry:76 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)77 %1 = and i32 %0, 478 %cmp.not = icmp eq i32 %1, 079 br i1 %cmp.not, label %if.end, label %if.then80 81if.then: ; preds = %entry82 store i32 100, ptr @val, align 483 br label %if.end84 85if.end: ; preds = %if.then, %entry86 ret i32 187}88 89define dso_local signext i32 @xvtsqrtdp_and_8_eq(<2 x double> %input) {90; CHECK-LABEL: xvtsqrtdp_and_8_eq:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: xvtsqrtdp cr0, v293; CHECK-NEXT: bge cr0, .LBB3_294; CHECK-NEXT: # %bb.1: # %if.then95; CHECK-NEXT: addis r3, r2, .LC0@toc@ha96; CHECK-NEXT: li r4, 10097; CHECK-NEXT: ld r3, .LC0@toc@l(r3)98; CHECK-NEXT: stw r4, 0(r3)99; CHECK-NEXT: .LBB3_2: # %if.end100; CHECK-NEXT: li r3, 1101; CHECK-NEXT: blr102entry:103 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)104 %1 = and i32 %0, 8105 %cmp.not = icmp eq i32 %1, 0106 br i1 %cmp.not, label %if.end, label %if.then107 108if.then: ; preds = %entry109 store i32 100, ptr @val, align 4110 br label %if.end111 112if.end: ; preds = %if.then, %entry113 ret i32 1114}115 116define dso_local signext i32 @xvtsqrtdp_and_1_ne(<2 x double> %input) {117; CHECK-LABEL: xvtsqrtdp_and_1_ne:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: xvtsqrtdp cr0, v2120; CHECK-NEXT: bun cr0, .LBB4_2121; CHECK-NEXT: # %bb.1: # %if.then122; CHECK-NEXT: addis r3, r2, .LC0@toc@ha123; CHECK-NEXT: li r4, 100124; CHECK-NEXT: ld r3, .LC0@toc@l(r3)125; CHECK-NEXT: stw r4, 0(r3)126; CHECK-NEXT: .LBB4_2: # %if.end127; CHECK-NEXT: li r3, 1128; CHECK-NEXT: blr129entry:130 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)131 %1 = and i32 %0, 1132 %cmp.not = icmp ne i32 %1, 0133 br i1 %cmp.not, label %if.end, label %if.then134 135if.then: ; preds = %entry136 store i32 100, ptr @val, align 4137 br label %if.end138 139if.end: ; preds = %if.then, %entry140 ret i32 1141}142 143define dso_local signext i32 @xvtsqrtdp_and_2_ne(<2 x double> %input) {144; CHECK-LABEL: xvtsqrtdp_and_2_ne:145; CHECK: # %bb.0: # %if.end146; CHECK-NEXT: li r3, 1147; CHECK-NEXT: blr148if.end: ; preds = %if.then, %entry149 ret i32 1150}151 152define dso_local signext i32 @xvtsqrtdp_and_4_ne(<2 x double> %input) {153; CHECK-LABEL: xvtsqrtdp_and_4_ne:154; CHECK: # %bb.0: # %entry155; CHECK-NEXT: xvtsqrtdp cr0, v2156; CHECK-NEXT: bgt cr0, .LBB6_2157; CHECK-NEXT: # %bb.1: # %if.then158; CHECK-NEXT: addis r3, r2, .LC0@toc@ha159; CHECK-NEXT: li r4, 100160; CHECK-NEXT: ld r3, .LC0@toc@l(r3)161; CHECK-NEXT: stw r4, 0(r3)162; CHECK-NEXT: .LBB6_2: # %if.end163; CHECK-NEXT: li r3, 1164; CHECK-NEXT: blr165entry:166 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)167 %1 = and i32 %0, 4168 %cmp.not = icmp ne i32 %1, 0169 br i1 %cmp.not, label %if.end, label %if.then170 171if.then: ; preds = %entry172 store i32 100, ptr @val, align 4173 br label %if.end174 175if.end: ; preds = %if.then, %entry176 ret i32 1177}178 179define dso_local signext i32 @xvtsqrtdp_and_8_ne(<2 x double> %input) {180; CHECK-LABEL: xvtsqrtdp_and_8_ne:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: xvtsqrtdp cr0, v2183; CHECK-NEXT: blt cr0, .LBB7_2184; CHECK-NEXT: # %bb.1: # %if.then185; CHECK-NEXT: addis r3, r2, .LC0@toc@ha186; CHECK-NEXT: li r4, 100187; CHECK-NEXT: ld r3, .LC0@toc@l(r3)188; CHECK-NEXT: stw r4, 0(r3)189; CHECK-NEXT: .LBB7_2: # %if.end190; CHECK-NEXT: li r3, 1191; CHECK-NEXT: blr192entry:193 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input)194 %1 = and i32 %0, 8195 %cmp.not = icmp ne i32 %1, 0196 br i1 %cmp.not, label %if.end, label %if.then197 198if.then: ; preds = %entry199 store i32 100, ptr @val, align 4200 br label %if.end201 202if.end: ; preds = %if.then, %entry203 ret i32 1204}205