522 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \3; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s4; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \5; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s6 7; Function Attrs: nounwind8define zeroext i8 @_Z6testcff(float %arg) {9; CHECK-LABEL: _Z6testcff:10; CHECK: # %bb.0: # %entry11; CHECK-NEXT: xscvdpsxws f0, f112; CHECK-NEXT: stfs f1, -4(r1)13; CHECK-NEXT: mffprwz r3, f014; CHECK-NEXT: blr15entry:16 %arg.addr = alloca float, align 417 store float %arg, ptr %arg.addr, align 418 %0 = load float, ptr %arg.addr, align 419 %conv = fptoui float %0 to i820 ret i8 %conv21}22 23; Function Attrs: nounwind24define float @_Z6testfcc(i8 zeroext %arg) {25; CHECK-LABEL: _Z6testfcc:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: mtfprwz f0, r328; CHECK-NEXT: stb r3, -1(r1)29; CHECK-NEXT: xscvuxdsp f1, f030; CHECK-NEXT: blr31entry:32 %arg.addr = alloca i8, align 133 store i8 %arg, ptr %arg.addr, align 134 %0 = load i8, ptr %arg.addr, align 135 %conv = uitofp i8 %0 to float36 ret float %conv37}38 39; Function Attrs: nounwind40define zeroext i8 @_Z6testcdd(double %arg) {41; CHECK-LABEL: _Z6testcdd:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: xscvdpsxws f0, f144; CHECK-NEXT: stfd f1, -8(r1)45; CHECK-NEXT: mffprwz r3, f046; CHECK-NEXT: blr47entry:48 %arg.addr = alloca double, align 849 store double %arg, ptr %arg.addr, align 850 %0 = load double, ptr %arg.addr, align 851 %conv = fptoui double %0 to i852 ret i8 %conv53}54 55; Function Attrs: nounwind56define double @_Z6testdcc(i8 zeroext %arg) {57; CHECK-LABEL: _Z6testdcc:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: mtfprwz f0, r360; CHECK-NEXT: stb r3, -1(r1)61; CHECK-NEXT: xscvuxddp f1, f062; CHECK-NEXT: blr63entry:64 %arg.addr = alloca i8, align 165 store i8 %arg, ptr %arg.addr, align 166 %0 = load i8, ptr %arg.addr, align 167 %conv = uitofp i8 %0 to double68 ret double %conv69}70 71; Function Attrs: nounwind72define zeroext i8 @_Z7testucff(float %arg) {73; CHECK-LABEL: _Z7testucff:74; CHECK: # %bb.0: # %entry75; CHECK-NEXT: xscvdpsxws f0, f176; CHECK-NEXT: stfs f1, -4(r1)77; CHECK-NEXT: mffprwz r3, f078; CHECK-NEXT: blr79entry:80 %arg.addr = alloca float, align 481 store float %arg, ptr %arg.addr, align 482 %0 = load float, ptr %arg.addr, align 483 %conv = fptoui float %0 to i884 ret i8 %conv85}86 87; Function Attrs: nounwind88define float @_Z7testfuch(i8 zeroext %arg) {89; CHECK-LABEL: _Z7testfuch:90; CHECK: # %bb.0: # %entry91; CHECK-NEXT: mtfprwz f0, r392; CHECK-NEXT: stb r3, -1(r1)93; CHECK-NEXT: xscvuxdsp f1, f094; CHECK-NEXT: blr95entry:96 %arg.addr = alloca i8, align 197 store i8 %arg, ptr %arg.addr, align 198 %0 = load i8, ptr %arg.addr, align 199 %conv = uitofp i8 %0 to float100 ret float %conv101}102 103; Function Attrs: nounwind104define zeroext i8 @_Z7testucdd(double %arg) {105; CHECK-LABEL: _Z7testucdd:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: xscvdpsxws f0, f1108; CHECK-NEXT: stfd f1, -8(r1)109; CHECK-NEXT: mffprwz r3, f0110; CHECK-NEXT: blr111entry:112 %arg.addr = alloca double, align 8113 store double %arg, ptr %arg.addr, align 8114 %0 = load double, ptr %arg.addr, align 8115 %conv = fptoui double %0 to i8116 ret i8 %conv117}118 119; Function Attrs: nounwind120define double @_Z7testduch(i8 zeroext %arg) {121; CHECK-LABEL: _Z7testduch:122; CHECK: # %bb.0: # %entry123; CHECK-NEXT: mtfprwz f0, r3124; CHECK-NEXT: stb r3, -1(r1)125; CHECK-NEXT: xscvuxddp f1, f0126; CHECK-NEXT: blr127entry:128 %arg.addr = alloca i8, align 1129 store i8 %arg, ptr %arg.addr, align 1130 %0 = load i8, ptr %arg.addr, align 1131 %conv = uitofp i8 %0 to double132 ret double %conv133}134 135; Function Attrs: nounwind136define signext i16 @_Z6testsff(float %arg) {137; CHECK-LABEL: _Z6testsff:138; CHECK: # %bb.0: # %entry139; CHECK-NEXT: xscvdpsxws f0, f1140; CHECK-NEXT: stfs f1, -4(r1)141; CHECK-NEXT: mffprwz r3, f0142; CHECK-NEXT: extsw r3, r3143; CHECK-NEXT: blr144entry:145 %arg.addr = alloca float, align 4146 store float %arg, ptr %arg.addr, align 4147 %0 = load float, ptr %arg.addr, align 4148 %conv = fptosi float %0 to i16149 ret i16 %conv150}151 152; Function Attrs: nounwind153define float @_Z6testfss(i16 signext %arg) {154; CHECK-LABEL: _Z6testfss:155; CHECK: # %bb.0: # %entry156; CHECK-NEXT: mtfprwa f0, r3157; CHECK-NEXT: sth r3, -2(r1)158; CHECK-NEXT: xscvsxdsp f1, f0159; CHECK-NEXT: blr160entry:161 %arg.addr = alloca i16, align 2162 store i16 %arg, ptr %arg.addr, align 2163 %0 = load i16, ptr %arg.addr, align 2164 %conv = sitofp i16 %0 to float165 ret float %conv166}167 168; Function Attrs: nounwind169define signext i16 @_Z6testsdd(double %arg) {170; CHECK-LABEL: _Z6testsdd:171; CHECK: # %bb.0: # %entry172; CHECK-NEXT: xscvdpsxws f0, f1173; CHECK-NEXT: stfd f1, -8(r1)174; CHECK-NEXT: mffprwz r3, f0175; CHECK-NEXT: extsw r3, r3176; CHECK-NEXT: blr177entry:178 %arg.addr = alloca double, align 8179 store double %arg, ptr %arg.addr, align 8180 %0 = load double, ptr %arg.addr, align 8181 %conv = fptosi double %0 to i16182 ret i16 %conv183}184 185; Function Attrs: nounwind186define double @_Z6testdss(i16 signext %arg) {187; CHECK-LABEL: _Z6testdss:188; CHECK: # %bb.0: # %entry189; CHECK-NEXT: mtfprwa f0, r3190; CHECK-NEXT: sth r3, -2(r1)191; CHECK-NEXT: xscvsxddp f1, f0192; CHECK-NEXT: blr193entry:194 %arg.addr = alloca i16, align 2195 store i16 %arg, ptr %arg.addr, align 2196 %0 = load i16, ptr %arg.addr, align 2197 %conv = sitofp i16 %0 to double198 ret double %conv199}200 201; Function Attrs: nounwind202define zeroext i16 @_Z7testusff(float %arg) {203; CHECK-LABEL: _Z7testusff:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: xscvdpsxws f0, f1206; CHECK-NEXT: stfs f1, -4(r1)207; CHECK-NEXT: mffprwz r3, f0208; CHECK-NEXT: blr209entry:210 %arg.addr = alloca float, align 4211 store float %arg, ptr %arg.addr, align 4212 %0 = load float, ptr %arg.addr, align 4213 %conv = fptoui float %0 to i16214 ret i16 %conv215}216 217; Function Attrs: nounwind218define float @_Z7testfust(i16 zeroext %arg) {219; CHECK-LABEL: _Z7testfust:220; CHECK: # %bb.0: # %entry221; CHECK-NEXT: mtfprwz f0, r3222; CHECK-NEXT: sth r3, -2(r1)223; CHECK-NEXT: xscvuxdsp f1, f0224; CHECK-NEXT: blr225entry:226 %arg.addr = alloca i16, align 2227 store i16 %arg, ptr %arg.addr, align 2228 %0 = load i16, ptr %arg.addr, align 2229 %conv = uitofp i16 %0 to float230 ret float %conv231}232 233; Function Attrs: nounwind234define zeroext i16 @_Z7testusdd(double %arg) {235; CHECK-LABEL: _Z7testusdd:236; CHECK: # %bb.0: # %entry237; CHECK-NEXT: xscvdpsxws f0, f1238; CHECK-NEXT: stfd f1, -8(r1)239; CHECK-NEXT: mffprwz r3, f0240; CHECK-NEXT: blr241entry:242 %arg.addr = alloca double, align 8243 store double %arg, ptr %arg.addr, align 8244 %0 = load double, ptr %arg.addr, align 8245 %conv = fptoui double %0 to i16246 ret i16 %conv247}248 249; Function Attrs: nounwind250define double @_Z7testdust(i16 zeroext %arg) {251; CHECK-LABEL: _Z7testdust:252; CHECK: # %bb.0: # %entry253; CHECK-NEXT: mtfprwz f0, r3254; CHECK-NEXT: sth r3, -2(r1)255; CHECK-NEXT: xscvuxddp f1, f0256; CHECK-NEXT: blr257entry:258 %arg.addr = alloca i16, align 2259 store i16 %arg, ptr %arg.addr, align 2260 %0 = load i16, ptr %arg.addr, align 2261 %conv = uitofp i16 %0 to double262 ret double %conv263}264 265; Function Attrs: nounwind266define signext i32 @_Z6testiff(float %arg) {267; CHECK-LABEL: _Z6testiff:268; CHECK: # %bb.0: # %entry269; CHECK-NEXT: xscvdpsxws f0, f1270; CHECK-NEXT: stfs f1, -4(r1)271; CHECK-NEXT: mffprwz r3, f0272; CHECK-NEXT: extsw r3, r3273; CHECK-NEXT: blr274entry:275 %arg.addr = alloca float, align 4276 store float %arg, ptr %arg.addr, align 4277 %0 = load float, ptr %arg.addr, align 4278 %conv = fptosi float %0 to i32279 ret i32 %conv280}281 282; Function Attrs: nounwind283define float @_Z6testfii(i32 signext %arg) {284; CHECK-LABEL: _Z6testfii:285; CHECK: # %bb.0: # %entry286; CHECK-NEXT: mtfprwa f0, r3287; CHECK-NEXT: stw r3, -4(r1)288; CHECK-NEXT: xscvsxdsp f1, f0289; CHECK-NEXT: blr290entry:291 %arg.addr = alloca i32, align 4292 store i32 %arg, ptr %arg.addr, align 4293 %0 = load i32, ptr %arg.addr, align 4294 %conv = sitofp i32 %0 to float295 ret float %conv296}297 298; Function Attrs: nounwind299define signext i32 @_Z6testidd(double %arg) {300; CHECK-LABEL: _Z6testidd:301; CHECK: # %bb.0: # %entry302; CHECK-NEXT: xscvdpsxws f0, f1303; CHECK-NEXT: stfd f1, -8(r1)304; CHECK-NEXT: mffprwz r3, f0305; CHECK-NEXT: extsw r3, r3306; CHECK-NEXT: blr307entry:308 %arg.addr = alloca double, align 8309 store double %arg, ptr %arg.addr, align 8310 %0 = load double, ptr %arg.addr, align 8311 %conv = fptosi double %0 to i32312 ret i32 %conv313}314 315; Function Attrs: nounwind316define double @_Z6testdii(i32 signext %arg) {317; CHECK-LABEL: _Z6testdii:318; CHECK: # %bb.0: # %entry319; CHECK-NEXT: mtfprwa f0, r3320; CHECK-NEXT: stw r3, -4(r1)321; CHECK-NEXT: xscvsxddp f1, f0322; CHECK-NEXT: blr323entry:324 %arg.addr = alloca i32, align 4325 store i32 %arg, ptr %arg.addr, align 4326 %0 = load i32, ptr %arg.addr, align 4327 %conv = sitofp i32 %0 to double328 ret double %conv329}330 331; Function Attrs: nounwind332define zeroext i32 @_Z7testuiff(float %arg) {333; CHECK-LABEL: _Z7testuiff:334; CHECK: # %bb.0: # %entry335; CHECK-NEXT: xscvdpuxws f0, f1336; CHECK-NEXT: stfs f1, -4(r1)337; CHECK-NEXT: mffprwz r3, f0338; CHECK-NEXT: blr339entry:340 %arg.addr = alloca float, align 4341 store float %arg, ptr %arg.addr, align 4342 %0 = load float, ptr %arg.addr, align 4343 %conv = fptoui float %0 to i32344 ret i32 %conv345}346 347; Function Attrs: nounwind348define float @_Z7testfuij(i32 zeroext %arg) {349; CHECK-LABEL: _Z7testfuij:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: mtfprwz f0, r3352; CHECK-NEXT: stw r3, -4(r1)353; CHECK-NEXT: xscvuxdsp f1, f0354; CHECK-NEXT: blr355entry:356 %arg.addr = alloca i32, align 4357 store i32 %arg, ptr %arg.addr, align 4358 %0 = load i32, ptr %arg.addr, align 4359 %conv = uitofp i32 %0 to float360 ret float %conv361}362 363; Function Attrs: nounwind364define zeroext i32 @_Z7testuidd(double %arg) {365; CHECK-LABEL: _Z7testuidd:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: xscvdpuxws f0, f1368; CHECK-NEXT: stfd f1, -8(r1)369; CHECK-NEXT: mffprwz r3, f0370; CHECK-NEXT: blr371entry:372 %arg.addr = alloca double, align 8373 store double %arg, ptr %arg.addr, align 8374 %0 = load double, ptr %arg.addr, align 8375 %conv = fptoui double %0 to i32376 ret i32 %conv377}378 379; Function Attrs: nounwind380define double @_Z7testduij(i32 zeroext %arg) {381; CHECK-LABEL: _Z7testduij:382; CHECK: # %bb.0: # %entry383; CHECK-NEXT: mtfprwz f0, r3384; CHECK-NEXT: stw r3, -4(r1)385; CHECK-NEXT: xscvuxddp f1, f0386; CHECK-NEXT: blr387entry:388 %arg.addr = alloca i32, align 4389 store i32 %arg, ptr %arg.addr, align 4390 %0 = load i32, ptr %arg.addr, align 4391 %conv = uitofp i32 %0 to double392 ret double %conv393}394 395; Function Attrs: nounwind396define i64 @_Z7testllff(float %arg) {397; CHECK-LABEL: _Z7testllff:398; CHECK: # %bb.0: # %entry399; CHECK-NEXT: xscvdpsxds f0, f1400; CHECK-NEXT: stfs f1, -4(r1)401; CHECK-NEXT: mffprd r3, f0402; CHECK-NEXT: blr403entry:404 %arg.addr = alloca float, align 4405 store float %arg, ptr %arg.addr, align 4406 %0 = load float, ptr %arg.addr, align 4407 %conv = fptosi float %0 to i64408 ret i64 %conv409}410 411; Function Attrs: nounwind412define float @_Z7testfllx(i64 %arg) {413; CHECK-LABEL: _Z7testfllx:414; CHECK: # %bb.0: # %entry415; CHECK-NEXT: mtfprd f0, r3416; CHECK-NEXT: std r3, -8(r1)417; CHECK-NEXT: xscvsxdsp f1, f0418; CHECK-NEXT: blr419entry:420 %arg.addr = alloca i64, align 8421 store i64 %arg, ptr %arg.addr, align 8422 %0 = load i64, ptr %arg.addr, align 8423 %conv = sitofp i64 %0 to float424 ret float %conv425}426 427; Function Attrs: nounwind428define i64 @_Z7testlldd(double %arg) {429; CHECK-LABEL: _Z7testlldd:430; CHECK: # %bb.0: # %entry431; CHECK-NEXT: xscvdpsxds f0, f1432; CHECK-NEXT: stfd f1, -8(r1)433; CHECK-NEXT: mffprd r3, f0434; CHECK-NEXT: blr435entry:436 %arg.addr = alloca double, align 8437 store double %arg, ptr %arg.addr, align 8438 %0 = load double, ptr %arg.addr, align 8439 %conv = fptosi double %0 to i64440 ret i64 %conv441}442 443; Function Attrs: nounwind444define double @_Z7testdllx(i64 %arg) {445; CHECK-LABEL: _Z7testdllx:446; CHECK: # %bb.0: # %entry447; CHECK-NEXT: mtfprd f0, r3448; CHECK-NEXT: std r3, -8(r1)449; CHECK-NEXT: xscvsxddp f1, f0450; CHECK-NEXT: blr451entry:452 %arg.addr = alloca i64, align 8453 store i64 %arg, ptr %arg.addr, align 8454 %0 = load i64, ptr %arg.addr, align 8455 %conv = sitofp i64 %0 to double456 ret double %conv457}458 459; Function Attrs: nounwind460define i64 @_Z8testullff(float %arg) {461; CHECK-LABEL: _Z8testullff:462; CHECK: # %bb.0: # %entry463; CHECK-NEXT: xscvdpuxds f0, f1464; CHECK-NEXT: stfs f1, -4(r1)465; CHECK-NEXT: mffprd r3, f0466; CHECK-NEXT: blr467entry:468 %arg.addr = alloca float, align 4469 store float %arg, ptr %arg.addr, align 4470 %0 = load float, ptr %arg.addr, align 4471 %conv = fptoui float %0 to i64472 ret i64 %conv473}474 475; Function Attrs: nounwind476define float @_Z8testfully(i64 %arg) {477; CHECK-LABEL: _Z8testfully:478; CHECK: # %bb.0: # %entry479; CHECK-NEXT: mtfprd f0, r3480; CHECK-NEXT: std r3, -8(r1)481; CHECK-NEXT: xscvuxdsp f1, f0482; CHECK-NEXT: blr483entry:484 %arg.addr = alloca i64, align 8485 store i64 %arg, ptr %arg.addr, align 8486 %0 = load i64, ptr %arg.addr, align 8487 %conv = uitofp i64 %0 to float488 ret float %conv489}490 491; Function Attrs: nounwind492define i64 @_Z8testulldd(double %arg) {493; CHECK-LABEL: _Z8testulldd:494; CHECK: # %bb.0: # %entry495; CHECK-NEXT: xscvdpuxds f0, f1496; CHECK-NEXT: stfd f1, -8(r1)497; CHECK-NEXT: mffprd r3, f0498; CHECK-NEXT: blr499entry:500 %arg.addr = alloca double, align 8501 store double %arg, ptr %arg.addr, align 8502 %0 = load double, ptr %arg.addr, align 8503 %conv = fptoui double %0 to i64504 ret i64 %conv505}506 507; Function Attrs: nounwind508define double @_Z8testdully(i64 %arg) {509; CHECK-LABEL: _Z8testdully:510; CHECK: # %bb.0: # %entry511; CHECK-NEXT: mtfprd f0, r3512; CHECK-NEXT: std r3, -8(r1)513; CHECK-NEXT: xscvuxddp f1, f0514; CHECK-NEXT: blr515entry:516 %arg.addr = alloca i64, align 8517 store i64 %arg, ptr %arg.addr, align 8518 %0 = load i64, ptr %arg.addr, align 8519 %conv = uitofp i64 %0 to double520 ret double %conv521}522