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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s \4; RUN: --check-prefixes=CHECK,P85; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \6; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s \7; RUN: --check-prefixes=CHECK,P98; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \9; RUN: < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | \10; RUN: FileCheck %s -check-prefix=NOVSX11; RUN: llc -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 < %s -simplify-mir \12; RUN: -stop-after=machine-cp | FileCheck %s -check-prefix=MIR13 14declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)15declare i64 @llvm.experimental.constrained.fptosi.i64.f64(double, metadata)16declare i64 @llvm.experimental.constrained.fptoui.i64.f64(double, metadata)17declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)18 19declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)20declare i64 @llvm.experimental.constrained.fptosi.i64.f32(float, metadata)21declare i64 @llvm.experimental.constrained.fptoui.i64.f32(float, metadata)22declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)23 24declare double @llvm.experimental.constrained.sitofp.f64.i32(i32, metadata, metadata)25declare double @llvm.experimental.constrained.sitofp.f64.i64(i64, metadata, metadata)26declare double @llvm.experimental.constrained.uitofp.f64.i32(i32, metadata, metadata)27declare double @llvm.experimental.constrained.uitofp.f64.i64(i64, metadata, metadata)28 29declare float @llvm.experimental.constrained.sitofp.f32.i64(i64, metadata, metadata)30declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)31declare float @llvm.experimental.constrained.uitofp.f32.i32(i32, metadata, metadata)32declare float @llvm.experimental.constrained.uitofp.f32.i64(i64, metadata, metadata)33 34define i32 @d_to_i32(double %m) #0 {35; CHECK-LABEL: d_to_i32:36; CHECK: # %bb.0: # %entry37; CHECK-NEXT: xscvdpsxws f0, f138; CHECK-NEXT: mffprwz r3, f039; CHECK-NEXT: blr40;41; NOVSX-LABEL: d_to_i32:42; NOVSX: # %bb.0: # %entry43; NOVSX-NEXT: fctiwz f0, f144; NOVSX-NEXT: addi r3, r1, -445; NOVSX-NEXT: stfiwx f0, 0, r346; NOVSX-NEXT: lwz r3, -4(r1)47; NOVSX-NEXT: blr48entry:49 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict")50 ret i32 %conv51}52 53define i64 @d_to_i64(double %m) #0 {54; CHECK-LABEL: d_to_i64:55; CHECK: # %bb.0: # %entry56; CHECK-NEXT: xscvdpsxds f0, f157; CHECK-NEXT: mffprd r3, f058; CHECK-NEXT: blr59;60; NOVSX-LABEL: d_to_i64:61; NOVSX: # %bb.0: # %entry62; NOVSX-NEXT: fctidz f0, f163; NOVSX-NEXT: stfd f0, -8(r1)64; NOVSX-NEXT: ld r3, -8(r1)65; NOVSX-NEXT: blr66entry:67 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict")68 ret i64 %conv69}70 71define i64 @d_to_u64(double %m) #0 {72; CHECK-LABEL: d_to_u64:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: xscvdpuxds f0, f175; CHECK-NEXT: mffprd r3, f076; CHECK-NEXT: blr77;78; NOVSX-LABEL: d_to_u64:79; NOVSX: # %bb.0: # %entry80; NOVSX-NEXT: fctiduz f0, f181; NOVSX-NEXT: stfd f0, -8(r1)82; NOVSX-NEXT: ld r3, -8(r1)83; NOVSX-NEXT: blr84entry:85 %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.strict")86 ret i64 %conv87}88 89define zeroext i32 @d_to_u32(double %m) #0 {90; CHECK-LABEL: d_to_u32:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: xscvdpuxws f0, f193; CHECK-NEXT: mffprwz r3, f094; CHECK-NEXT: blr95;96; NOVSX-LABEL: d_to_u32:97; NOVSX: # %bb.0: # %entry98; NOVSX-NEXT: fctiwuz f0, f199; NOVSX-NEXT: addi r3, r1, -4100; NOVSX-NEXT: stfiwx f0, 0, r3101; NOVSX-NEXT: lwz r3, -4(r1)102; NOVSX-NEXT: blr103entry:104 %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.strict")105 ret i32 %conv106}107 108define signext i32 @f_to_i32(float %m) #0 {109; CHECK-LABEL: f_to_i32:110; CHECK: # %bb.0: # %entry111; CHECK-NEXT: xscvdpsxws f0, f1112; CHECK-NEXT: mffprwz r3, f0113; CHECK-NEXT: extsw r3, r3114; CHECK-NEXT: blr115;116; NOVSX-LABEL: f_to_i32:117; NOVSX: # %bb.0: # %entry118; NOVSX-NEXT: fctiwz f0, f1119; NOVSX-NEXT: addi r3, r1, -4120; NOVSX-NEXT: stfiwx f0, 0, r3121; NOVSX-NEXT: lwa r3, -4(r1)122; NOVSX-NEXT: blr123entry:124 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict")125 ret i32 %conv126}127 128define i64 @f_to_i64(float %m) #0 {129; CHECK-LABEL: f_to_i64:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: xscvdpsxds f0, f1132; CHECK-NEXT: mffprd r3, f0133; CHECK-NEXT: blr134;135; NOVSX-LABEL: f_to_i64:136; NOVSX: # %bb.0: # %entry137; NOVSX-NEXT: fctidz f0, f1138; NOVSX-NEXT: stfd f0, -8(r1)139; NOVSX-NEXT: ld r3, -8(r1)140; NOVSX-NEXT: blr141entry:142 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict")143 ret i64 %conv144}145 146define i64 @f_to_u64(float %m) #0 {147; CHECK-LABEL: f_to_u64:148; CHECK: # %bb.0: # %entry149; CHECK-NEXT: xscvdpuxds f0, f1150; CHECK-NEXT: mffprd r3, f0151; CHECK-NEXT: blr152;153; NOVSX-LABEL: f_to_u64:154; NOVSX: # %bb.0: # %entry155; NOVSX-NEXT: fctiduz f0, f1156; NOVSX-NEXT: stfd f0, -8(r1)157; NOVSX-NEXT: ld r3, -8(r1)158; NOVSX-NEXT: blr159entry:160 %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.strict")161 ret i64 %conv162}163 164define zeroext i32 @f_to_u32(float %m) #0 {165; CHECK-LABEL: f_to_u32:166; CHECK: # %bb.0: # %entry167; CHECK-NEXT: xscvdpuxws f0, f1168; CHECK-NEXT: mffprwz r3, f0169; CHECK-NEXT: blr170;171; NOVSX-LABEL: f_to_u32:172; NOVSX: # %bb.0: # %entry173; NOVSX-NEXT: fctiwuz f0, f1174; NOVSX-NEXT: addi r3, r1, -4175; NOVSX-NEXT: stfiwx f0, 0, r3176; NOVSX-NEXT: lwz r3, -4(r1)177; NOVSX-NEXT: blr178entry:179 %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.strict")180 ret i32 %conv181}182 183define double @i32_to_d(i32 signext %m) #0 {184; CHECK-LABEL: i32_to_d:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: mtfprwa f0, r3187; CHECK-NEXT: xscvsxddp f1, f0188; CHECK-NEXT: blr189;190; NOVSX-LABEL: i32_to_d:191; NOVSX: # %bb.0: # %entry192; NOVSX-NEXT: stw r3, -4(r1)193; NOVSX-NEXT: addi r3, r1, -4194; NOVSX-NEXT: lfiwax f0, 0, r3195; NOVSX-NEXT: fcfid f1, f0196; NOVSX-NEXT: blr197entry:198 %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")199 ret double %conv200}201 202define double @i64_to_d(i64 %m) #0 {203; CHECK-LABEL: i64_to_d:204; CHECK: # %bb.0: # %entry205; CHECK-NEXT: mtfprd f0, r3206; CHECK-NEXT: xscvsxddp f1, f0207; CHECK-NEXT: blr208;209; NOVSX-LABEL: i64_to_d:210; NOVSX: # %bb.0: # %entry211; NOVSX-NEXT: std r3, -8(r1)212; NOVSX-NEXT: lfd f0, -8(r1)213; NOVSX-NEXT: fcfid f1, f0214; NOVSX-NEXT: blr215entry:216 %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")217 ret double %conv218}219 220define double @u32_to_d(i32 zeroext %m) #0 {221; CHECK-LABEL: u32_to_d:222; CHECK: # %bb.0: # %entry223; CHECK-NEXT: mtfprwz f0, r3224; CHECK-NEXT: xscvuxddp f1, f0225; CHECK-NEXT: blr226;227; NOVSX-LABEL: u32_to_d:228; NOVSX: # %bb.0: # %entry229; NOVSX-NEXT: stw r3, -4(r1)230; NOVSX-NEXT: addi r3, r1, -4231; NOVSX-NEXT: lfiwzx f0, 0, r3232; NOVSX-NEXT: fcfidu f1, f0233; NOVSX-NEXT: blr234entry:235 %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")236 ret double %conv237}238 239define double @u64_to_d(i64 %m) #0 {240; CHECK-LABEL: u64_to_d:241; CHECK: # %bb.0: # %entry242; CHECK-NEXT: mtfprd f0, r3243; CHECK-NEXT: xscvuxddp f1, f0244; CHECK-NEXT: blr245;246; NOVSX-LABEL: u64_to_d:247; NOVSX: # %bb.0: # %entry248; NOVSX-NEXT: std r3, -8(r1)249; NOVSX-NEXT: lfd f0, -8(r1)250; NOVSX-NEXT: fcfidu f1, f0251; NOVSX-NEXT: blr252entry:253 %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")254 ret double %conv255}256 257define float @i32_to_f(i32 signext %m) #0 {258; CHECK-LABEL: i32_to_f:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: mtfprwa f0, r3261; CHECK-NEXT: xscvsxdsp f1, f0262; CHECK-NEXT: blr263;264; NOVSX-LABEL: i32_to_f:265; NOVSX: # %bb.0: # %entry266; NOVSX-NEXT: stw r3, -4(r1)267; NOVSX-NEXT: addi r3, r1, -4268; NOVSX-NEXT: lfiwax f0, 0, r3269; NOVSX-NEXT: fcfids f1, f0270; NOVSX-NEXT: blr271entry:272 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")273 ret float %conv274}275 276define float @i64_to_f(i64 %m) #0 {277; CHECK-LABEL: i64_to_f:278; CHECK: # %bb.0: # %entry279; CHECK-NEXT: mtfprd f0, r3280; CHECK-NEXT: xscvsxdsp f1, f0281; CHECK-NEXT: blr282;283; NOVSX-LABEL: i64_to_f:284; NOVSX: # %bb.0: # %entry285; NOVSX-NEXT: std r3, -8(r1)286; NOVSX-NEXT: lfd f0, -8(r1)287; NOVSX-NEXT: fcfids f1, f0288; NOVSX-NEXT: blr289entry:290 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")291 ret float %conv292}293 294define float @u32_to_f(i32 zeroext %m) #0 {295; CHECK-LABEL: u32_to_f:296; CHECK: # %bb.0: # %entry297; CHECK-NEXT: mtfprwz f0, r3298; CHECK-NEXT: xscvuxdsp f1, f0299; CHECK-NEXT: blr300;301; NOVSX-LABEL: u32_to_f:302; NOVSX: # %bb.0: # %entry303; NOVSX-NEXT: stw r3, -4(r1)304; NOVSX-NEXT: addi r3, r1, -4305; NOVSX-NEXT: lfiwzx f0, 0, r3306; NOVSX-NEXT: fcfidus f1, f0307; NOVSX-NEXT: blr308entry:309 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")310 ret float %conv311}312 313define float @u64_to_f(i64 %m) #0 {314; CHECK-LABEL: u64_to_f:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: mtfprd f0, r3317; CHECK-NEXT: xscvuxdsp f1, f0318; CHECK-NEXT: blr319;320; NOVSX-LABEL: u64_to_f:321; NOVSX: # %bb.0: # %entry322; NOVSX-NEXT: std r3, -8(r1)323; NOVSX-NEXT: lfd f0, -8(r1)324; NOVSX-NEXT: fcfidus f1, f0325; NOVSX-NEXT: blr326entry:327 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")328 ret float %conv329}330 331define void @d_to_i32_store(double %m, ptr %addr) #0 {332; CHECK-LABEL: d_to_i32_store:333; CHECK: # %bb.0: # %entry334; CHECK-NEXT: xscvdpsxws f0, f1335; CHECK-NEXT: stfiwx f0, 0, r4336; CHECK-NEXT: blr337;338; NOVSX-LABEL: d_to_i32_store:339; NOVSX: # %bb.0: # %entry340; NOVSX-NEXT: fctiwz f0, f1341; NOVSX-NEXT: addi r3, r1, -4342; NOVSX-NEXT: stfiwx f0, 0, r3343; NOVSX-NEXT: lwz r3, -4(r1)344; NOVSX-NEXT: stw r3, 0(r4)345; NOVSX-NEXT: blr346entry:347 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.strict")348 store i32 %conv, ptr %addr, align 4349 ret void350}351 352define void @d_to_i64_store(double %m, ptr %addr) #0 {353; P8-LABEL: d_to_i64_store:354; P8: # %bb.0: # %entry355; P8-NEXT: xscvdpsxds f0, f1356; P8-NEXT: stxsdx f0, 0, r4357; P8-NEXT: blr358;359; P9-LABEL: d_to_i64_store:360; P9: # %bb.0: # %entry361; P9-NEXT: xscvdpsxds v2, f1362; P9-NEXT: stxsd v2, 0(r4)363; P9-NEXT: blr364;365; NOVSX-LABEL: d_to_i64_store:366; NOVSX: # %bb.0: # %entry367; NOVSX-NEXT: fctidz f0, f1368; NOVSX-NEXT: stfd f0, -8(r1)369; NOVSX-NEXT: ld r3, -8(r1)370; NOVSX-NEXT: std r3, 0(r4)371; NOVSX-NEXT: blr372entry:373 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.strict")374 store i64 %conv, ptr %addr, align 8375 ret void376}377 378define void @d_to_u64_store(double %m, ptr %addr) #0 {379; P8-LABEL: d_to_u64_store:380; P8: # %bb.0: # %entry381; P8-NEXT: xscvdpuxds f0, f1382; P8-NEXT: stxsdx f0, 0, r4383; P8-NEXT: blr384;385; P9-LABEL: d_to_u64_store:386; P9: # %bb.0: # %entry387; P9-NEXT: xscvdpuxds v2, f1388; P9-NEXT: stxsd v2, 0(r4)389; P9-NEXT: blr390;391; NOVSX-LABEL: d_to_u64_store:392; NOVSX: # %bb.0: # %entry393; NOVSX-NEXT: fctiduz f0, f1394; NOVSX-NEXT: stfd f0, -8(r1)395; NOVSX-NEXT: ld r3, -8(r1)396; NOVSX-NEXT: std r3, 0(r4)397; NOVSX-NEXT: blr398entry:399 %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.strict")400 store i64 %conv, ptr %addr, align 8401 ret void402}403 404define void @d_to_u32_store(double %m, ptr %addr) #0 {405; CHECK-LABEL: d_to_u32_store:406; CHECK: # %bb.0: # %entry407; CHECK-NEXT: xscvdpuxws f0, f1408; CHECK-NEXT: stfiwx f0, 0, r4409; CHECK-NEXT: blr410;411; NOVSX-LABEL: d_to_u32_store:412; NOVSX: # %bb.0: # %entry413; NOVSX-NEXT: fctiwuz f0, f1414; NOVSX-NEXT: addi r3, r1, -4415; NOVSX-NEXT: stfiwx f0, 0, r3416; NOVSX-NEXT: lwz r3, -4(r1)417; NOVSX-NEXT: stw r3, 0(r4)418; NOVSX-NEXT: blr419entry:420 %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.strict")421 store i32 %conv, ptr %addr, align 4422 ret void423}424 425define void @f_to_i32_store(float %m, ptr %addr) #0 {426; CHECK-LABEL: f_to_i32_store:427; CHECK: # %bb.0: # %entry428; CHECK-NEXT: xscvdpsxws f0, f1429; CHECK-NEXT: stfiwx f0, 0, r4430; CHECK-NEXT: blr431;432; NOVSX-LABEL: f_to_i32_store:433; NOVSX: # %bb.0: # %entry434; NOVSX-NEXT: fctiwz f0, f1435; NOVSX-NEXT: addi r3, r1, -4436; NOVSX-NEXT: stfiwx f0, 0, r3437; NOVSX-NEXT: lwz r3, -4(r1)438; NOVSX-NEXT: stw r3, 0(r4)439; NOVSX-NEXT: blr440entry:441 %conv = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.strict")442 store i32 %conv, ptr %addr, align 4443 ret void444}445 446define void @f_to_i64_store(float %m, ptr %addr) #0 {447; P8-LABEL: f_to_i64_store:448; P8: # %bb.0: # %entry449; P8-NEXT: xscvdpsxds f0, f1450; P8-NEXT: stxsdx f0, 0, r4451; P8-NEXT: blr452;453; P9-LABEL: f_to_i64_store:454; P9: # %bb.0: # %entry455; P9-NEXT: xscvdpsxds v2, f1456; P9-NEXT: stxsd v2, 0(r4)457; P9-NEXT: blr458;459; NOVSX-LABEL: f_to_i64_store:460; NOVSX: # %bb.0: # %entry461; NOVSX-NEXT: fctidz f0, f1462; NOVSX-NEXT: stfd f0, -8(r1)463; NOVSX-NEXT: ld r3, -8(r1)464; NOVSX-NEXT: std r3, 0(r4)465; NOVSX-NEXT: blr466entry:467 %conv = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.strict")468 store i64 %conv, ptr %addr, align 8469 ret void470}471 472define void @f_to_u64_store(float %m, ptr %addr) #0 {473; P8-LABEL: f_to_u64_store:474; P8: # %bb.0: # %entry475; P8-NEXT: xscvdpuxds f0, f1476; P8-NEXT: stxsdx f0, 0, r4477; P8-NEXT: blr478;479; P9-LABEL: f_to_u64_store:480; P9: # %bb.0: # %entry481; P9-NEXT: xscvdpuxds v2, f1482; P9-NEXT: stxsd v2, 0(r4)483; P9-NEXT: blr484;485; NOVSX-LABEL: f_to_u64_store:486; NOVSX: # %bb.0: # %entry487; NOVSX-NEXT: fctiduz f0, f1488; NOVSX-NEXT: stfd f0, -8(r1)489; NOVSX-NEXT: ld r3, -8(r1)490; NOVSX-NEXT: std r3, 0(r4)491; NOVSX-NEXT: blr492entry:493 %conv = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.strict")494 store i64 %conv, ptr %addr, align 8495 ret void496}497 498define void @f_to_u32_store(float %m, ptr %addr) #0 {499; CHECK-LABEL: f_to_u32_store:500; CHECK: # %bb.0: # %entry501; CHECK-NEXT: xscvdpuxws f0, f1502; CHECK-NEXT: stfiwx f0, 0, r4503; CHECK-NEXT: blr504;505; NOVSX-LABEL: f_to_u32_store:506; NOVSX: # %bb.0: # %entry507; NOVSX-NEXT: fctiwuz f0, f1508; NOVSX-NEXT: addi r3, r1, -4509; NOVSX-NEXT: stfiwx f0, 0, r3510; NOVSX-NEXT: lwz r3, -4(r1)511; NOVSX-NEXT: stw r3, 0(r4)512; NOVSX-NEXT: blr513entry:514 %conv = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.strict")515 store i32 %conv, ptr %addr, align 4516 ret void517}518 519define double @load_i32_to_d(ptr %addr) #0 {520; CHECK-LABEL: load_i32_to_d:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: lfiwax f0, 0, r3523; CHECK-NEXT: xscvsxddp f1, f0524; CHECK-NEXT: blr525;526; NOVSX-LABEL: load_i32_to_d:527; NOVSX: # %bb.0: # %entry528; NOVSX-NEXT: lfiwax f0, 0, r3529; NOVSX-NEXT: fcfid f1, f0530; NOVSX-NEXT: blr531entry:532 %m = load i32, ptr %addr, align 4533 %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")534 ret double %conv535}536 537define double @load_i64_to_d(ptr %addr) #0 {538; CHECK-LABEL: load_i64_to_d:539; CHECK: # %bb.0: # %entry540; CHECK-NEXT: lfd f0, 0(r3)541; CHECK-NEXT: xscvsxddp f1, f0542; CHECK-NEXT: blr543;544; NOVSX-LABEL: load_i64_to_d:545; NOVSX: # %bb.0: # %entry546; NOVSX-NEXT: lfd f0, 0(r3)547; NOVSX-NEXT: fcfid f1, f0548; NOVSX-NEXT: blr549entry:550 %m = load i64, ptr %addr, align 8551 %conv = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")552 ret double %conv553}554 555define double @load_u32_to_d(ptr %addr) #0 {556; CHECK-LABEL: load_u32_to_d:557; CHECK: # %bb.0: # %entry558; CHECK-NEXT: lfiwzx f0, 0, r3559; CHECK-NEXT: xscvuxddp f1, f0560; CHECK-NEXT: blr561;562; NOVSX-LABEL: load_u32_to_d:563; NOVSX: # %bb.0: # %entry564; NOVSX-NEXT: lfiwzx f0, 0, r3565; NOVSX-NEXT: fcfidu f1, f0566; NOVSX-NEXT: blr567entry:568 %m = load i32, ptr %addr, align 4569 %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")570 ret double %conv571}572 573define double @load_u64_to_d(ptr %addr) #0 {574; CHECK-LABEL: load_u64_to_d:575; CHECK: # %bb.0: # %entry576; CHECK-NEXT: lfd f0, 0(r3)577; CHECK-NEXT: xscvuxddp f1, f0578; CHECK-NEXT: blr579;580; NOVSX-LABEL: load_u64_to_d:581; NOVSX: # %bb.0: # %entry582; NOVSX-NEXT: lfd f0, 0(r3)583; NOVSX-NEXT: fcfidu f1, f0584; NOVSX-NEXT: blr585entry:586 %m = load i64, ptr %addr, align 8587 %conv = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")588 ret double %conv589}590 591define float @load_i32_to_f(ptr %addr) #0 {592; CHECK-LABEL: load_i32_to_f:593; CHECK: # %bb.0: # %entry594; CHECK-NEXT: lfiwax f0, 0, r3595; CHECK-NEXT: xscvsxdsp f1, f0596; CHECK-NEXT: blr597;598; NOVSX-LABEL: load_i32_to_f:599; NOVSX: # %bb.0: # %entry600; NOVSX-NEXT: lfiwax f0, 0, r3601; NOVSX-NEXT: fcfids f1, f0602; NOVSX-NEXT: blr603entry:604 %m = load i32, ptr %addr, align 4605 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")606 ret float %conv607}608 609define float @load_i64_to_f(ptr %addr) #0 {610; CHECK-LABEL: load_i64_to_f:611; CHECK: # %bb.0: # %entry612; CHECK-NEXT: lfd f0, 0(r3)613; CHECK-NEXT: xscvsxdsp f1, f0614; CHECK-NEXT: blr615;616; NOVSX-LABEL: load_i64_to_f:617; NOVSX: # %bb.0: # %entry618; NOVSX-NEXT: lfd f0, 0(r3)619; NOVSX-NEXT: fcfids f1, f0620; NOVSX-NEXT: blr621entry:622 %m = load i64, ptr %addr, align 8623 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")624 ret float %conv625}626 627define float @load_u32_to_f(ptr %addr) #0 {628; CHECK-LABEL: load_u32_to_f:629; CHECK: # %bb.0: # %entry630; CHECK-NEXT: lfiwzx f0, 0, r3631; CHECK-NEXT: xscvuxdsp f1, f0632; CHECK-NEXT: blr633;634; NOVSX-LABEL: load_u32_to_f:635; NOVSX: # %bb.0: # %entry636; NOVSX-NEXT: lfiwzx f0, 0, r3637; NOVSX-NEXT: fcfidus f1, f0638; NOVSX-NEXT: blr639entry:640 %m = load i32, ptr %addr, align 4641 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")642 ret float %conv643}644 645define float @load_u64_to_f(ptr %addr) #0 {646; CHECK-LABEL: load_u64_to_f:647; CHECK: # %bb.0: # %entry648; CHECK-NEXT: lfd f0, 0(r3)649; CHECK-NEXT: xscvuxdsp f1, f0650; CHECK-NEXT: blr651;652; NOVSX-LABEL: load_u64_to_f:653; NOVSX: # %bb.0: # %entry654; NOVSX-NEXT: lfd f0, 0(r3)655; NOVSX-NEXT: fcfidus f1, f0656; NOVSX-NEXT: blr657entry:658 %m = load i64, ptr %addr, align 8659 %conv = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.strict")660 ret float %conv661}662 663define void @fptoint_nofpexcept_f64(double %m, ptr %addr1, ptr %addr2) #0 {664; MIR-LABEL: name: fptoint_nofpexcept_f64665; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS666; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS667; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS668; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS669entry:670 %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %m, metadata !"fpexcept.ignore")671 %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %m, metadata !"fpexcept.ignore")672 %conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %m, metadata !"fpexcept.ignore")673 %conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %m, metadata !"fpexcept.ignore")674 store volatile i32 %conv1, ptr %addr1, align 4675 store volatile i32 %conv2, ptr %addr1, align 4676 store volatile i64 %conv3, ptr %addr2, align 8677 store volatile i64 %conv4, ptr %addr2, align 8678 ret void679}680 681define void @fptoint_nofpexcept_f32(float %m, ptr %addr1, ptr %addr2) #0 {682; MIR-LABEL: name: fptoint_nofpexcept_f32683; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS684; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS685; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPSXDS686; MIR: renamable $vf{{[0-9]+}} = nofpexcept XSCVDPUXDS687entry:688 %conv1 = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %m, metadata !"fpexcept.ignore")689 %conv2 = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %m, metadata !"fpexcept.ignore")690 %conv3 = tail call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %m, metadata !"fpexcept.ignore")691 %conv4 = tail call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %m, metadata !"fpexcept.ignore")692 store volatile i32 %conv1, ptr %addr1, align 4693 store volatile i32 %conv2, ptr %addr1, align 4694 store volatile i64 %conv3, ptr %addr2, align 8695 store volatile i64 %conv4, ptr %addr2, align 8696 ret void697}698 699define void @inttofp_nofpexcept_i32(i32 %m, ptr %addr1, ptr %addr2) #0 {700; MIR-LABEL: name: inttofp_nofpexcept_i32701; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP702; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP703; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDDP704; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDDP705entry:706 %conv1 = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")707 %conv2 = tail call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")708 %conv3 = tail call double @llvm.experimental.constrained.sitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")709 %conv4 = tail call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")710 store volatile float %conv1, ptr %addr1, align 4711 store volatile float %conv2, ptr %addr1, align 4712 store volatile double %conv3, ptr %addr2, align 8713 store volatile double %conv4, ptr %addr2, align 8714 ret void715}716 717define void @inttofp_nofpexcept_i64(i64 %m, ptr %addr1, ptr %addr2) #0 {718; MIR-LABEL: name: inttofp_nofpexcept_i64719; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDSP720; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDSP721; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVSXDDP722; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVUXDDP723entry:724 %conv1 = tail call float @llvm.experimental.constrained.sitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")725 %conv2 = tail call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")726 %conv3 = tail call double @llvm.experimental.constrained.sitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")727 %conv4 = tail call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")728 store volatile float %conv1, ptr %addr1, align 4729 store volatile float %conv2, ptr %addr1, align 4730 store volatile double %conv3, ptr %addr2, align 8731 store volatile double %conv4, ptr %addr2, align 8732 ret void733}734 735define <2 x double> @inttofp_nofpexcept_vec(<2 x i16> %m) #0 {736; MIR-LABEL: name: inttofp_nofpexcept_vec737; MIR: renamable $v{{[0-9]+}} = nofpexcept XVCVSXDDP738entry:739 %conv = tail call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16> %m, metadata !"round.dynamic", metadata !"fpexcept.ignore")740 ret <2 x double> %conv741}742 743declare <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i16(<2 x i16>, metadata, metadata)744 745attributes #0 = { strictfp }746