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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \3; RUN: < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr9 -O0 | FileCheck %s4 5define i32 @une_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {6; CHECK-LABEL: une_ppcf128:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: fcmpu cr0, f1, f39; CHECK-NEXT: crmove 4*cr5+lt, eq10; CHECK-NEXT: fcmpu cr1, f2, f411; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+eq12; CHECK-NEXT: crnot 4*cr5+gt, 4*cr5+gt13; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt14; CHECK-NEXT: crmove 4*cr5+lt, eq15; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt16; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+lt17; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt18; CHECK-NEXT: li r4, 019; CHECK-NEXT: li r3, 120; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt21; CHECK-NEXT: clrldi r3, r3, 3222; CHECK-NEXT: blr23entry:24 %0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"une", metadata !"fpexcept.strict") #025 %1 = zext i1 %0 to i3226 ret i32 %127}28 29; This is a different branch from une30define i32 @ogt_ppcf128(ppc_fp128 %a, ppc_fp128 %b) #0 {31; CHECK-LABEL: ogt_ppcf128:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: fcmpu cr0, f1, f334; CHECK-NEXT: crmove 4*cr5+lt, eq35; CHECK-NEXT: fcmpu cr1, f2, f436; CHECK-NEXT: crmove 4*cr5+gt, 4*cr1+gt37; CHECK-NEXT: crand 4*cr5+gt, 4*cr5+lt, 4*cr5+gt38; CHECK-NEXT: crmove 4*cr5+lt, eq39; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt40; CHECK-NEXT: crmove 4*cr5+eq, gt41; CHECK-NEXT: crand 4*cr5+lt, 4*cr5+lt, 4*cr5+eq42; CHECK-NEXT: cror 4*cr5+lt, 4*cr5+lt, 4*cr5+gt43; CHECK-NEXT: li r4, 044; CHECK-NEXT: li r3, 145; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt46; CHECK-NEXT: clrldi r3, r3, 3247; CHECK-NEXT: blr48entry:49 %0 = call i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128 %a, ppc_fp128 %b, metadata !"ogt", metadata !"fpexcept.strict") #050 %1 = zext i1 %0 to i3251 ret i32 %152}53 54define i1 @test_f128(fp128 %a, fp128 %b) #0 {55; CHECK-LABEL: test_f128:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: xscmpuqp cr0, v2, v358; CHECK-NEXT: crmove 4*cr5+lt, eq59; CHECK-NEXT: crnot 4*cr5+lt, 4*cr5+lt60; CHECK-NEXT: li r4, 061; CHECK-NEXT: li r3, 162; CHECK-NEXT: isel r3, r3, r4, 4*cr5+lt63; CHECK-NEXT: blr64entry:65 %0 = call i1 @llvm.experimental.constrained.fcmp.f128(fp128 %a, fp128 %b, metadata !"une", metadata !"fpexcept.strict") #066 ret i1 %067}68 69define i1 @testbr_f64(double %a, double %b) #0 {70; CHECK-LABEL: testbr_f64:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: fcmpu cr0, f1, f273; CHECK-NEXT: crmove 4*cr5+lt, eq74; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB3_275; CHECK-NEXT: b .LBB3_176; CHECK-NEXT: .LBB3_1: # %tr77; CHECK-NEXT: li r3, -178; CHECK-NEXT: blr79; CHECK-NEXT: .LBB3_2: # %fl80; CHECK-NEXT: li r3, 081; CHECK-NEXT: blr82entry:83 %0 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"une", metadata !"fpexcept.strict") #084 br i1 %0, label %tr, label %fl85tr:86 ret i1 true87fl:88 ret i1 false89}90 91define i1 @testbr_f32(float %a, float %b) #0 {92; CHECK-LABEL: testbr_f32:93; CHECK: # %bb.0: # %entry94; CHECK-NEXT: fcmpu cr0, f1, f295; CHECK-NEXT: crmove 4*cr5+lt, eq96; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB4_297; CHECK-NEXT: b .LBB4_198; CHECK-NEXT: .LBB4_1: # %tr99; CHECK-NEXT: li r3, -1100; CHECK-NEXT: blr101; CHECK-NEXT: .LBB4_2: # %fl102; CHECK-NEXT: li r3, 0103; CHECK-NEXT: blr104entry:105 %0 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"une", metadata !"fpexcept.strict") #0106 br i1 %0, label %tr, label %fl107tr:108 ret i1 true109fl:110 ret i1 false111}112 113declare i1 @llvm.experimental.constrained.fcmp.ppcf128(ppc_fp128, ppc_fp128, metadata, metadata)114declare i1 @llvm.experimental.constrained.fcmp.f128(fp128, fp128, metadata, metadata)115declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)116declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)117 118attributes #0 = { strictfp }119