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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc-unknown-linux -mattr=spe | FileCheck %s -check-prefix=SPE3 4define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {5; SPE-LABEL: test_f32_oeq_s:6; SPE: # %bb.0:7; SPE-NEXT: efscmpeq cr0, r5, r68; SPE-NEXT: bclr 12, gt, 09; SPE-NEXT: # %bb.1:10; SPE-NEXT: mr r3, r411; SPE-NEXT: blr12 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oeq", metadata !"fpexcept.strict") #013 %res = select i1 %cond, i32 %a, i32 %b14 ret i32 %res15}16 17define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {18; SPE-LABEL: test_f32_ogt_s:19; SPE: # %bb.0:20; SPE-NEXT: efscmpgt cr0, r5, r621; SPE-NEXT: bclr 12, gt, 022; SPE-NEXT: # %bb.1:23; SPE-NEXT: mr r3, r424; SPE-NEXT: blr25 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ogt", metadata !"fpexcept.strict") #026 %res = select i1 %cond, i32 %a, i32 %b27 ret i32 %res28}29 30define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {31; SPE-LABEL: test_f32_oge_s:32; SPE: # %bb.0:33; SPE-NEXT: efscmpeq cr0, r6, r634; SPE-NEXT: bc 4, gt, .LBB2_335; SPE-NEXT: # %bb.1:36; SPE-NEXT: efscmpeq cr0, r5, r537; SPE-NEXT: bc 4, gt, .LBB2_338; SPE-NEXT: # %bb.2:39; SPE-NEXT: efscmplt cr0, r5, r640; SPE-NEXT: bclr 4, gt, 041; SPE-NEXT: .LBB2_3:42; SPE-NEXT: mr r3, r443; SPE-NEXT: blr44 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oge", metadata !"fpexcept.strict") #045 %res = select i1 %cond, i32 %a, i32 %b46 ret i32 %res47}48 49define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {50; SPE-LABEL: test_f32_olt_s:51; SPE: # %bb.0:52; SPE-NEXT: efscmplt cr0, r5, r653; SPE-NEXT: bclr 12, gt, 054; SPE-NEXT: # %bb.1:55; SPE-NEXT: mr r3, r456; SPE-NEXT: blr57 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"olt", metadata !"fpexcept.strict") #058 %res = select i1 %cond, i32 %a, i32 %b59 ret i32 %res60}61 62define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {63; SPE-LABEL: test_f32_ole_s:64; SPE: # %bb.0:65; SPE-NEXT: efscmpeq cr0, r6, r666; SPE-NEXT: bc 4, gt, .LBB4_367; SPE-NEXT: # %bb.1:68; SPE-NEXT: efscmpeq cr0, r5, r569; SPE-NEXT: bc 4, gt, .LBB4_370; SPE-NEXT: # %bb.2:71; SPE-NEXT: efscmpgt cr0, r5, r672; SPE-NEXT: bclr 4, gt, 073; SPE-NEXT: .LBB4_3:74; SPE-NEXT: mr r3, r475; SPE-NEXT: blr76 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ole", metadata !"fpexcept.strict") #077 %res = select i1 %cond, i32 %a, i32 %b78 ret i32 %res79}80 81define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {82; SPE-LABEL: test_f32_one_s:83; SPE: # %bb.0:84; SPE-NEXT: efscmplt cr0, r5, r685; SPE-NEXT: bclr 12, gt, 086; SPE-NEXT: # %bb.1:87; SPE-NEXT: efscmpgt cr0, r5, r688; SPE-NEXT: bclr 12, gt, 089; SPE-NEXT: # %bb.2:90; SPE-NEXT: mr r3, r491; SPE-NEXT: blr92 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"one", metadata !"fpexcept.strict") #093 %res = select i1 %cond, i32 %a, i32 %b94 ret i32 %res95}96 97define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {98; SPE-LABEL: test_f32_ord_s:99; SPE: # %bb.0:100; SPE-NEXT: efscmpeq cr0, r6, r6101; SPE-NEXT: bc 4, gt, .LBB6_2102; SPE-NEXT: # %bb.1:103; SPE-NEXT: efscmpeq cr0, r5, r5104; SPE-NEXT: bclr 12, gt, 0105; SPE-NEXT: .LBB6_2:106; SPE-NEXT: mr r3, r4107; SPE-NEXT: blr108 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ord", metadata !"fpexcept.strict") #0109 %res = select i1 %cond, i32 %a, i32 %b110 ret i32 %res111}112 113define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {114; SPE-LABEL: test_f32_ueq_s:115; SPE: # %bb.0:116; SPE-NEXT: efscmplt cr0, r5, r6117; SPE-NEXT: bc 12, gt, .LBB7_3118; SPE-NEXT: # %bb.1:119; SPE-NEXT: efscmpgt cr0, r5, r6120; SPE-NEXT: bc 12, gt, .LBB7_3121; SPE-NEXT: # %bb.2:122; SPE-NEXT: mr r4, r3123; SPE-NEXT: .LBB7_3:124; SPE-NEXT: mr r3, r4125; SPE-NEXT: blr126 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0127 %res = select i1 %cond, i32 %a, i32 %b128 ret i32 %res129}130 131define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {132; SPE-LABEL: test_f32_ugt_s:133; SPE: # %bb.0:134; SPE-NEXT: efscmpeq cr0, r5, r5135; SPE-NEXT: bclr 4, gt, 0136; SPE-NEXT: # %bb.1:137; SPE-NEXT: efscmpeq cr0, r6, r6138; SPE-NEXT: bclr 4, gt, 0139; SPE-NEXT: # %bb.2:140; SPE-NEXT: efscmpgt cr0, r5, r6141; SPE-NEXT: bclr 12, gt, 0142; SPE-NEXT: # %bb.3:143; SPE-NEXT: mr r3, r4144; SPE-NEXT: blr145 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ugt", metadata !"fpexcept.strict") #0146 %res = select i1 %cond, i32 %a, i32 %b147 ret i32 %res148}149 150define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {151; SPE-LABEL: test_f32_uge_s:152; SPE: # %bb.0:153; SPE-NEXT: efscmplt cr0, r5, r6154; SPE-NEXT: bc 12, gt, .LBB9_2155; SPE-NEXT: # %bb.1:156; SPE-NEXT: mr r4, r3157; SPE-NEXT: .LBB9_2:158; SPE-NEXT: mr r3, r4159; SPE-NEXT: blr160 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0161 %res = select i1 %cond, i32 %a, i32 %b162 ret i32 %res163}164 165define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {166; SPE-LABEL: test_f32_ult_s:167; SPE: # %bb.0:168; SPE-NEXT: efscmpeq cr0, r5, r5169; SPE-NEXT: bclr 4, gt, 0170; SPE-NEXT: # %bb.1:171; SPE-NEXT: efscmpeq cr0, r6, r6172; SPE-NEXT: bclr 4, gt, 0173; SPE-NEXT: # %bb.2:174; SPE-NEXT: efscmplt cr0, r5, r6175; SPE-NEXT: bclr 12, gt, 0176; SPE-NEXT: # %bb.3:177; SPE-NEXT: mr r3, r4178; SPE-NEXT: blr179 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ult", metadata !"fpexcept.strict") #0180 %res = select i1 %cond, i32 %a, i32 %b181 ret i32 %res182}183 184define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {185; SPE-LABEL: test_f32_ule_s:186; SPE: # %bb.0:187; SPE-NEXT: efscmpgt cr0, r5, r6188; SPE-NEXT: bc 12, gt, .LBB11_2189; SPE-NEXT: # %bb.1:190; SPE-NEXT: mr r4, r3191; SPE-NEXT: .LBB11_2:192; SPE-NEXT: mr r3, r4193; SPE-NEXT: blr194 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0195 %res = select i1 %cond, i32 %a, i32 %b196 ret i32 %res197}198 199define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {200; SPE-LABEL: test_f32_une_s:201; SPE: # %bb.0:202; SPE-NEXT: efscmpeq cr0, r5, r6203; SPE-NEXT: bc 12, gt, .LBB12_2204; SPE-NEXT: # %bb.1:205; SPE-NEXT: mr r4, r3206; SPE-NEXT: .LBB12_2:207; SPE-NEXT: mr r3, r4208; SPE-NEXT: blr209 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0210 %res = select i1 %cond, i32 %a, i32 %b211 ret i32 %res212}213 214define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {215; SPE-LABEL: test_f32_uno_s:216; SPE: # %bb.0:217; SPE-NEXT: efscmpeq cr0, r5, r5218; SPE-NEXT: bclr 4, gt, 0219; SPE-NEXT: # %bb.1:220; SPE-NEXT: efscmpeq cr0, r6, r6221; SPE-NEXT: bclr 4, gt, 0222; SPE-NEXT: # %bb.2:223; SPE-NEXT: mr r3, r4224; SPE-NEXT: blr225 %cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uno", metadata !"fpexcept.strict") #0226 %res = select i1 %cond, i32 %a, i32 %b227 ret i32 %res228}229 230define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {231; SPE-LABEL: test_f64_oeq_s:232; SPE: # %bb.0:233; SPE-NEXT: evmergelo r7, r7, r8234; SPE-NEXT: evmergelo r5, r5, r6235; SPE-NEXT: efdcmpeq cr0, r5, r7236; SPE-NEXT: bclr 12, gt, 0237; SPE-NEXT: # %bb.1:238; SPE-NEXT: mr r3, r4239; SPE-NEXT: blr240 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oeq", metadata !"fpexcept.strict") #0241 %res = select i1 %cond, i32 %a, i32 %b242 ret i32 %res243}244 245define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {246; SPE-LABEL: test_f64_ogt_s:247; SPE: # %bb.0:248; SPE-NEXT: evmergelo r7, r7, r8249; SPE-NEXT: evmergelo r5, r5, r6250; SPE-NEXT: efdcmpgt cr0, r5, r7251; SPE-NEXT: bclr 12, gt, 0252; SPE-NEXT: # %bb.1:253; SPE-NEXT: mr r3, r4254; SPE-NEXT: blr255 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ogt", metadata !"fpexcept.strict") #0256 %res = select i1 %cond, i32 %a, i32 %b257 ret i32 %res258}259 260define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {261; SPE-LABEL: test_f64_oge_s:262; SPE: # %bb.0:263; SPE-NEXT: evmergelo r5, r5, r6264; SPE-NEXT: evmergelo r6, r7, r8265; SPE-NEXT: efdcmpeq cr0, r6, r6266; SPE-NEXT: bc 4, gt, .LBB16_3267; SPE-NEXT: # %bb.1:268; SPE-NEXT: efdcmpeq cr0, r5, r5269; SPE-NEXT: bc 4, gt, .LBB16_3270; SPE-NEXT: # %bb.2:271; SPE-NEXT: efdcmplt cr0, r5, r6272; SPE-NEXT: bclr 4, gt, 0273; SPE-NEXT: .LBB16_3:274; SPE-NEXT: mr r3, r4275; SPE-NEXT: blr276 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0277 %res = select i1 %cond, i32 %a, i32 %b278 ret i32 %res279}280 281define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {282; SPE-LABEL: test_f64_olt_s:283; SPE: # %bb.0:284; SPE-NEXT: evmergelo r7, r7, r8285; SPE-NEXT: evmergelo r5, r5, r6286; SPE-NEXT: efdcmplt cr0, r5, r7287; SPE-NEXT: bclr 12, gt, 0288; SPE-NEXT: # %bb.1:289; SPE-NEXT: mr r3, r4290; SPE-NEXT: blr291 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"olt", metadata !"fpexcept.strict") #0292 %res = select i1 %cond, i32 %a, i32 %b293 ret i32 %res294}295 296define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {297; SPE-LABEL: test_f64_ole_s:298; SPE: # %bb.0:299; SPE-NEXT: evmergelo r5, r5, r6300; SPE-NEXT: evmergelo r6, r7, r8301; SPE-NEXT: efdcmpeq cr0, r6, r6302; SPE-NEXT: bc 4, gt, .LBB18_3303; SPE-NEXT: # %bb.1:304; SPE-NEXT: efdcmpeq cr0, r5, r5305; SPE-NEXT: bc 4, gt, .LBB18_3306; SPE-NEXT: # %bb.2:307; SPE-NEXT: efdcmpgt cr0, r5, r6308; SPE-NEXT: bclr 4, gt, 0309; SPE-NEXT: .LBB18_3:310; SPE-NEXT: mr r3, r4311; SPE-NEXT: blr312 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0313 %res = select i1 %cond, i32 %a, i32 %b314 ret i32 %res315}316 317define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {318; SPE-LABEL: test_f64_one_s:319; SPE: # %bb.0:320; SPE-NEXT: evmergelo r7, r7, r8321; SPE-NEXT: evmergelo r5, r5, r6322; SPE-NEXT: efdcmplt cr0, r5, r7323; SPE-NEXT: bclr 12, gt, 0324; SPE-NEXT: # %bb.1:325; SPE-NEXT: efdcmpgt cr0, r5, r7326; SPE-NEXT: bclr 12, gt, 0327; SPE-NEXT: # %bb.2:328; SPE-NEXT: mr r3, r4329; SPE-NEXT: blr330 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"one", metadata !"fpexcept.strict") #0331 %res = select i1 %cond, i32 %a, i32 %b332 ret i32 %res333}334 335define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {336; SPE-LABEL: test_f64_ord_s:337; SPE: # %bb.0:338; SPE-NEXT: evmergelo r5, r5, r6339; SPE-NEXT: evmergelo r6, r7, r8340; SPE-NEXT: efdcmpeq cr0, r6, r6341; SPE-NEXT: bc 4, gt, .LBB20_2342; SPE-NEXT: # %bb.1:343; SPE-NEXT: efdcmpeq cr0, r5, r5344; SPE-NEXT: bclr 12, gt, 0345; SPE-NEXT: .LBB20_2:346; SPE-NEXT: mr r3, r4347; SPE-NEXT: blr348 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ord", metadata !"fpexcept.strict") #0349 %res = select i1 %cond, i32 %a, i32 %b350 ret i32 %res351}352 353define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {354; SPE-LABEL: test_f64_ueq_s:355; SPE: # %bb.0:356; SPE-NEXT: evmergelo r7, r7, r8357; SPE-NEXT: evmergelo r5, r5, r6358; SPE-NEXT: efdcmplt cr0, r5, r7359; SPE-NEXT: bc 12, gt, .LBB21_3360; SPE-NEXT: # %bb.1:361; SPE-NEXT: efdcmpgt cr0, r5, r7362; SPE-NEXT: bc 12, gt, .LBB21_3363; SPE-NEXT: # %bb.2:364; SPE-NEXT: mr r4, r3365; SPE-NEXT: .LBB21_3:366; SPE-NEXT: mr r3, r4367; SPE-NEXT: blr368 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0369 %res = select i1 %cond, i32 %a, i32 %b370 ret i32 %res371}372 373define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {374; SPE-LABEL: test_f64_ugt_s:375; SPE: # %bb.0:376; SPE-NEXT: evmergelo r7, r7, r8377; SPE-NEXT: evmergelo r5, r5, r6378; SPE-NEXT: efdcmpeq cr0, r5, r5379; SPE-NEXT: bclr 4, gt, 0380; SPE-NEXT: # %bb.1:381; SPE-NEXT: efdcmpeq cr0, r7, r7382; SPE-NEXT: bclr 4, gt, 0383; SPE-NEXT: # %bb.2:384; SPE-NEXT: efdcmpgt cr0, r5, r7385; SPE-NEXT: bclr 12, gt, 0386; SPE-NEXT: # %bb.3:387; SPE-NEXT: mr r3, r4388; SPE-NEXT: blr389 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0390 %res = select i1 %cond, i32 %a, i32 %b391 ret i32 %res392}393 394define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {395; SPE-LABEL: test_f64_uge_s:396; SPE: # %bb.0:397; SPE-NEXT: evmergelo r7, r7, r8398; SPE-NEXT: evmergelo r5, r5, r6399; SPE-NEXT: efdcmplt cr0, r5, r7400; SPE-NEXT: bc 12, gt, .LBB23_2401; SPE-NEXT: # %bb.1:402; SPE-NEXT: mr r4, r3403; SPE-NEXT: .LBB23_2:404; SPE-NEXT: mr r3, r4405; SPE-NEXT: blr406 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0407 %res = select i1 %cond, i32 %a, i32 %b408 ret i32 %res409}410 411define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {412; SPE-LABEL: test_f64_ult_s:413; SPE: # %bb.0:414; SPE-NEXT: evmergelo r7, r7, r8415; SPE-NEXT: evmergelo r5, r5, r6416; SPE-NEXT: efdcmpeq cr0, r5, r5417; SPE-NEXT: bclr 4, gt, 0418; SPE-NEXT: # %bb.1:419; SPE-NEXT: efdcmpeq cr0, r7, r7420; SPE-NEXT: bclr 4, gt, 0421; SPE-NEXT: # %bb.2:422; SPE-NEXT: efdcmplt cr0, r5, r7423; SPE-NEXT: bclr 12, gt, 0424; SPE-NEXT: # %bb.3:425; SPE-NEXT: mr r3, r4426; SPE-NEXT: blr427 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0428 %res = select i1 %cond, i32 %a, i32 %b429 ret i32 %res430}431 432define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {433; SPE-LABEL: test_f64_ule_s:434; SPE: # %bb.0:435; SPE-NEXT: evmergelo r7, r7, r8436; SPE-NEXT: evmergelo r5, r5, r6437; SPE-NEXT: efdcmpgt cr0, r5, r7438; SPE-NEXT: bc 12, gt, .LBB25_2439; SPE-NEXT: # %bb.1:440; SPE-NEXT: mr r4, r3441; SPE-NEXT: .LBB25_2:442; SPE-NEXT: mr r3, r4443; SPE-NEXT: blr444 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0445 %res = select i1 %cond, i32 %a, i32 %b446 ret i32 %res447}448 449define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {450; SPE-LABEL: test_f64_une_s:451; SPE: # %bb.0:452; SPE-NEXT: evmergelo r7, r7, r8453; SPE-NEXT: evmergelo r5, r5, r6454; SPE-NEXT: efdcmpeq cr0, r5, r7455; SPE-NEXT: bc 12, gt, .LBB26_2456; SPE-NEXT: # %bb.1:457; SPE-NEXT: mr r4, r3458; SPE-NEXT: .LBB26_2:459; SPE-NEXT: mr r3, r4460; SPE-NEXT: blr461 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0462 %res = select i1 %cond, i32 %a, i32 %b463 ret i32 %res464}465 466define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {467; SPE-LABEL: test_f64_uno_s:468; SPE: # %bb.0:469; SPE-NEXT: evmergelo r7, r7, r8470; SPE-NEXT: evmergelo r5, r5, r6471; SPE-NEXT: efdcmpeq cr0, r5, r5472; SPE-NEXT: bclr 4, gt, 0473; SPE-NEXT: # %bb.1:474; SPE-NEXT: efdcmpeq cr0, r7, r7475; SPE-NEXT: bclr 4, gt, 0476; SPE-NEXT: # %bb.2:477; SPE-NEXT: mr r3, r4478; SPE-NEXT: blr479 %cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uno", metadata !"fpexcept.strict") #0480 %res = select i1 %cond, i32 %a, i32 %b481 ret i32 %res482}483 484attributes #0 = { strictfp nounwind }485 486declare i1 @llvm.experimental.constrained.fcmps.f32(float, float, metadata, metadata)487declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)488