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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"5target triple = "powerpc64-unknown-linux-gnu"6 7define double @zerocmp1(double %a, double %y, double %z) #0 {8entry:9 %cmp = fcmp ult double %a, 0.000000e+0010 %z.y = select i1 %cmp, double %z, double %y11 ret double %z.y12 13; CHECK: @zerocmp114; CHECK-NOT: fsel15; CHECK: blr16 17; CHECK-FM: @zerocmp118; CHECK-FM: fsel 1, 1, 2, 319; CHECK-FM: blr20 21; CHECK-FM-VSX: @zerocmp122; CHECK-FM-VSX: fsel 1, 1, 2, 323; CHECK-FM-VSX: blr24}25 26define double @zerocmp2(double %a, double %y, double %z) #0 {27entry:28 %cmp = fcmp ogt double %a, 0.000000e+0029 %y.z = select i1 %cmp, double %y, double %z30 ret double %y.z31 32; CHECK: @zerocmp233; CHECK-NOT: fsel34; CHECK: blr35 36; CHECK-FM: @zerocmp237; CHECK-FM: fneg [[REG:[0-9]+]], 138; CHECK-FM: fsel 1, [[REG]], 3, 239; CHECK-FM: blr40 41; CHECK-FM-VSX: @zerocmp242; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 143; CHECK-FM-VSX: fsel 1, [[REG]], 3, 244; CHECK-FM-VSX: blr45}46 47define double @zerocmp3(double %a, double %y, double %z) #0 {48entry:49 %cmp = fcmp oeq double %a, 0.000000e+0050 %y.z = select i1 %cmp, double %y, double %z51 ret double %y.z52 53; CHECK: @zerocmp354; CHECK-NOT: fsel55; CHECK: blr56 57; CHECK-FM: @zerocmp358; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 359; CHECK-FM: fneg [[REG2:[0-9]+]], 160; CHECK-FM: fsel 1, [[REG2]], [[REG]], 361; CHECK-FM: blr62 63; CHECK-FM-VSX: @zerocmp364; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 365; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 166; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 367; CHECK-FM-VSX: blr68}69 70define double @min1(double %a, double %b) #0 {71entry:72 %cmp = fcmp ole double %a, %b73 %cond = select i1 %cmp, double %a, double %b74 ret double %cond75 76; CHECK: @min177; CHECK-NOT: fsel78; CHECK: blr79 80; CHECK-FM: @min181; CHECK-FM: fsub [[REG:[0-9]+]], 2, 182; CHECK-FM: fsel 1, [[REG]], 1, 283; CHECK-FM: blr84 85; CHECK-FM-VSX: @min186; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 187; CHECK-FM-VSX: fsel 1, [[REG]], 1, 288; CHECK-FM-VSX: blr89}90 91define double @max1(double %a, double %b) #0 {92entry:93 %cmp = fcmp oge double %a, %b94 %cond = select i1 %cmp, double %a, double %b95 ret double %cond96 97; CHECK: @max198; CHECK-NOT: fsel99; CHECK: blr100 101; CHECK-FM: @max1102; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2103; CHECK-FM: fsel 1, [[REG]], 1, 2104; CHECK-FM: blr105 106; CHECK-FM-VSX: @max1107; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2108; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2109; CHECK-FM-VSX: blr110}111 112define double @cmp1(double %a, double %b, double %y, double %z) #0 {113entry:114 %cmp = fcmp ult double %a, %b115 %z.y = select i1 %cmp, double %z, double %y116 ret double %z.y117 118; CHECK: @cmp1119; CHECK-NOT: fsel120; CHECK: blr121 122; CHECK-FM: @cmp1123; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2124; CHECK-FM: fsel 1, [[REG]], 3, 4125; CHECK-FM: blr126 127; CHECK-FM-VSX: @cmp1128; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2129; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4130; CHECK-FM-VSX: blr131}132 133define double @cmp2(double %a, double %b, double %y, double %z) #0 {134entry:135 %cmp = fcmp ogt double %a, %b136 %y.z = select i1 %cmp, double %y, double %z137 ret double %y.z138 139; CHECK: @cmp2140; CHECK-NOT: fsel141; CHECK: blr142 143; CHECK-FM: @cmp2144; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1145; CHECK-FM: fsel 1, [[REG]], 4, 3146; CHECK-FM: blr147 148; CHECK-FM-VSX: @cmp2149; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1150; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3151; CHECK-FM-VSX: blr152}153 154define double @cmp3(double %a, double %b, double %y, double %z) #0 {155entry:156 %cmp = fcmp oeq double %a, %b157 %y.z = select i1 %cmp, double %y, double %z158 ret double %y.z159 160; CHECK: @cmp3161; CHECK-NOT: fsel162; CHECK: blr163 164; CHECK-FM: @cmp3165; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2166; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4167; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]168; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4169; CHECK-FM: blr170 171; CHECK-FM-VSX: @cmp3172; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2173; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4174; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]175; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4176; CHECK-FM-VSX: blr177}178 179attributes #0 = { nounwind readnone }180 181