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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr6 | FileCheck -check-prefix=CHECK-PWR6 %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck -check-prefix=CHECK-A2 %s4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s5target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"6target triple = "powerpc64-unknown-linux-gnu"7 8define float @foo(i32 %a) nounwind {9entry:10 %x = sitofp i32 %a to float11 ret float %x12 13; CHECK: @foo14; CHECK: extsw [[REG:[0-9]+]], 315; CHECK: std [[REG]],16; CHECK: lfd [[REG2:[0-9]+]],17; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]]18; CHECK: frsp 1, [[REG3]]19; CHECK: blr20 21; CHECK-PWR6: @foo22; CHECK-PWR6: stw 3,23; CHECK-PWR6: lfiwax [[REG:[0-9]+]],24; CHECK-PWR6: fcfid [[REG2:[0-9]+]], [[REG]]25; CHECK-PWR6: frsp 1, [[REG2]]26; CHECK-PWR6: blr27 28; CHECK-A2: @foo29; CHECK-A2: stw 3,30; CHECK-A2: lfiwax [[REG:[0-9]+]],31; CHECK-A2: fcfids 1, [[REG]]32; CHECK-A2: blr33 34; CHECK-VSX: @foo35; CHECK-VSX: stw 3,36; CHECK-VSX: lfiwax [[REG:[0-9]+]],37; CHECK-VSX: fcfids 1, [[REG]]38; CHECK-VSX: blr39}40 41define double @goo(i32 %a) nounwind {42entry:43 %x = sitofp i32 %a to double44 ret double %x45 46; CHECK: @goo47; CHECK: extsw [[REG:[0-9]+]], 348; CHECK: std [[REG]],49; CHECK: lfd [[REG2:[0-9]+]],50; CHECK: fcfid 1, [[REG2]]51; CHECK: blr52 53; CHECK-PWR6: @goo54; CHECK-PWR6: stw 3,55; CHECK-PWR6: lfiwax [[REG:[0-9]+]],56; CHECK-PWR6: fcfid 1, [[REG]]57; CHECK-PWR6: blr58 59; CHECK-A2: @goo60; CHECK-A2: stw 3,61; CHECK-A2: lfiwax [[REG:[0-9]+]],62; CHECK-A2: fcfid 1, [[REG]]63; CHECK-A2: blr64 65; CHECK-VSX: @goo66; CHECK-VSX: stw 3,67; CHECK-VSX: lfiwax [[REG:[0-9]+]],68; CHECK-VSX: xscvsxddp 1, [[REG]]69; CHECK-VSX: blr70}71 72define float @foou(i32 %a) nounwind {73entry:74 %x = uitofp i32 %a to float75 ret float %x76 77; CHECK-A2: @foou78; CHECK-A2: stw 3,79; CHECK-A2: lfiwzx [[REG:[0-9]+]],80; CHECK-A2: fcfidus 1, [[REG]]81; CHECK-A2: blr82 83; CHECK-VSX: @foou84; CHECK-VSX: stw 3,85; CHECK-VSX: lfiwzx [[REG:[0-9]+]],86; CHECK-VSX: fcfidus 1, [[REG]]87; CHECK-VSX: blr88}89 90define double @goou(i32 %a) nounwind {91entry:92 %x = uitofp i32 %a to double93 ret double %x94 95; CHECK-A2: @goou96; CHECK-A2: stw 3,97; CHECK-A2: lfiwzx [[REG:[0-9]+]],98; CHECK-A2: fcfidu 1, [[REG]]99; CHECK-A2: blr100 101; CHECK-VSX: @goou102; CHECK-VSX: stw 3,103; CHECK-VSX: lfiwzx [[REG:[0-9]+]],104; CHECK-VSX: xscvuxddp 1, [[REG]]105; CHECK-VSX: blr106}107 108