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1; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \2; RUN: -mcpu=a2 | FileCheck %s3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \4; RUN: -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s5; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr9 -mattr=-direct-move | FileCheck %s -check-prefix=CHECK-P97target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"8target triple = "powerpc64-unknown-linux-gnu"9 10define float @foo(i64 %a) nounwind {11entry:12 %x = sitofp i64 %a to float13 ret float %x14 15; CHECK: @foo16; CHECK: std 3,17; CHECK: lfd [[REG:[0-9]+]],18; CHECK: fcfids 1, [[REG]]19; CHECK: blr20 21; CHECK-VSX: @foo22; CHECK-VSX: std 3,23; CHECK-VSX: lfd [[REG:[0-9]+]],24; CHECK-VSX: fcfids 1, [[REG]]25; CHECK-VSX: blr26 27; CHECK-P9: @foo28; CHECK-P9: std 3,29; CHECK-P9: lfd [[REG:[0-9]+]],30; CHECK-P9: xscvsxdsp 1, [[REG]]31; CHECK-P9: blr32}33 34define double @goo(i64 %a) nounwind {35entry:36 %x = sitofp i64 %a to double37 ret double %x38 39; CHECK: @goo40; CHECK: std 3,41; CHECK: lfd [[REG:[0-9]+]],42; CHECK: fcfid 1, [[REG]]43; CHECK: blr44 45; CHECK-VSX: @goo46; CHECK-VSX: std 3,47; CHECK-VSX: lfd [[REG:[0-9]+]],48; CHECK-VSX: xscvsxddp 1, [[REG]]49; CHECK-VSX: blr50 51; CHECK-P9: @goo52; CHECK-P9: std 3,53; CHECK-P9: lfd [[REG:[0-9]+]],54; CHECK-P9: xscvsxddp 1, [[REG]]55; CHECK-P9: blr56}57 58define float @foou(i64 %a) nounwind {59entry:60 %x = uitofp i64 %a to float61 ret float %x62 63; CHECK: @foou64; CHECK: std 3,65; CHECK: lfd [[REG:[0-9]+]],66; CHECK: fcfidus 1, [[REG]]67; CHECK: blr68 69; CHECK-VSX: @foou70; CHECK-VSX: std 3,71; CHECK-VSX: lfd [[REG:[0-9]+]],72; CHECK-VSX: fcfidus 1, [[REG]]73; CHECK-VSX: blr74 75; CHECK-P9: @foou76; CHECK-P9: std 3,77; CHECK-P9: lfd [[REG:[0-9]+]],78; CHECK-P9: xscvuxdsp 1, [[REG]]79; CHECK-P9: blr80}81 82define double @goou(i64 %a) nounwind {83entry:84 %x = uitofp i64 %a to double85 ret double %x86 87; CHECK: @goou88; CHECK: std 3,89; CHECK: lfd [[REG:[0-9]+]],90; CHECK: fcfidu 1, [[REG]]91; CHECK: blr92 93; CHECK-VSX: @goou94; CHECK-VSX: std 3,95; CHECK-VSX: lfd [[REG:[0-9]+]],96; CHECK-VSX: xscvuxddp 1, [[REG]]97; CHECK-VSX: blr98 99; CHECK-P9: @goou100; CHECK-P9: std 3,101; CHECK-P9: lfd [[REG:[0-9]+]],102; CHECK-P9: xscvuxddp 1, [[REG]]103; CHECK-P9: blr104}105 106