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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s3; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"5target triple = "powerpc64-unknown-linux-gnu"6 7define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {8; CHECK-LABEL: test:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: slwi 5, 6, 1611; CHECK-NEXT: extsh 6, 612; CHECK-NEXT: cmpwi 5, -113; CHECK-NEXT: add 5, 6, 314; CHECK-NEXT: clrlwi 6, 6, 1715; CHECK-NEXT: sub 6, 3, 616; CHECK-NEXT: sub 3, 4, 317; CHECK-NEXT: iselgt 5, 5, 618; CHECK-NEXT: extsh 5, 519; CHECK-NEXT: add 3, 3, 520; CHECK-NEXT: blr21;22; CHECK-NO-ISEL-LABEL: test:23; CHECK-NO-ISEL: # %bb.0: # %entry24; CHECK-NO-ISEL-NEXT: slwi 7, 6, 1625; CHECK-NO-ISEL-NEXT: extsh 5, 626; CHECK-NO-ISEL-NEXT: cmpwi 7, -127; CHECK-NO-ISEL-NEXT: ble 0, .LBB0_228; CHECK-NO-ISEL-NEXT: # %bb.1: # %cond.false29; CHECK-NO-ISEL-NEXT: add 5, 5, 330; CHECK-NO-ISEL-NEXT: b .LBB0_331; CHECK-NO-ISEL-NEXT: .LBB0_2: # %cond.true32; CHECK-NO-ISEL-NEXT: clrlwi 5, 5, 1733; CHECK-NO-ISEL-NEXT: sub 5, 3, 534; CHECK-NO-ISEL-NEXT: .LBB0_3: # %cond.end35; CHECK-NO-ISEL-NEXT: extsh 5, 536; CHECK-NO-ISEL-NEXT: sub 3, 4, 337; CHECK-NO-ISEL-NEXT: add 3, 3, 538; CHECK-NO-ISEL-NEXT: blr39entry:40 %sext82 = shl i32 %d, 1641 %conv29 = ashr exact i32 %sext82, 1642 %cmp = icmp slt i32 %sext82, 043 br i1 %cmp, label %cond.true, label %cond.false44 45cond.true: ; preds = %sw.epilog46 %and33 = and i32 %conv29, 3276747 %sub34 = sub nsw i32 %a, %and3348 br label %cond.end49 50cond.false: ; preds = %sw.epilog51 %add37 = add nsw i32 %conv29, %a52 br label %cond.end53 54 55cond.end: ; preds = %cond.false, %cond.true56 %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]57 %sext83 = shl i32 %cond, 1658 %conv39 = ashr exact i32 %sext83, 1659 %add41 = sub i32 %b, %a60 %sub43 = add i32 %add41, %conv3961 ret i32 %sub4362}63 64