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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=powerpc64-- -mcpu=pwr5 -verify-machineinstrs < %s | \3; RUN: FileCheck %s4define void @bs(ptr %p) {5; CHECK-LABEL: bs:6; CHECK: # %bb.0:7; CHECK-NEXT: li 4, 48; CHECK-NEXT: lwbrx 5, 0, 39; CHECK-NEXT: lwbrx 4, 3, 410; CHECK-NEXT: rldimi 5, 4, 32, 011; CHECK-NEXT: std 5, 0(3)12; CHECK-NEXT: blr13 %x = load i64, ptr %p, align 814 %b = call i64 @llvm.bswap.i64(i64 %x)15 store i64 %b, ptr %p, align 816 ret void17}18 19define i64 @volatile_ld(ptr %p) {20; CHECK-LABEL: volatile_ld:21; CHECK: # %bb.0:22; CHECK-NEXT: ld 4, 0(3)23; CHECK-NEXT: rotldi 5, 4, 1624; CHECK-NEXT: rotldi 3, 4, 825; CHECK-NEXT: rldimi 3, 5, 8, 4826; CHECK-NEXT: rotldi 5, 4, 2427; CHECK-NEXT: rldimi 3, 5, 16, 4028; CHECK-NEXT: rotldi 5, 4, 3229; CHECK-NEXT: rldimi 3, 5, 24, 3230; CHECK-NEXT: rotldi 5, 4, 4831; CHECK-NEXT: rldimi 3, 5, 40, 1632; CHECK-NEXT: rotldi 5, 4, 5633; CHECK-NEXT: rldimi 3, 5, 48, 834; CHECK-NEXT: rldimi 3, 4, 56, 035; CHECK-NEXT: blr36 %x = load volatile i64, ptr %p, align 837 %b = call i64 @llvm.bswap.i64(i64 %x)38 ret i64 %b39}40 41define i64 @misaligned_ld(ptr %p) {42; CHECK-LABEL: misaligned_ld:43; CHECK: # %bb.0:44; CHECK-NEXT: li 4, 445; CHECK-NEXT: lwbrx 4, 3, 446; CHECK-NEXT: lwbrx 3, 0, 347; CHECK-NEXT: rldimi 3, 4, 32, 048; CHECK-NEXT: blr49 %x = load i64, ptr %p, align 150 %b = call i64 @llvm.bswap.i64(i64 %x)51 ret i64 %b52}53 54declare i64 @llvm.bswap.i64(i64) #255