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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \4; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10LE5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \8; RUN: < %s | FileCheck %s --check-prefix=CHECK-P10BE9 10; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \11; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \12; RUN: < %s | FileCheck %s --check-prefix=CHECK-P913 14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \15; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \16; RUN: < %s | FileCheck %s --check-prefix=CHECK-P917 18define <8 x i16> @test1(ptr %a) {19; CHECK-P10LE-LABEL: test1:20; CHECK-P10LE: # %bb.0: # %entry21; CHECK-P10LE-NEXT: lxvrhx v2, 0, r322; CHECK-P10LE-NEXT: blr23;24; CHECK-P10BE-LABEL: test1:25; CHECK-P10BE: # %bb.0: # %entry26; CHECK-P10BE-NEXT: lxsihzx v2, 0, r327; CHECK-P10BE-NEXT: vsplth v2, v2, 328; CHECK-P10BE-NEXT: blr29;30; CHECK-P9-LABEL: test1:31; CHECK-P9: # %bb.0: # %entry32; CHECK-P9-NEXT: lxsihzx v2, 0, r333; CHECK-P9-NEXT: vsplth v2, v2, 334; CHECK-P9-NEXT: blr35entry:36 %0 = load i16, ptr %a, align 237 %vecinit = insertelement <8 x i16> undef, i16 %0, i32 038 ret <8 x i16> %vecinit39}40 41define <16 x i8> @test2(ptr %a) {42; CHECK-P10LE-LABEL: test2:43; CHECK-P10LE: # %bb.0: # %entry44; CHECK-P10LE-NEXT: lxvrbx v2, 0, r345; CHECK-P10LE-NEXT: blr46;47; CHECK-P10BE-LABEL: test2:48; CHECK-P10BE: # %bb.0: # %entry49; CHECK-P10BE-NEXT: lxsibzx v2, 0, r350; CHECK-P10BE-NEXT: vspltb v2, v2, 751; CHECK-P10BE-NEXT: blr52;53; CHECK-P9-LABEL: test2:54; CHECK-P9: # %bb.0: # %entry55; CHECK-P9-NEXT: lxsibzx v2, 0, r356; CHECK-P9-NEXT: vspltb v2, v2, 757; CHECK-P9-NEXT: blr58entry:59 %0 = load i8, ptr %a, align 160 %vecins = insertelement <16 x i8> undef, i8 %0, i32 061 ret <16 x i8> %vecins62}63 64