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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \3; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s4; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -disable-lsr \5; RUN: -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr10 < %s | FileCheck %s \6; RUN: --check-prefix=CHECK-BE7 8; This test checks the PPCLoopInstrFormPrep pass supports the lxvp and stxvp9; intrinsics so we generate more dq-form instructions instead of x-forms.10 11%_elem_type_of_x = type <{ double }>12%_elem_type_of_y = type <{ double }>13 14define void @foo(ptr %.n, ptr %.x, ptr %.y, ptr %.sum) {15; CHECK-LABEL: foo:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: ld r5, 0(r3)18; CHECK-NEXT: cmpdi r5, 019; CHECK-NEXT: blelr cr020; CHECK-NEXT: # %bb.1: # %_loop_1_do_.lr.ph21; CHECK-NEXT: addi r3, r4, 122; CHECK-NEXT: addi r4, r5, -123; CHECK-NEXT: lxv vs0, 0(r6)24; CHECK-NEXT: rldicl r4, r4, 60, 425; CHECK-NEXT: addi r4, r4, 126; CHECK-NEXT: mtctr r427; CHECK-NEXT: .p2align 528; CHECK-NEXT: .LBB0_2: # %_loop_1_do_29; CHECK-NEXT: #30; CHECK-NEXT: lxvp vsp34, 0(r3)31; CHECK-NEXT: lxvp vsp36, 32(r3)32; CHECK-NEXT: addi r3, r3, 12833; CHECK-NEXT: xvadddp vs0, vs0, vs3534; CHECK-NEXT: xvadddp vs0, vs0, vs3435; CHECK-NEXT: xvadddp vs0, vs0, vs3736; CHECK-NEXT: xvadddp vs0, vs0, vs3637; CHECK-NEXT: bdnz .LBB0_238; CHECK-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge39; CHECK-NEXT: stxv vs0, 0(r6)40; CHECK-NEXT: blr41;42; CHECK-BE-LABEL: foo:43; CHECK-BE: # %bb.0: # %entry44; CHECK-BE-NEXT: ld r5, 0(r3)45; CHECK-BE-NEXT: cmpdi r5, 046; CHECK-BE-NEXT: blelr cr047; CHECK-BE-NEXT: # %bb.1: # %_loop_1_do_.lr.ph48; CHECK-BE-NEXT: addi r3, r4, 149; CHECK-BE-NEXT: addi r4, r5, -150; CHECK-BE-NEXT: lxv vs0, 0(r6)51; CHECK-BE-NEXT: rldicl r4, r4, 60, 452; CHECK-BE-NEXT: addi r4, r4, 153; CHECK-BE-NEXT: mtctr r454; CHECK-BE-NEXT: .p2align 555; CHECK-BE-NEXT: .LBB0_2: # %_loop_1_do_56; CHECK-BE-NEXT: #57; CHECK-BE-NEXT: lxvp vsp34, 0(r3)58; CHECK-BE-NEXT: lxvp vsp36, 32(r3)59; CHECK-BE-NEXT: addi r3, r3, 12860; CHECK-BE-NEXT: xvadddp vs0, vs0, vs3461; CHECK-BE-NEXT: xvadddp vs0, vs0, vs3562; CHECK-BE-NEXT: xvadddp vs0, vs0, vs3663; CHECK-BE-NEXT: xvadddp vs0, vs0, vs3764; CHECK-BE-NEXT: bdnz .LBB0_265; CHECK-BE-NEXT: # %bb.3: # %_loop_1_loopHeader_._return_bb_crit_edge66; CHECK-BE-NEXT: stxv vs0, 0(r6)67; CHECK-BE-NEXT: blr68entry:69 %_val_n_2 = load i64, ptr %.n, align 870 %_grt_tmp7 = icmp slt i64 %_val_n_2, 171 br i1 %_grt_tmp7, label %_return_bb, label %_loop_1_do_.lr.ph72 73_loop_1_do_.lr.ph: ; preds = %entry74 %x_rvo_based_addr_5 = getelementptr inbounds [0 x %_elem_type_of_x], ptr %.x, i64 0, i64 -175 %.sum.promoted = load <2 x double>, ptr %.sum, align 1676 br label %_loop_1_do_77 78_loop_1_do_: ; preds = %_loop_1_do_.lr.ph, %_loop_1_do_79 %_val_sum_9 = phi <2 x double> [ %.sum.promoted, %_loop_1_do_.lr.ph ], [ %_add_tmp49, %_loop_1_do_ ]80 %i.08 = phi i64 [ 1, %_loop_1_do_.lr.ph ], [ %_loop_1_update_loop_ix, %_loop_1_do_ ]81 %x_ix_dim_0_6 = getelementptr %_elem_type_of_x, ptr %x_rvo_based_addr_5, i64 %i.0882 %0 = getelementptr i8, ptr %x_ix_dim_0_6, i64 183 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)84 %2 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %1)85 %.fca.0.extract1 = extractvalue { <16 x i8>, <16 x i8> } %2, 086 %.fca.1.extract2 = extractvalue { <16 x i8>, <16 x i8> } %2, 187 %3 = getelementptr i8, ptr %x_ix_dim_0_6, i64 3388 %4 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %3)89 %5 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1> %4)90 %.fca.0.extract = extractvalue { <16 x i8>, <16 x i8> } %5, 091 %.fca.1.extract = extractvalue { <16 x i8>, <16 x i8> } %5, 192 %6 = bitcast <16 x i8> %.fca.0.extract1 to <2 x double>93 %_add_tmp23 = fadd contract <2 x double> %_val_sum_9, %694 %7 = bitcast <16 x i8> %.fca.1.extract2 to <2 x double>95 %_add_tmp32 = fadd contract <2 x double> %_add_tmp23, %796 %8 = bitcast <16 x i8> %.fca.0.extract to <2 x double>97 %_add_tmp40 = fadd contract <2 x double> %_add_tmp32, %898 %9 = bitcast <16 x i8> %.fca.1.extract to <2 x double>99 %_add_tmp49 = fadd contract <2 x double> %_add_tmp40, %9100 %_loop_1_update_loop_ix = add nuw nsw i64 %i.08, 16101 %_grt_tmp = icmp sgt i64 %_loop_1_update_loop_ix, %_val_n_2102 br i1 %_grt_tmp, label %_loop_1_loopHeader_._return_bb_crit_edge, label %_loop_1_do_103 104_loop_1_loopHeader_._return_bb_crit_edge: ; preds = %_loop_1_do_105 store <2 x double> %_add_tmp49, ptr %.sum, align 16106 br label %_return_bb107 108_return_bb: ; preds = %_loop_1_loopHeader_._return_bb_crit_edge, %entry109 ret void110}111 112declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)113declare { <16 x i8>, <16 x i8> } @llvm.ppc.vsx.disassemble.pair(<256 x i1>)114