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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \2; RUN: -code-model=small < %s | FileCheck %s --check-prefix=SMALL3 4; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \5; RUN: -code-model=large < %s | FileCheck %s --check-prefix=LARGE6 7@a = common global i32 08 9define zeroext i32 @test_load() {10entry:11 %0 = load i32, ptr @a12 ret i32 %013}14 15; SMALL-LABEL: .test_load:{{$}}16; SMALL: ld [[REG1:[0-9]+]], L..C0(2)17; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])18; SMALL: blr19 20; LARGE-LABEL: .test_load:{{$}}21; LARGE: addis [[REG1:[0-9]+]], L..C0@u(2)22; LARGE: ld [[REG2:[0-9]+]], L..C0@l([[REG1]])23; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])24; LARGE: blr25 26@b = common global i32 027 28define void @test_store(i32 zeroext %0) {29 store i32 %0, ptr @b30 ret void31}32 33; SMALL-LABEL: .test_store:{{$}}34; SMALL: ld [[REG1:[0-9]+]], L..C1(2)35; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])36; SMALL: blr37 38; LARGE-LABEL: .test_store:{{$}}39; LARGE: addis [[REG1:[0-9]+]], L..C1@u(2)40; LARGE: ld [[REG2:[0-9]+]], L..C1@l([[REG1]])41; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])42; LARGE: blr43 44; SMALL: .tc a[TC],a45; SMALL: .tc b[TC],b46 47; LARGE: .tc a[TE],a48; LARGE: .tc b[TE],b49