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1; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr7 < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-PWR2; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 < %s | FileCheck %s -check-prefix=FIXPOINT3target datalayout = "E-m:e-i64:64-n32:64"4target triple = "powerpc64-unknown-linux-gnu"5 6; Verify that the first two adds are independent regardless of how the inputs are7; commuted. The destination registers are used as source registers for the third add.8 9define float @reassociate_adds1(float %x0, float %x1, float %x2, float %x3) {10; CHECK-LABEL: reassociate_adds1:11; CHECK: # %bb.0:12; CHECK: fadds [[REG0:[0-9]+]], 1, 213; CHECK: fadds [[REG1:[0-9]+]], 3, 414; CHECK: fadds 1, [[REG0]], [[REG1]]15; CHECK-NEXT: blr16 17 %t0 = fadd reassoc nsz float %x0, %x118 %t1 = fadd reassoc nsz float %t0, %x219 %t2 = fadd reassoc nsz float %t1, %x320 ret float %t221}22 23define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {24; CHECK-LABEL: reassociate_adds2:25; CHECK: # %bb.0:26; CHECK: fadds [[REG0:[0-9]+]], 1, 227; CHECK: fadds [[REG1:[0-9]+]], 3, 428; CHECK: fadds 1, [[REG1]], [[REG0]]29; CHECK-NEXT: blr30 31 %t0 = fadd reassoc nsz float %x0, %x132 %t1 = fadd reassoc nsz float %x2, %t033 %t2 = fadd reassoc nsz float %t1, %x334 ret float %t235}36 37define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {38; CHECK-LABEL: reassociate_adds3:39; CHECK: # %bb.0:40; CHECK: fadds [[REG0:[0-9]+]], 1, 241; CHECK: fadds [[REG1:[0-9]+]], 4, 342; CHECK: fadds 1, [[REG1]], [[REG0]]43; CHECK-NEXT: blr44 45 %t0 = fadd reassoc nsz float %x0, %x146 %t1 = fadd reassoc nsz float %t0, %x247 %t2 = fadd reassoc nsz float %x3, %t148 ret float %t249}50 51define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {52; CHECK-LABEL: reassociate_adds4:53; CHECK: # %bb.0:54; CHECK: fadds [[REG0:[0-9]+]], 1, 255; CHECK: fadds [[REG1:[0-9]+]], 4, 356; CHECK: fadds 1, [[REG1]], [[REG0]]57; CHECK-NEXT: blr58 59 %t0 = fadd reassoc nsz float %x0, %x160 %t1 = fadd reassoc nsz float %x2, %t061 %t2 = fadd reassoc nsz float %x3, %t162 ret float %t263}64 65; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not66; produced because that would cost more compile time.67 68define float @reassociate_adds5(float %x0, float %x1, float %x2, float %x3, float %x4, float %x5, float %x6, float %x7) {69; CHECK-LABEL: reassociate_adds5:70; CHECK: # %bb.0:71; CHECK-DAG: fadds [[REG12:[0-9]+]], 5, 672; CHECK-DAG: fadds [[REG0:[0-9]+]], 1, 273; CHECK-DAG: fadds [[REG11:[0-9]+]], 3, 474; CHECK-DAG: fadds [[REG13:[0-9]+]], [[REG12]], 775; CHECK-DAG: fadds [[REG1:[0-9]+]], [[REG0]], [[REG11]]76; CHECK-DAG: fadds [[REG2:[0-9]+]], [[REG1]], [[REG13]]77; CHECK: fadds 1, [[REG2]], 878; CHECK-NEXT: blr79 80 %t0 = fadd reassoc nsz float %x0, %x181 %t1 = fadd reassoc nsz float %t0, %x282 %t2 = fadd reassoc nsz float %t1, %x383 %t3 = fadd reassoc nsz float %t2, %x484 %t4 = fadd reassoc nsz float %t3, %x585 %t5 = fadd reassoc nsz float %t4, %x686 %t6 = fadd reassoc nsz float %t5, %x787 ret float %t688}89 90; Verify that we reassociate vector instructions too.91 92define <4 x float> @vector_reassociate_adds1(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {93; CHECK-LABEL: vector_reassociate_adds1:94; CHECK: # %bb.0:95; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 3596; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 3797; CHECK-PWR: xvaddsp 34, [[REG0]], [[REG1]]98; CHECK-NEXT: blr99 100 %t0 = fadd reassoc nsz <4 x float> %x0, %x1101 %t1 = fadd reassoc nsz <4 x float> %t0, %x2102 %t2 = fadd reassoc nsz <4 x float> %t1, %x3103 ret <4 x float> %t2104}105 106define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {107; CHECK-LABEL: vector_reassociate_adds2:108; CHECK: # %bb.0:109; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35110; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 36, 37111; CHECK-PWR: xvaddsp 34, [[REG1]], [[REG0]]112; CHECK-NEXT: blr113 114 %t0 = fadd reassoc nsz <4 x float> %x0, %x1115 %t1 = fadd reassoc nsz <4 x float> %x2, %t0116 %t2 = fadd reassoc nsz <4 x float> %t1, %x3117 ret <4 x float> %t2118}119 120define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {121; CHECK-LABEL: vector_reassociate_adds3:122; CHECK: # %bb.0:123; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35124; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 37, 36125; CHECK-PWR: xvaddsp 34, [[REG1]], [[REG0]]126; CHECK-NEXT: blr127 128 %t0 = fadd reassoc nsz <4 x float> %x0, %x1129 %t1 = fadd reassoc nsz <4 x float> %t0, %x2130 %t2 = fadd reassoc nsz <4 x float> %x3, %t1131 ret <4 x float> %t2132}133 134define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {135; CHECK-LABEL: vector_reassociate_adds4:136; CHECK: # %bb.0:137; CHECK-PWR: xvaddsp [[REG0:[0-9]+]], 34, 35138; CHECK-PWR: xvaddsp [[REG1:[0-9]+]], 37, 36139; CHECK-PWR: xvaddsp 34, [[REG1]], [[REG0]]140; CHECK-NEXT: blr141 142 %t0 = fadd reassoc nsz <4 x float> %x0, %x1143 %t1 = fadd reassoc nsz <4 x float> %x2, %t0144 %t2 = fadd reassoc nsz <4 x float> %x3, %t1145 ret <4 x float> %t2146}147 148define float @reassociate_adds6(float %x0, float %x1, float %x2, float %x3) {149 %t0 = fdiv float %x0, %x1150 %t1 = fadd float %x2, %t0151 %t2 = fadd float %x3, %t1152 ret float %t2153}154 155define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {156 %t0 = fdiv float %x0, %x1157 %t1 = fmul float %x2, %t0158 %t2 = fmul float %x3, %t1159 ret float %t2160}161 162define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {163 %t0 = fdiv double %x0, %x1164 %t1 = fadd double %x2, %t0165 %t2 = fadd double %x3, %t1166 ret double %t2167}168 169define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {170 %t0 = fdiv double %x0, %x1171 %t1 = fmul double %x2, %t0172 %t2 = fmul double %x3, %t1173 ret double %t2174}175 176define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {177; FIXPOINT-LABEL: reassociate_mullw:178; FIXPOINT: # %bb.0:179; FIXPOINT: mullw [[REG0:[0-9]+]], 3, 4180; FIXPOINT: mullw [[REG1:[0-9]+]], 5, 6181; FIXPOINT: mullw 3, [[REG0]], [[REG1]]182; FIXPOINT-NEXT: blr183 184 %t0 = mul i32 %x0, %x1185 %t1 = mul i32 %t0, %x2186 %t2 = mul i32 %t1, %x3187 ret i32 %t2188}189 190define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {191; FIXPOINT-LABEL: reassociate_mulld:192; FIXPOINT: # %bb.0:193; FIXPOINT: mulld [[REG0:[0-9]+]], 3, 4194; FIXPOINT: mulld [[REG1:[0-9]+]], 5, 6195; FIXPOINT: mulld 3, [[REG0]], [[REG1]]196; FIXPOINT-NEXT: blr197 198 %t0 = mul i64 %x0, %x1199 %t1 = mul i64 %t0, %x2200 %t2 = mul i64 %t1, %x3201 ret i64 %t2202}203 204define double @reassociate_mamaa_double(double %0, double %1, double %2, double %3, double %4, double %5) {205; CHECK-LABEL: reassociate_mamaa_double:206; CHECK: # %bb.0:207; CHECK-PWR-DAG: xsmaddadp 1, 6, 5208; CHECK-PWR-DAG: xsmaddadp 2, 4, 3209; CHECK-PWR: xsadddp 1, 2, 1210; CHECK-NEXT: blr211 %7 = fmul contract reassoc nsz double %3, %2212 %8 = fmul contract reassoc nsz double %5, %4213 %9 = fadd contract reassoc nsz double %1, %0214 %10 = fadd contract reassoc nsz double %9, %7215 %11 = fadd contract reassoc nsz double %10, %8216 ret double %11217}218 219define float @reassociate_mamaa_float(float %0, float %1, float %2, float %3, float %4, float %5) {220; CHECK-LABEL: reassociate_mamaa_float:221; CHECK: # %bb.0:222; CHECK-DAG: fmadds [[REG0:[0-9]+]], 4, 3, 2223; CHECK-DAG: fmadds [[REG1:[0-9]+]], 6, 5, 1224; CHECK: fadds 1, [[REG0]], [[REG1]]225; CHECK-NEXT: blr226 %7 = fmul contract reassoc nsz float %3, %2227 %8 = fmul contract reassoc nsz float %5, %4228 %9 = fadd contract reassoc nsz float %1, %0229 %10 = fadd contract reassoc nsz float %9, %7230 %11 = fadd contract reassoc nsz float %10, %8231 ret float %11232}233 234define <4 x float> @reassociate_mamaa_vec(<4 x float> %0, <4 x float> %1, <4 x float> %2, <4 x float> %3, <4 x float> %4, <4 x float> %5) {235; CHECK-LABEL: reassociate_mamaa_vec:236; CHECK: # %bb.0:237; CHECK-PWR-DAG: xvmaddasp [[REG0:[0-9]+]], 39, 38238; CHECK-PWR-DAG: xvmaddasp [[REG1:[0-9]+]], 37, 36239; CHECK-PWR: xvaddsp 34, [[REG1]], [[REG0]]240; CHECK-NEXT: blr241 %7 = fmul contract reassoc nsz <4 x float> %3, %2242 %8 = fmul contract reassoc nsz <4 x float> %5, %4243 %9 = fadd contract reassoc nsz <4 x float> %1, %0244 %10 = fadd contract reassoc nsz <4 x float> %9, %7245 %11 = fadd contract reassoc nsz <4 x float> %10, %8246 ret <4 x float> %11247}248 249define double @reassociate_mamama_double(double %0, double %1, double %2, double %3, double %4, double %5, double %6, double %7, double %8) {250; CHECK-LABEL: reassociate_mamama_double:251; CHECK: # %bb.0:252; CHECK-PWR: xsmaddadp 7, 2, 1253; CHECK-PWR-DAG: xsmuldp [[REG0:[0-9]+]], 4, 3254; CHECK-PWR-DAG: xsmaddadp 7, 6, 5255; CHECK-PWR-DAG: xsmaddadp [[REG0]], 9, 8256; CHECK-PWR: xsadddp 1, 7, [[REG0]]257; CHECK-NEXT: blr258 %10 = fmul contract reassoc nsz double %1, %0259 %11 = fmul contract reassoc nsz double %3, %2260 %12 = fmul contract reassoc nsz double %5, %4261 %13 = fmul contract reassoc nsz double %8, %7262 %14 = fadd contract reassoc nsz double %11, %10263 %15 = fadd contract reassoc nsz double %14, %6264 %16 = fadd contract reassoc nsz double %15, %12265 %17 = fadd contract reassoc nsz double %16, %13266 ret double %17267}268 269define dso_local float @reassociate_mamama_8(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8,270 float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16) {271; CHECK-LABEL: reassociate_mamama_8:272; CHECK: # %bb.0:273; CHECK-DAG: fmadds [[REG0:[0-9]+]], 3, 2, 1274; CHECK-DAG: fmuls [[REG1:[0-9]+]], 5, 4275; CHECK-DAG: fmadds [[REG2:[0-9]+]], 7, 6, [[REG0]]276; CHECK-DAG: fmadds [[REG3:[0-9]+]], 9, 8, [[REG1]]277;278; CHECK-DAG: fmadds [[REG4:[0-9]+]], 13, 12, [[REG3]]279; CHECK-DAG: fmadds [[REG5:[0-9]+]], 11, 10, [[REG2]]280;281; CHECK-DAG: fmadds [[REG6:[0-9]+]], 31, 0, [[REG4]]282; CHECK-DAG: fmadds [[REG7:[0-9]+]], 29, 30, [[REG5]]283; CHECK: fadds 1, [[REG7]], [[REG6]]284; CHECK-NEXT: blr285 %18 = fmul contract reassoc nsz float %2, %1286 %19 = fadd contract reassoc nsz float %18, %0287 %20 = fmul contract reassoc nsz float %4, %3288 %21 = fadd contract reassoc nsz float %19, %20289 %22 = fmul contract reassoc nsz float %6, %5290 %23 = fadd contract reassoc nsz float %21, %22291 %24 = fmul contract reassoc nsz float %8, %7292 %25 = fadd contract reassoc nsz float %23, %24293 %26 = fmul contract reassoc nsz float %10, %9294 %27 = fadd contract reassoc nsz float %25, %26295 %28 = fmul contract reassoc nsz float %12, %11296 %29 = fadd contract reassoc nsz float %27, %28297 %30 = fmul contract reassoc nsz float %14, %13298 %31 = fadd contract reassoc nsz float %29, %30299 %32 = fmul contract reassoc nsz float %16, %15300 %33 = fadd contract reassoc nsz float %31, %32301 ret float %33302}303 304