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1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \2; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=MEDIUM %s3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=medium \4; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-VSX %s5; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \6; RUN: -fast-isel=false -mattr=-vsx <%s | FileCheck -check-prefix=LARGE %s7; RUN: llc -verify-machineinstrs -mcpu=pwr7 -O0 -code-model=large \8; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-VSX %s9; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=medium \10; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=MEDIUM-P9 %s11; RUN: llc -verify-machineinstrs -mcpu=pwr9 -O0 -code-model=large \12; RUN: -fast-isel=false -mattr=+vsx <%s | FileCheck -check-prefix=LARGE-P9 %s13 14; Test correct code generation for medium and large code model15; for loading a value from the constant pool (TOC-relative).16 17target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"18target triple = "powerpc64-unknown-linux-gnu"19 20define double @test_double_const() nounwind {21entry:22 ret double 0x3F4FD4920B498CF023}24 25; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:26; MEDIUM: .quad 0x3f4fd4920b498cf027; MEDIUM-LABEL: test_double_const:28; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha29; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l30; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])31 32; MEDIUM-VSX: [[VAR:[a-z0-9A-Z_.]+]]:33; MEDIUM-VSX: .quad 0x3f4fd4920b498cf034; MEDIUM-VSX-LABEL: test_double_const:35; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha36; MEDIUM-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})37 38; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:39; LARGE: .quad 0x3f4fd4920b498cf040; LARGE-LABEL: test_double_const:41; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha42; LARGE: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])43; LARGE: lfd {{[0-9]+}}, 0([[REG2]])44 45; LARGE-VSX: [[VAR:[a-z0-9A-Z_.]+]]:46; LARGE-VSX: .quad 0x3f4fd4920b498cf047; LARGE-VSX-LABEL: test_double_const:48; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha49; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])50; LARGE-VSX: lfd {{[0-9]+}}, 0({{[0-9]+}})51 52; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:53; MEDIUM-P9: .quad 0x3f4fd4920b498cf054; MEDIUM-P9-LABEL: test_double_const:55; MEDIUM-P9: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha56; MEDIUM-P9: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l57; MEDIUM-P9: lfd {{[0-9]+}}, 0([[REG2]])58 59; LARGE-P9: [[VAR:[a-z0-9A-Z_.]+]]:60; LARGE-P9: .quad 0x3f4fd4920b498cf061; LARGE-P9-LABEL: test_double_const:62; LARGE-P9: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha63; LARGE-P9: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])64; LARGE-P9: lfd {{[0-9]+}}, 0([[REG2]])65