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1; RUN: llc -verify-machineinstrs < %s -enable-misched -pre-RA-sched=source -scheditins=false \2; RUN: -disable-ifcvt-triangle-false -disable-post-ra -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s3;4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"5 6; %val1 is a load live out of %entry. It should be hoisted7; above the add.8; CHECK-LABEL: testload:9; CHECK: %entry10; CHECK: lwz11; CHECK: addi12; CHECK: bne13; CHECK: %true14define i32 @testload(ptr %ptr, i32 %sumin) {15entry:16 %sum1 = add i32 %sumin, 117 %val1 = load i32, ptr %ptr18 %p = icmp eq i32 %sumin, 019 br i1 %p, label %true, label %end, !prof !120true:21 %sum2 = add i32 %sum1, 122 %ptr2 = getelementptr i32, ptr %ptr, i32 123 %val = load i32, ptr %ptr224 %val2 = add i32 %val1, %val25 br label %end26end:27 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]28 %summerge = phi i32 [ %sum1, %entry], [ %sum2, %true ]29 %sumout = add i32 %valmerge, %summerge30 ret i32 %sumout31}32 33; The prefetch gets a default latency of 3 cycles and should be hoisted34; above the add.35;36; CHECK-LABEL: testprefetch:37; CHECK: %entry38; CHECK: dcbt39; CHECK: addi40; CHECK: blr41define i32 @testprefetch(ptr %ptr, i32 %i) {42entry:43 %val1 = add i32 %i, 144 tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )45 %p = icmp eq i32 %i, 046 br i1 %p, label %true, label %end47true:48 %val2 = add i32 %val1, 149 br label %end50end:51 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ]52 ret i32 %valmerge53}54declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind55 56!1 = !{!"branch_weights", i32 2, i32 1}57