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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \9; RUN: -mcpu=future -ppc-asm-full-reg-names \10; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-WACC11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \12; RUN: -mcpu=future -ppc-asm-full-reg-names \13; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE-WACC14 15; assemble_acc16declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)17define void @ass_acc(ptr %ptr, <16 x i8> %vc) {18; CHECK-LABEL: ass_acc:19; CHECK: # %bb.0: # %entry20; CHECK-NEXT: xxlor vs3, v2, v221; CHECK-NEXT: xxlor vs2, v2, v222; CHECK-NEXT: xxlor vs0, vs2, vs223; CHECK-NEXT: xxlor vs1, vs3, vs324; CHECK-NEXT: stxv vs0, 48(r3)25; CHECK-NEXT: stxv vs1, 32(r3)26; CHECK-NEXT: stxv vs2, 16(r3)27; CHECK-NEXT: stxv vs3, 0(r3)28; CHECK-NEXT: blr29;30; CHECK-BE-LABEL: ass_acc:31; CHECK-BE: # %bb.0: # %entry32; CHECK-BE-NEXT: xxlor vs3, v2, v233; CHECK-BE-NEXT: xxlor vs2, v2, v234; CHECK-BE-NEXT: xxlor vs0, vs2, vs235; CHECK-BE-NEXT: xxlor vs1, vs3, vs336; CHECK-BE-NEXT: stxv vs1, 16(r3)37; CHECK-BE-NEXT: stxv vs0, 0(r3)38; CHECK-BE-NEXT: stxv vs3, 48(r3)39; CHECK-BE-NEXT: stxv vs2, 32(r3)40; CHECK-BE-NEXT: blr41;42; CHECK-WACC-LABEL: ass_acc:43; CHECK-WACC: # %bb.0: # %entry44; CHECK-WACC-NEXT: vmr v3, v245; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 046; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 047; CHECK-WACC-NEXT: stxv v4, 48(r3)48; CHECK-WACC-NEXT: stxv v5, 32(r3)49; CHECK-WACC-NEXT: stxv v2, 16(r3)50; CHECK-WACC-NEXT: stxv v3, 0(r3)51; CHECK-WACC-NEXT: blr52;53; CHECK-BE-WACC-LABEL: ass_acc:54; CHECK-BE-WACC: # %bb.0: # %entry55; CHECK-BE-WACC-NEXT: vmr v3, v256; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 057; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 058; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)59; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)60; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)61; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)62; CHECK-BE-WACC-NEXT: blr63entry:64 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)65 store <512 x i1> %0, ptr %ptr, align 6466 ret void67}68 69; xxmtacc70declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)71define void @int_xxmtacc(ptr %ptr, <16 x i8> %vc) {72; CHECK-LABEL: int_xxmtacc:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: xxlor vs3, v2, v275; CHECK-NEXT: xxlor vs2, v2, v276; CHECK-NEXT: xxlor vs0, vs2, vs277; CHECK-NEXT: xxlor vs1, vs3, vs378; CHECK-NEXT: xxmtacc acc079; CHECK-NEXT: stxv vs0, 48(r3)80; CHECK-NEXT: stxv vs1, 32(r3)81; CHECK-NEXT: stxv vs2, 16(r3)82; CHECK-NEXT: stxv vs3, 0(r3)83; CHECK-NEXT: blr84;85; CHECK-BE-LABEL: int_xxmtacc:86; CHECK-BE: # %bb.0: # %entry87; CHECK-BE-NEXT: xxlor vs3, v2, v288; CHECK-BE-NEXT: xxlor vs2, v2, v289; CHECK-BE-NEXT: xxlor vs0, vs2, vs290; CHECK-BE-NEXT: xxlor vs1, vs3, vs391; CHECK-BE-NEXT: xxmtacc acc092; CHECK-BE-NEXT: stxv vs1, 16(r3)93; CHECK-BE-NEXT: stxv vs0, 0(r3)94; CHECK-BE-NEXT: stxv vs3, 48(r3)95; CHECK-BE-NEXT: stxv vs2, 32(r3)96; CHECK-BE-NEXT: blr97;98; CHECK-WACC-LABEL: int_xxmtacc:99; CHECK-WACC: # %bb.0: # %entry100; CHECK-WACC-NEXT: vmr v3, v2101; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0102; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0103; CHECK-WACC-NEXT: stxv v4, 48(r3)104; CHECK-WACC-NEXT: stxv v5, 32(r3)105; CHECK-WACC-NEXT: stxv v2, 16(r3)106; CHECK-WACC-NEXT: stxv v3, 0(r3)107; CHECK-WACC-NEXT: blr108;109; CHECK-BE-WACC-LABEL: int_xxmtacc:110; CHECK-BE-WACC: # %bb.0: # %entry111; CHECK-BE-WACC-NEXT: vmr v3, v2112; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0113; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0114; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)115; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)116; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)117; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)118; CHECK-BE-WACC-NEXT: blr119entry:120; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is121; generated from the call to xxmtacc then one xxmfacc is generated for the store122 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)123 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)124 store <512 x i1> %1, ptr %ptr, align 64125 ret void126}127 128; xxmfacc129declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)130define void @int_xxmfacc(ptr %ptr, <16 x i8> %vc) {131; CHECK-LABEL: int_xxmfacc:132; CHECK: # %bb.0: # %entry133; CHECK-NEXT: xxlor vs3, v2, v2134; CHECK-NEXT: xxlor vs2, v2, v2135; CHECK-NEXT: xxlor vs0, vs2, vs2136; CHECK-NEXT: xxlor vs1, vs3, vs3137; CHECK-NEXT: stxv vs0, 48(r3)138; CHECK-NEXT: stxv vs1, 32(r3)139; CHECK-NEXT: stxv vs2, 16(r3)140; CHECK-NEXT: stxv vs3, 0(r3)141; CHECK-NEXT: blr142;143; CHECK-BE-LABEL: int_xxmfacc:144; CHECK-BE: # %bb.0: # %entry145; CHECK-BE-NEXT: xxlor vs3, v2, v2146; CHECK-BE-NEXT: xxlor vs2, v2, v2147; CHECK-BE-NEXT: xxlor vs0, vs2, vs2148; CHECK-BE-NEXT: xxlor vs1, vs3, vs3149; CHECK-BE-NEXT: stxv vs1, 16(r3)150; CHECK-BE-NEXT: stxv vs0, 0(r3)151; CHECK-BE-NEXT: stxv vs3, 48(r3)152; CHECK-BE-NEXT: stxv vs2, 32(r3)153; CHECK-BE-NEXT: blr154;155; CHECK-WACC-LABEL: int_xxmfacc:156; CHECK-WACC: # %bb.0: # %entry157; CHECK-WACC-NEXT: vmr v3, v2158; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0159; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0160; CHECK-WACC-NEXT: stxv v4, 48(r3)161; CHECK-WACC-NEXT: stxv v5, 32(r3)162; CHECK-WACC-NEXT: stxv v2, 16(r3)163; CHECK-WACC-NEXT: stxv v3, 0(r3)164; CHECK-WACC-NEXT: blr165;166; CHECK-BE-WACC-LABEL: int_xxmfacc:167; CHECK-BE-WACC: # %bb.0: # %entry168; CHECK-BE-WACC-NEXT: vmr v3, v2169; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 0170; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0171; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)172; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)173; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)174; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)175; CHECK-BE-WACC-NEXT: blr176entry:177; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is178; generated from the call to xxmfacc then one xxmfacc is generated for the store179 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)180 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)181 store <512 x i1> %1, ptr %ptr, align 64182 ret void183}184 185; xxsetaccz186declare <512 x i1> @llvm.ppc.mma.xxsetaccz()187define void @int_xxsetaccz(ptr %ptr) {188; CHECK-LABEL: int_xxsetaccz:189; CHECK: # %bb.0: # %entry190; CHECK-NEXT: xxsetaccz acc0191; CHECK-NEXT: xxmfacc acc0192; CHECK-NEXT: stxv vs0, 48(r3)193; CHECK-NEXT: stxv vs1, 32(r3)194; CHECK-NEXT: stxv vs2, 16(r3)195; CHECK-NEXT: stxv vs3, 0(r3)196; CHECK-NEXT: blr197;198; CHECK-BE-LABEL: int_xxsetaccz:199; CHECK-BE: # %bb.0: # %entry200; CHECK-BE-NEXT: xxsetaccz acc0201; CHECK-BE-NEXT: xxmfacc acc0202; CHECK-BE-NEXT: stxv vs1, 16(r3)203; CHECK-BE-NEXT: stxv vs0, 0(r3)204; CHECK-BE-NEXT: stxv vs3, 48(r3)205; CHECK-BE-NEXT: stxv vs2, 32(r3)206; CHECK-BE-NEXT: blr207;208; CHECK-WACC-LABEL: int_xxsetaccz:209; CHECK-WACC: # %bb.0: # %entry210; CHECK-WACC-NEXT: dmxxsetaccz wacc0211; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0212; CHECK-WACC-NEXT: stxv v4, 48(r3)213; CHECK-WACC-NEXT: stxv v5, 32(r3)214; CHECK-WACC-NEXT: stxv v2, 16(r3)215; CHECK-WACC-NEXT: stxv v3, 0(r3)216; CHECK-WACC-NEXT: blr217;218; CHECK-BE-WACC-LABEL: int_xxsetaccz:219; CHECK-BE-WACC: # %bb.0: # %entry220; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0221; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0222; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)223; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)224; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)225; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)226; CHECK-BE-WACC-NEXT: blr227entry:228 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()229 store <512 x i1> %0, ptr %ptr, align 64230 ret void231}232 233; disassemble_acc234declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)235define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {236; CHECK-LABEL: disass_acc:237; CHECK: # %bb.0: # %entry238; CHECK-NEXT: xxsetaccz acc0239; CHECK-NEXT: xxmfacc acc0240; CHECK-NEXT: stxv vs3, 0(r3)241; CHECK-NEXT: stxv vs2, 0(r4)242; CHECK-NEXT: stxv vs1, 0(r5)243; CHECK-NEXT: stxv vs0, 0(r6)244; CHECK-NEXT: blr245;246; CHECK-BE-LABEL: disass_acc:247; CHECK-BE: # %bb.0: # %entry248; CHECK-BE-NEXT: xxsetaccz acc0249; CHECK-BE-NEXT: xxmfacc acc0250; CHECK-BE-NEXT: stxv vs0, 0(r3)251; CHECK-BE-NEXT: stxv vs1, 0(r4)252; CHECK-BE-NEXT: stxv vs2, 0(r5)253; CHECK-BE-NEXT: stxv vs3, 0(r6)254; CHECK-BE-NEXT: blr255;256; CHECK-WACC-LABEL: disass_acc:257; CHECK-WACC: # %bb.0: # %entry258; CHECK-WACC-NEXT: dmxxsetaccz wacc0259; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0260; CHECK-WACC-NEXT: stxv v5, 0(r3)261; CHECK-WACC-NEXT: stxv v4, 0(r4)262; CHECK-WACC-NEXT: stxv v3, 0(r5)263; CHECK-WACC-NEXT: stxv v2, 0(r6)264; CHECK-WACC-NEXT: blr265;266; CHECK-BE-WACC-LABEL: disass_acc:267; CHECK-BE-WACC: # %bb.0: # %entry268; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0269; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0270; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)271; CHECK-BE-WACC-NEXT: stxv v3, 0(r4)272; CHECK-BE-WACC-NEXT: stxv v4, 0(r5)273; CHECK-BE-WACC-NEXT: stxv v5, 0(r6)274; CHECK-BE-WACC-NEXT: blr275entry:276 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()277 %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)278 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0279 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1280 %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2281 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3282 store <16 x i8> %2, ptr %ptr1, align 16283 store <16 x i8> %3, ptr %ptr2, align 16284 store <16 x i8> %4, ptr %ptr3, align 16285 store <16 x i8> %5, ptr %ptr4, align 16286 ret void287}288 289declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)290define void @testBranch(ptr %ptr, <16 x i8> %vc, i32 %val) {291; CHECK-LABEL: testBranch:292; CHECK: # %bb.0: # %entry293; CHECK-NEXT: cmplwi r7, 0294; CHECK-NEXT: beq cr0, .LBB5_2295; CHECK-NEXT: # %bb.1: # %if.then296; CHECK-NEXT: xxsetaccz acc0297; CHECK-NEXT: b .LBB5_3298; CHECK-NEXT: .LBB5_2: # %if.else299; CHECK-NEXT: lxv vs3, 0(r3)300; CHECK-NEXT: lxv vs2, 16(r3)301; CHECK-NEXT: lxv vs1, 32(r3)302; CHECK-NEXT: lxv vs0, 48(r3)303; CHECK-NEXT: xxmtacc acc0304; CHECK-NEXT: xvi4ger8pp acc0, v2, v2305; CHECK-NEXT: .LBB5_3: # %if.end306; CHECK-NEXT: xxmfacc acc0307; CHECK-NEXT: stxv vs0, 48(r3)308; CHECK-NEXT: stxv vs1, 32(r3)309; CHECK-NEXT: stxv vs2, 16(r3)310; CHECK-NEXT: stxv vs3, 0(r3)311; CHECK-NEXT: blr312;313; CHECK-BE-LABEL: testBranch:314; CHECK-BE: # %bb.0: # %entry315; CHECK-BE-NEXT: cmplwi r7, 0316; CHECK-BE-NEXT: beq cr0, .LBB5_2317; CHECK-BE-NEXT: # %bb.1: # %if.then318; CHECK-BE-NEXT: xxsetaccz acc0319; CHECK-BE-NEXT: b .LBB5_3320; CHECK-BE-NEXT: .LBB5_2: # %if.else321; CHECK-BE-NEXT: lxv vs3, 48(r3)322; CHECK-BE-NEXT: lxv vs2, 32(r3)323; CHECK-BE-NEXT: lxv vs1, 16(r3)324; CHECK-BE-NEXT: lxv vs0, 0(r3)325; CHECK-BE-NEXT: xxmtacc acc0326; CHECK-BE-NEXT: xvi4ger8pp acc0, v2, v2327; CHECK-BE-NEXT: .LBB5_3: # %if.end328; CHECK-BE-NEXT: xxmfacc acc0329; CHECK-BE-NEXT: stxv vs1, 16(r3)330; CHECK-BE-NEXT: stxv vs0, 0(r3)331; CHECK-BE-NEXT: stxv vs3, 48(r3)332; CHECK-BE-NEXT: stxv vs2, 32(r3)333; CHECK-BE-NEXT: blr334;335; CHECK-WACC-LABEL: testBranch:336; CHECK-WACC: # %bb.0: # %entry337; CHECK-WACC-NEXT: cmplwi r7, 0338; CHECK-WACC-NEXT: beq cr0, .LBB5_2339; CHECK-WACC-NEXT: # %bb.1: # %if.then340; CHECK-WACC-NEXT: dmxxsetaccz wacc0341; CHECK-WACC-NEXT: b .LBB5_3342; CHECK-WACC-NEXT: .LBB5_2: # %if.else343; CHECK-WACC-NEXT: lxv v5, 0(r3)344; CHECK-WACC-NEXT: lxv v1, 32(r3)345; CHECK-WACC-NEXT: lxv v4, 16(r3)346; CHECK-WACC-NEXT: lxv v0, 48(r3)347; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0348; CHECK-WACC-NEXT: xvi4ger8pp wacc0, v2, v2349; CHECK-WACC-NEXT: .LBB5_3: # %if.end350; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0351; CHECK-WACC-NEXT: stxv v4, 48(r3)352; CHECK-WACC-NEXT: stxv v5, 32(r3)353; CHECK-WACC-NEXT: stxv v2, 16(r3)354; CHECK-WACC-NEXT: stxv v3, 0(r3)355; CHECK-WACC-NEXT: blr356;357; CHECK-BE-WACC-LABEL: testBranch:358; CHECK-BE-WACC: # %bb.0: # %entry359; CHECK-BE-WACC-NEXT: cmplwi r7, 0360; CHECK-BE-WACC-NEXT: beq cr0, .LBB5_2361; CHECK-BE-WACC-NEXT: # %bb.1: # %if.then362; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0363; CHECK-BE-WACC-NEXT: b .LBB5_3364; CHECK-BE-WACC-NEXT: .LBB5_2: # %if.else365; CHECK-BE-WACC-NEXT: lxv v5, 48(r3)366; CHECK-BE-WACC-NEXT: lxv v1, 16(r3)367; CHECK-BE-WACC-NEXT: lxv v4, 32(r3)368; CHECK-BE-WACC-NEXT: lxv v0, 0(r3)369; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0370; CHECK-BE-WACC-NEXT: xvi4ger8pp wacc0, v2, v2371; CHECK-BE-WACC-NEXT: .LBB5_3: # %if.end372; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0373; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)374; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)375; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)376; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)377; CHECK-BE-WACC-NEXT: blr378entry:379 %tobool = icmp eq i32 %val, 0380 br i1 %tobool, label %if.else, label %if.then381 382if.then:383 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()384 br label %if.end385 386if.else:387 %1 = load <512 x i1>, ptr %ptr, align 64388 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)389 br label %if.end390 391if.end:392 %vq1.0 = phi <512 x i1> [ %0, %if.then ], [ %2, %if.else ]393 store <512 x i1> %vq1.0, ptr %ptr, align 64394 ret void395}396 397; The following test cases check that the xxsetaccz instruction is correctly rematerialized398declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)399declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)400declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)401 402define void @testcse(ptr %res, <16 x i8> %vc) {403; CHECK-LABEL: testcse:404; CHECK: # %bb.0: # %entry405; CHECK-NEXT: xxsetaccz acc0406; CHECK-NEXT: xvf32gerpp acc0, v2, v2407; CHECK-NEXT: xxmfacc acc0408; CHECK-NEXT: stxv vs0, 48(r3)409; CHECK-NEXT: stxv vs1, 32(r3)410; CHECK-NEXT: stxv vs2, 16(r3)411; CHECK-NEXT: stxv vs3, 0(r3)412; CHECK-NEXT: stxv vs0, 112(r3)413; CHECK-NEXT: stxv vs1, 96(r3)414; CHECK-NEXT: stxv vs2, 80(r3)415; CHECK-NEXT: stxv vs3, 64(r3)416; CHECK-NEXT: blr417;418; CHECK-BE-LABEL: testcse:419; CHECK-BE: # %bb.0: # %entry420; CHECK-BE-NEXT: xxsetaccz acc0421; CHECK-BE-NEXT: xvf32gerpp acc0, v2, v2422; CHECK-BE-NEXT: xxmfacc acc0423; CHECK-BE-NEXT: stxv vs1, 16(r3)424; CHECK-BE-NEXT: stxv vs0, 0(r3)425; CHECK-BE-NEXT: stxv vs3, 48(r3)426; CHECK-BE-NEXT: stxv vs2, 32(r3)427; CHECK-BE-NEXT: stxv vs1, 80(r3)428; CHECK-BE-NEXT: stxv vs0, 64(r3)429; CHECK-BE-NEXT: stxv vs3, 112(r3)430; CHECK-BE-NEXT: stxv vs2, 96(r3)431; CHECK-BE-NEXT: blr432;433; CHECK-WACC-LABEL: testcse:434; CHECK-WACC: # %bb.0: # %entry435; CHECK-WACC-NEXT: dmxxsetaccz wacc0436; CHECK-WACC-NEXT: xvf32gerpp wacc0, v2, v2437; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0438; CHECK-WACC-NEXT: stxv v4, 48(r3)439; CHECK-WACC-NEXT: stxv v5, 32(r3)440; CHECK-WACC-NEXT: stxv v2, 16(r3)441; CHECK-WACC-NEXT: stxv v3, 0(r3)442; CHECK-WACC-NEXT: stxv v4, 112(r3)443; CHECK-WACC-NEXT: stxv v5, 96(r3)444; CHECK-WACC-NEXT: stxv v2, 80(r3)445; CHECK-WACC-NEXT: stxv v3, 64(r3)446; CHECK-WACC-NEXT: blr447;448; CHECK-BE-WACC-LABEL: testcse:449; CHECK-BE-WACC: # %bb.0: # %entry450; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0451; CHECK-BE-WACC-NEXT: xvf32gerpp wacc0, v2, v2452; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0453; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)454; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)455; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)456; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)457; CHECK-BE-WACC-NEXT: stxv v5, 112(r3)458; CHECK-BE-WACC-NEXT: stxv v4, 96(r3)459; CHECK-BE-WACC-NEXT: stxv v3, 80(r3)460; CHECK-BE-WACC-NEXT: stxv v2, 64(r3)461; CHECK-BE-WACC-NEXT: blr462entry:463 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()464 %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()465 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)466 %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)467 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 1468 store <512 x i1> %2, ptr %res, align 64469 store <512 x i1> %3, ptr %4, align 64470 ret void471}472 473define void @testcse2(ptr %res, <16 x i8> %vc) {474; CHECK-LABEL: testcse2:475; CHECK: # %bb.0: # %entry476; CHECK-NEXT: xxsetaccz acc0477; CHECK-NEXT: xxsetaccz acc1478; CHECK-NEXT: xvf32gerpp acc1, v2, v2479; CHECK-NEXT: xvf32gerpn acc0, v2, v2480; CHECK-NEXT: xxmfacc acc1481; CHECK-NEXT: xxmfacc acc0482; CHECK-NEXT: stxv vs4, 48(r3)483; CHECK-NEXT: stxv vs5, 32(r3)484; CHECK-NEXT: stxv vs6, 16(r3)485; CHECK-NEXT: stxv vs7, 0(r3)486; CHECK-NEXT: stxv vs0, 112(r3)487; CHECK-NEXT: stxv vs1, 96(r3)488; CHECK-NEXT: stxv vs2, 80(r3)489; CHECK-NEXT: stxv vs3, 64(r3)490; CHECK-NEXT: blr491;492; CHECK-BE-LABEL: testcse2:493; CHECK-BE: # %bb.0: # %entry494; CHECK-BE-NEXT: xxsetaccz acc0495; CHECK-BE-NEXT: xxsetaccz acc1496; CHECK-BE-NEXT: xvf32gerpp acc1, v2, v2497; CHECK-BE-NEXT: xvf32gerpn acc0, v2, v2498; CHECK-BE-NEXT: xxmfacc acc1499; CHECK-BE-NEXT: xxmfacc acc0500; CHECK-BE-NEXT: stxv vs5, 16(r3)501; CHECK-BE-NEXT: stxv vs4, 0(r3)502; CHECK-BE-NEXT: stxv vs7, 48(r3)503; CHECK-BE-NEXT: stxv vs6, 32(r3)504; CHECK-BE-NEXT: stxv vs1, 80(r3)505; CHECK-BE-NEXT: stxv vs0, 64(r3)506; CHECK-BE-NEXT: stxv vs3, 112(r3)507; CHECK-BE-NEXT: stxv vs2, 96(r3)508; CHECK-BE-NEXT: blr509;510; CHECK-WACC-LABEL: testcse2:511; CHECK-WACC: # %bb.0: # %entry512; CHECK-WACC-NEXT: dmxxsetaccz wacc1513; CHECK-WACC-NEXT: dmxxsetaccz wacc0514; CHECK-WACC-NEXT: xvf32gerpp wacc1, v2, v2515; CHECK-WACC-NEXT: xvf32gerpn wacc0, v2, v2516; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0517; CHECK-WACC-NEXT: stxv v4, 48(r3)518; CHECK-WACC-NEXT: stxv v5, 32(r3)519; CHECK-WACC-NEXT: stxv v2, 16(r3)520; CHECK-WACC-NEXT: stxv v3, 0(r3)521; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0522; CHECK-WACC-NEXT: stxv v4, 112(r3)523; CHECK-WACC-NEXT: stxv v5, 96(r3)524; CHECK-WACC-NEXT: stxv v2, 80(r3)525; CHECK-WACC-NEXT: stxv v3, 64(r3)526; CHECK-WACC-NEXT: blr527;528; CHECK-BE-WACC-LABEL: testcse2:529; CHECK-BE-WACC: # %bb.0: # %entry530; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc1531; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0532; CHECK-BE-WACC-NEXT: xvf32gerpp wacc1, v2, v2533; CHECK-BE-WACC-NEXT: xvf32gerpn wacc0, v2, v2534; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0535; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)536; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)537; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)538; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)539; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0540; CHECK-BE-WACC-NEXT: stxv v5, 112(r3)541; CHECK-BE-WACC-NEXT: stxv v4, 96(r3)542; CHECK-BE-WACC-NEXT: stxv v3, 80(r3)543; CHECK-BE-WACC-NEXT: stxv v2, 64(r3)544; CHECK-BE-WACC-NEXT: blr545entry:546 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()547 %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()548 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)549 %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)550 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 1551 store <512 x i1> %2, ptr %res, align 64552 store <512 x i1> %3, ptr %4, align 64553 ret void554}555 556define void @testcse3(ptr %res, <16 x i8> %vc) {557; CHECK-LABEL: testcse3:558; CHECK: # %bb.0: # %entry559; CHECK-NEXT: xxsetaccz acc0560; CHECK-NEXT: xxsetaccz acc1561; CHECK-NEXT: xvf32gerpp acc1, v2, v2562; CHECK-NEXT: xvf32gerpn acc0, v2, v2563; CHECK-NEXT: xxmfacc acc1564; CHECK-NEXT: xxmfacc acc0565; CHECK-NEXT: stxv vs4, 48(r3)566; CHECK-NEXT: stxv vs5, 32(r3)567; CHECK-NEXT: stxv vs6, 16(r3)568; CHECK-NEXT: stxv vs7, 0(r3)569; CHECK-NEXT: stxv vs0, 112(r3)570; CHECK-NEXT: stxv vs1, 96(r3)571; CHECK-NEXT: stxv vs2, 80(r3)572; CHECK-NEXT: stxv vs3, 64(r3)573; CHECK-NEXT: blr574;575; CHECK-BE-LABEL: testcse3:576; CHECK-BE: # %bb.0: # %entry577; CHECK-BE-NEXT: xxsetaccz acc0578; CHECK-BE-NEXT: xxsetaccz acc1579; CHECK-BE-NEXT: xvf32gerpp acc1, v2, v2580; CHECK-BE-NEXT: xvf32gerpn acc0, v2, v2581; CHECK-BE-NEXT: xxmfacc acc1582; CHECK-BE-NEXT: xxmfacc acc0583; CHECK-BE-NEXT: stxv vs5, 16(r3)584; CHECK-BE-NEXT: stxv vs4, 0(r3)585; CHECK-BE-NEXT: stxv vs7, 48(r3)586; CHECK-BE-NEXT: stxv vs6, 32(r3)587; CHECK-BE-NEXT: stxv vs1, 80(r3)588; CHECK-BE-NEXT: stxv vs0, 64(r3)589; CHECK-BE-NEXT: stxv vs3, 112(r3)590; CHECK-BE-NEXT: stxv vs2, 96(r3)591; CHECK-BE-NEXT: blr592;593; CHECK-WACC-LABEL: testcse3:594; CHECK-WACC: # %bb.0: # %entry595; CHECK-WACC-NEXT: dmxxsetaccz wacc1596; CHECK-WACC-NEXT: dmxxsetaccz wacc0597; CHECK-WACC-NEXT: xvf32gerpp wacc1, v2, v2598; CHECK-WACC-NEXT: xvf32gerpn wacc0, v2, v2599; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0600; CHECK-WACC-NEXT: stxv v4, 48(r3)601; CHECK-WACC-NEXT: stxv v5, 32(r3)602; CHECK-WACC-NEXT: stxv v2, 16(r3)603; CHECK-WACC-NEXT: stxv v3, 0(r3)604; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0605; CHECK-WACC-NEXT: stxv v4, 112(r3)606; CHECK-WACC-NEXT: stxv v5, 96(r3)607; CHECK-WACC-NEXT: stxv v2, 80(r3)608; CHECK-WACC-NEXT: stxv v3, 64(r3)609; CHECK-WACC-NEXT: blr610;611; CHECK-BE-WACC-LABEL: testcse3:612; CHECK-BE-WACC: # %bb.0: # %entry613; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc1614; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0615; CHECK-BE-WACC-NEXT: xvf32gerpp wacc1, v2, v2616; CHECK-BE-WACC-NEXT: xvf32gerpn wacc0, v2, v2617; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0618; CHECK-BE-WACC-NEXT: stxv v5, 48(r3)619; CHECK-BE-WACC-NEXT: stxv v4, 32(r3)620; CHECK-BE-WACC-NEXT: stxv v3, 16(r3)621; CHECK-BE-WACC-NEXT: stxv v2, 0(r3)622; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0623; CHECK-BE-WACC-NEXT: stxv v5, 112(r3)624; CHECK-BE-WACC-NEXT: stxv v4, 96(r3)625; CHECK-BE-WACC-NEXT: stxv v3, 80(r3)626; CHECK-BE-WACC-NEXT: stxv v2, 64(r3)627; CHECK-BE-WACC-NEXT: blr628entry:629 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()630 %1 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)631 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)632 %3 = getelementptr inbounds <512 x i1>, ptr %res, i64 1633 store <512 x i1> %1, ptr %res, align 64634 store <512 x i1> %2, ptr %3, align 64635 ret void636}637 638define void @testcse4(ptr %res, i32 %lim, ptr %vc) {639; CHECK-LABEL: testcse4:640; CHECK: # %bb.0: # %entry641; CHECK-NEXT: cmpwi r4, 1642; CHECK-NEXT: bltlr cr0643; CHECK-NEXT: # %bb.1: # %for.body.preheader644; CHECK-NEXT: clrldi r4, r4, 32645; CHECK-NEXT: li r6, 0646; CHECK-NEXT: mtctr r4647; CHECK-NEXT: li r4, 0648; CHECK-NEXT: .p2align 4649; CHECK-NEXT: .LBB9_2: # %for.body650; CHECK-NEXT: #651; CHECK-NEXT: rldic r7, r6, 4, 28652; CHECK-NEXT: xxsetaccz acc2653; CHECK-NEXT: xxsetaccz acc1654; CHECK-NEXT: addi r6, r6, 6655; CHECK-NEXT: add r8, r5, r7656; CHECK-NEXT: lxvx vs0, r5, r7657; CHECK-NEXT: rldic r7, r4, 6, 26658; CHECK-NEXT: addi r4, r4, 3659; CHECK-NEXT: lxv vs1, 16(r8)660; CHECK-NEXT: xvf32gerpp acc2, vs0, vs1661; CHECK-NEXT: lxv vs0, 32(r8)662; CHECK-NEXT: lxv vs1, 48(r8)663; CHECK-NEXT: xvf32gerpn acc1, vs0, vs1664; CHECK-NEXT: lxv vs12, 64(r8)665; CHECK-NEXT: lxv vs13, 80(r8)666; CHECK-NEXT: xxsetaccz acc0667; CHECK-NEXT: add r8, r3, r7668; CHECK-NEXT: xxmfacc acc2669; CHECK-NEXT: xvf32gernp acc0, vs12, vs13670; CHECK-NEXT: stxvx vs11, r3, r7671; CHECK-NEXT: stxv vs8, 48(r8)672; CHECK-NEXT: xxmfacc acc1673; CHECK-NEXT: stxv vs9, 32(r8)674; CHECK-NEXT: stxv vs10, 16(r8)675; CHECK-NEXT: stxv vs4, 112(r8)676; CHECK-NEXT: stxv vs5, 96(r8)677; CHECK-NEXT: xxmfacc acc0678; CHECK-NEXT: stxv vs6, 80(r8)679; CHECK-NEXT: stxv vs7, 64(r8)680; CHECK-NEXT: stxv vs0, 176(r8)681; CHECK-NEXT: stxv vs1, 160(r8)682; CHECK-NEXT: stxv vs2, 144(r8)683; CHECK-NEXT: stxv vs3, 128(r8)684; CHECK-NEXT: bdnz .LBB9_2685; CHECK-NEXT: # %bb.3: # %for.cond.cleanup686; CHECK-NEXT: blr687;688; CHECK-BE-LABEL: testcse4:689; CHECK-BE: # %bb.0: # %entry690; CHECK-BE-NEXT: cmpwi r4, 1691; CHECK-BE-NEXT: bltlr cr0692; CHECK-BE-NEXT: # %bb.1: # %for.body.preheader693; CHECK-BE-NEXT: clrldi r4, r4, 32694; CHECK-BE-NEXT: li r6, 0695; CHECK-BE-NEXT: mtctr r4696; CHECK-BE-NEXT: li r4, 0697; CHECK-BE-NEXT: .p2align 4698; CHECK-BE-NEXT: .LBB9_2: # %for.body699; CHECK-BE-NEXT: #700; CHECK-BE-NEXT: rldic r7, r6, 4, 28701; CHECK-BE-NEXT: xxsetaccz acc2702; CHECK-BE-NEXT: xxsetaccz acc1703; CHECK-BE-NEXT: addi r6, r6, 6704; CHECK-BE-NEXT: add r8, r5, r7705; CHECK-BE-NEXT: lxvx vs0, r5, r7706; CHECK-BE-NEXT: rldic r7, r4, 6, 26707; CHECK-BE-NEXT: addi r4, r4, 3708; CHECK-BE-NEXT: lxv vs1, 16(r8)709; CHECK-BE-NEXT: xvf32gerpp acc2, vs0, vs1710; CHECK-BE-NEXT: lxv vs0, 32(r8)711; CHECK-BE-NEXT: lxv vs1, 48(r8)712; CHECK-BE-NEXT: xvf32gerpn acc1, vs0, vs1713; CHECK-BE-NEXT: lxv vs12, 64(r8)714; CHECK-BE-NEXT: lxv vs13, 80(r8)715; CHECK-BE-NEXT: xxsetaccz acc0716; CHECK-BE-NEXT: add r8, r3, r7717; CHECK-BE-NEXT: xxmfacc acc2718; CHECK-BE-NEXT: xvf32gernp acc0, vs12, vs13719; CHECK-BE-NEXT: stxvx vs8, r3, r7720; CHECK-BE-NEXT: stxv vs9, 16(r8)721; CHECK-BE-NEXT: xxmfacc acc1722; CHECK-BE-NEXT: stxv vs11, 48(r8)723; CHECK-BE-NEXT: stxv vs10, 32(r8)724; CHECK-BE-NEXT: stxv vs5, 80(r8)725; CHECK-BE-NEXT: stxv vs4, 64(r8)726; CHECK-BE-NEXT: xxmfacc acc0727; CHECK-BE-NEXT: stxv vs7, 112(r8)728; CHECK-BE-NEXT: stxv vs6, 96(r8)729; CHECK-BE-NEXT: stxv vs1, 144(r8)730; CHECK-BE-NEXT: stxv vs0, 128(r8)731; CHECK-BE-NEXT: stxv vs3, 176(r8)732; CHECK-BE-NEXT: stxv vs2, 160(r8)733; CHECK-BE-NEXT: bdnz .LBB9_2734; CHECK-BE-NEXT: # %bb.3: # %for.cond.cleanup735; CHECK-BE-NEXT: blr736;737; CHECK-WACC-LABEL: testcse4:738; CHECK-WACC: # %bb.0: # %entry739; CHECK-WACC-NEXT: cmpwi r4, 1740; CHECK-WACC-NEXT: bltlr cr0741; CHECK-WACC-NEXT: # %bb.1: # %for.body.preheader742; CHECK-WACC-NEXT: clrldi r4, r4, 32743; CHECK-WACC-NEXT: mtctr r4744; CHECK-WACC-NEXT: li r4, 0745; CHECK-WACC-NEXT: li r6, 0746; CHECK-WACC-NEXT: .p2align 4747; CHECK-WACC-NEXT: .LBB9_2: # %for.body748; CHECK-WACC-NEXT: #749; CHECK-WACC-NEXT: rldic r7, r6, 4, 28750; CHECK-WACC-NEXT: add r8, r5, r7751; CHECK-WACC-NEXT: lxvx vs0, r5, r7752; CHECK-WACC-NEXT: lxv vs1, 16(r8)753; CHECK-WACC-NEXT: dmxxsetaccz wacc2754; CHECK-WACC-NEXT: dmxxsetaccz wacc1755; CHECK-WACC-NEXT: dmxxsetaccz wacc0756; CHECK-WACC-NEXT: xvf32gerpp wacc2, vs0, vs1757; CHECK-WACC-NEXT: lxv vs0, 32(r8)758; CHECK-WACC-NEXT: lxv vs1, 48(r8)759; CHECK-WACC-NEXT: rldic r7, r4, 6, 26760; CHECK-WACC-NEXT: addi r4, r4, 3761; CHECK-WACC-NEXT: addi r6, r6, 6762; CHECK-WACC-NEXT: xvf32gerpn wacc1, vs0, vs1763; CHECK-WACC-NEXT: lxv vs0, 64(r8)764; CHECK-WACC-NEXT: lxv vs1, 80(r8)765; CHECK-WACC-NEXT: add r8, r3, r7766; CHECK-WACC-NEXT: xvf32gernp wacc0, vs0, vs1767; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc2, 0768; CHECK-WACC-NEXT: stxvx v3, r3, r7769; CHECK-WACC-NEXT: stxv v4, 48(r8)770; CHECK-WACC-NEXT: stxv v5, 32(r8)771; CHECK-WACC-NEXT: stxv v2, 16(r8)772; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0773; CHECK-WACC-NEXT: stxv v4, 112(r8)774; CHECK-WACC-NEXT: stxv v5, 96(r8)775; CHECK-WACC-NEXT: stxv v2, 80(r8)776; CHECK-WACC-NEXT: stxv v3, 64(r8)777; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0778; CHECK-WACC-NEXT: stxv v4, 176(r8)779; CHECK-WACC-NEXT: stxv v5, 160(r8)780; CHECK-WACC-NEXT: stxv v2, 144(r8)781; CHECK-WACC-NEXT: stxv v3, 128(r8)782; CHECK-WACC-NEXT: bdnz .LBB9_2783; CHECK-WACC-NEXT: # %bb.3: # %for.cond.cleanup784; CHECK-WACC-NEXT: blr785;786; CHECK-BE-WACC-LABEL: testcse4:787; CHECK-BE-WACC: # %bb.0: # %entry788; CHECK-BE-WACC-NEXT: cmpwi r4, 1789; CHECK-BE-WACC-NEXT: bltlr cr0790; CHECK-BE-WACC-NEXT: # %bb.1: # %for.body.preheader791; CHECK-BE-WACC-NEXT: clrldi r4, r4, 32792; CHECK-BE-WACC-NEXT: mtctr r4793; CHECK-BE-WACC-NEXT: li r4, 0794; CHECK-BE-WACC-NEXT: li r6, 0795; CHECK-BE-WACC-NEXT: .p2align 4796; CHECK-BE-WACC-NEXT: .LBB9_2: # %for.body797; CHECK-BE-WACC-NEXT: #798; CHECK-BE-WACC-NEXT: rldic r7, r6, 4, 28799; CHECK-BE-WACC-NEXT: add r8, r5, r7800; CHECK-BE-WACC-NEXT: lxvx vs0, r5, r7801; CHECK-BE-WACC-NEXT: lxv vs1, 16(r8)802; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc2803; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc1804; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0805; CHECK-BE-WACC-NEXT: xvf32gerpp wacc2, vs0, vs1806; CHECK-BE-WACC-NEXT: lxv vs0, 32(r8)807; CHECK-BE-WACC-NEXT: lxv vs1, 48(r8)808; CHECK-BE-WACC-NEXT: rldic r7, r4, 6, 26809; CHECK-BE-WACC-NEXT: addi r4, r4, 3810; CHECK-BE-WACC-NEXT: addi r6, r6, 6811; CHECK-BE-WACC-NEXT: xvf32gerpn wacc1, vs0, vs1812; CHECK-BE-WACC-NEXT: lxv vs0, 64(r8)813; CHECK-BE-WACC-NEXT: lxv vs1, 80(r8)814; CHECK-BE-WACC-NEXT: add r8, r3, r7815; CHECK-BE-WACC-NEXT: xvf32gernp wacc0, vs0, vs1816; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc2, 0817; CHECK-BE-WACC-NEXT: stxvx v2, r3, r7818; CHECK-BE-WACC-NEXT: stxv v5, 48(r8)819; CHECK-BE-WACC-NEXT: stxv v4, 32(r8)820; CHECK-BE-WACC-NEXT: stxv v3, 16(r8)821; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc1, 0822; CHECK-BE-WACC-NEXT: stxv v5, 112(r8)823; CHECK-BE-WACC-NEXT: stxv v4, 96(r8)824; CHECK-BE-WACC-NEXT: stxv v3, 80(r8)825; CHECK-BE-WACC-NEXT: stxv v2, 64(r8)826; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0827; CHECK-BE-WACC-NEXT: stxv v5, 176(r8)828; CHECK-BE-WACC-NEXT: stxv v4, 160(r8)829; CHECK-BE-WACC-NEXT: stxv v3, 144(r8)830; CHECK-BE-WACC-NEXT: stxv v2, 128(r8)831; CHECK-BE-WACC-NEXT: bdnz .LBB9_2832; CHECK-BE-WACC-NEXT: # %bb.3: # %for.cond.cleanup833; CHECK-BE-WACC-NEXT: blr834entry:835 %cmp55 = icmp sgt i32 %lim, 0836 br i1 %cmp55, label %for.body.preheader, label %for.cond.cleanup837 838for.body.preheader: ; preds = %entry839 %wide.trip.count = zext i32 %lim to i64840 br label %for.body841 842for.cond.cleanup: ; preds = %for.body, %entry843 ret void844 845for.body: ; preds = %for.body, %for.body.preheader846 %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]847 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()848 %1 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()849 %2 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()850 %3 = trunc i64 %indvars.iv to i32851 %mul = mul nsw i32 %3, 6852 %idxprom = zext i32 %mul to i64853 %arrayidx = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom854 %4 = load <16 x i8>, ptr %arrayidx, align 16855 %add2 = or disjoint i32 %mul, 1856 %idxprom3 = zext i32 %add2 to i64857 %arrayidx4 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom3858 %5 = load <16 x i8>, ptr %arrayidx4, align 16859 %6 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %4, <16 x i8> %5)860 %add6 = add nuw nsw i32 %mul, 2861 %idxprom7 = zext i32 %add6 to i64862 %arrayidx8 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom7863 %7 = load <16 x i8>, ptr %arrayidx8, align 16864 %add10 = add nuw nsw i32 %mul, 3865 %idxprom11 = zext i32 %add10 to i64866 %arrayidx12 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom11867 %8 = load <16 x i8>, ptr %arrayidx12, align 16868 %9 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %1, <16 x i8> %7, <16 x i8> %8)869 %add14 = add nuw nsw i32 %mul, 4870 %idxprom15 = zext i32 %add14 to i64871 %arrayidx16 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom15872 %10 = load <16 x i8>, ptr %arrayidx16, align 16873 %add18 = add nuw nsw i32 %mul, 5874 %idxprom19 = zext i32 %add18 to i64875 %arrayidx20 = getelementptr inbounds <16 x i8>, ptr %vc, i64 %idxprom19876 %11 = load <16 x i8>, ptr %arrayidx20, align 16877 %12 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %2, <16 x i8> %10, <16 x i8> %11)878 %mul21 = mul i64 %indvars.iv, 3879 %idx.ext = and i64 %mul21, 4294967295880 %add.ptr = getelementptr inbounds <512 x i1>, ptr %res, i64 %idx.ext881 store <512 x i1> %6, ptr %add.ptr, align 64882 %add.ptr26 = getelementptr inbounds <512 x i1>, ptr %add.ptr, i64 1883 store <512 x i1> %9, ptr %add.ptr26, align 64884 %add.ptr30 = getelementptr inbounds <512 x i1>, ptr %add.ptr, i64 2885 store <512 x i1> %12, ptr %add.ptr30, align 64886 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1887 %exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count888 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body889}890 891declare i32 @testRedundantPrimeUnprimeF()892define void @testRedundantPrimeUnprime(ptr %dst, <16 x i8> %vc) nounwind {893; CHECK-LABEL: testRedundantPrimeUnprime:894; CHECK: # %bb.0: # %entry895; CHECK-NEXT: mflr r0896; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill897; CHECK-NEXT: std r0, 16(r1)898; CHECK-NEXT: stdu r1, -112(r1)899; CHECK-NEXT: xxsetaccz acc0900; CHECK-NEXT: xxsetaccz acc1901; CHECK-NEXT: mr r30, r3902; CHECK-NEXT: xxmfacc acc0903; CHECK-NEXT: stxv vs0, 48(r3)904; CHECK-NEXT: stxv vs1, 32(r3)905; CHECK-NEXT: stxv vs2, 16(r3)906; CHECK-NEXT: stxv vs3, 0(r3)907; CHECK-NEXT: xvf32gerpp acc1, v2, v2908; CHECK-NEXT: xxmfacc acc1909; CHECK-NEXT: stxv vs4, 80(r1)910; CHECK-NEXT: stxv vs5, 64(r1)911; CHECK-NEXT: stxv vs6, 48(r1)912; CHECK-NEXT: stxv vs7, 32(r1)913; CHECK-NEXT: bl testRedundantPrimeUnprimeF@notoc914; CHECK-NEXT: lxvp vsp0, 64(r1)915; CHECK-NEXT: lxvp vsp2, 32(r1)916; CHECK-NEXT: stxv vs0, 112(r30)917; CHECK-NEXT: stxv vs1, 96(r30)918; CHECK-NEXT: stxv vs2, 80(r30)919; CHECK-NEXT: stxv vs3, 64(r30)920; CHECK-NEXT: addi r1, r1, 112921; CHECK-NEXT: ld r0, 16(r1)922; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload923; CHECK-NEXT: mtlr r0924; CHECK-NEXT: blr925;926; CHECK-BE-LABEL: testRedundantPrimeUnprime:927; CHECK-BE: # %bb.0: # %entry928; CHECK-BE-NEXT: mflr r0929; CHECK-BE-NEXT: std r0, 16(r1)930; CHECK-BE-NEXT: stdu r1, -192(r1)931; CHECK-BE-NEXT: xxsetaccz acc0932; CHECK-BE-NEXT: xxsetaccz acc1933; CHECK-BE-NEXT: std r30, 176(r1) # 8-byte Folded Spill934; CHECK-BE-NEXT: mr r30, r3935; CHECK-BE-NEXT: xxmfacc acc0936; CHECK-BE-NEXT: stxv vs1, 16(r3)937; CHECK-BE-NEXT: stxv vs0, 0(r3)938; CHECK-BE-NEXT: stxv vs3, 48(r3)939; CHECK-BE-NEXT: stxv vs2, 32(r3)940; CHECK-BE-NEXT: xvf32gerpp acc1, v2, v2941; CHECK-BE-NEXT: xxmfacc acc1942; CHECK-BE-NEXT: stxv vs4, 112(r1)943; CHECK-BE-NEXT: stxv vs5, 128(r1)944; CHECK-BE-NEXT: stxv vs6, 144(r1)945; CHECK-BE-NEXT: stxv vs7, 160(r1)946; CHECK-BE-NEXT: bl testRedundantPrimeUnprimeF947; CHECK-BE-NEXT: nop948; CHECK-BE-NEXT: lxvp vsp0, 112(r1)949; CHECK-BE-NEXT: lxvp vsp2, 144(r1)950; CHECK-BE-NEXT: stxv vs3, 112(r30)951; CHECK-BE-NEXT: stxv vs2, 96(r30)952; CHECK-BE-NEXT: stxv vs1, 80(r30)953; CHECK-BE-NEXT: stxv vs0, 64(r30)954; CHECK-BE-NEXT: ld r30, 176(r1) # 8-byte Folded Reload955; CHECK-BE-NEXT: addi r1, r1, 192956; CHECK-BE-NEXT: ld r0, 16(r1)957; CHECK-BE-NEXT: mtlr r0958; CHECK-BE-NEXT: blr959;960; CHECK-WACC-LABEL: testRedundantPrimeUnprime:961; CHECK-WACC: # %bb.0: # %entry962; CHECK-WACC-NEXT: mflr r0963; CHECK-WACC-NEXT: std r30, -16(r1) # 8-byte Folded Spill964; CHECK-WACC-NEXT: std r0, 16(r1)965; CHECK-WACC-NEXT: stdu r1, -112(r1)966; CHECK-WACC-NEXT: dmxxsetaccz wacc0967; CHECK-WACC-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0968; CHECK-WACC-NEXT: stxv v0, 48(r3)969; CHECK-WACC-NEXT: stxv v1, 32(r3)970; CHECK-WACC-NEXT: stxv v4, 16(r3)971; CHECK-WACC-NEXT: stxv v5, 0(r3)972; CHECK-WACC-NEXT: xvf32gerpp wacc0, v2, v2973; CHECK-WACC-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 0974; CHECK-WACC-NEXT: mr r30, r3975; CHECK-WACC-NEXT: stxvp vsp36, 64(r1)976; CHECK-WACC-NEXT: stxvp vsp34, 32(r1)977; CHECK-WACC-NEXT: bl testRedundantPrimeUnprimeF@notoc978; CHECK-WACC-NEXT: lxvp vsp34, 64(r1)979; CHECK-WACC-NEXT: lxvp vsp36, 32(r1)980; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0981; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0982; CHECK-WACC-NEXT: stxv v4, 112(r30)983; CHECK-WACC-NEXT: stxv v5, 96(r30)984; CHECK-WACC-NEXT: stxv v2, 80(r30)985; CHECK-WACC-NEXT: stxv v3, 64(r30)986; CHECK-WACC-NEXT: addi r1, r1, 112987; CHECK-WACC-NEXT: ld r0, 16(r1)988; CHECK-WACC-NEXT: ld r30, -16(r1) # 8-byte Folded Reload989; CHECK-WACC-NEXT: mtlr r0990; CHECK-WACC-NEXT: blr991;992; CHECK-BE-WACC-LABEL: testRedundantPrimeUnprime:993; CHECK-BE-WACC: # %bb.0: # %entry994; CHECK-BE-WACC-NEXT: mflr r0995; CHECK-BE-WACC-NEXT: std r0, 16(r1)996; CHECK-BE-WACC-NEXT: stdu r1, -192(r1)997; CHECK-BE-WACC-NEXT: dmxxsetaccz wacc0998; CHECK-BE-WACC-NEXT: std r30, 176(r1) # 8-byte Folded Spill999; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 01000; CHECK-BE-WACC-NEXT: stxv v1, 48(r3)1001; CHECK-BE-WACC-NEXT: stxv v0, 32(r3)1002; CHECK-BE-WACC-NEXT: stxv v5, 16(r3)1003; CHECK-BE-WACC-NEXT: stxv v4, 0(r3)1004; CHECK-BE-WACC-NEXT: xvf32gerpp wacc0, v2, v21005; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp36, vsp34, wacc0, 01006; CHECK-BE-WACC-NEXT: mr r30, r31007; CHECK-BE-WACC-NEXT: stxvp vsp36, 112(r1)1008; CHECK-BE-WACC-NEXT: stxvp vsp34, 144(r1)1009; CHECK-BE-WACC-NEXT: bl testRedundantPrimeUnprimeF1010; CHECK-BE-WACC-NEXT: nop1011; CHECK-BE-WACC-NEXT: lxvp vsp34, 112(r1)1012; CHECK-BE-WACC-NEXT: lxvp vsp36, 144(r1)1013; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 01014; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01015; CHECK-BE-WACC-NEXT: stxv v5, 112(r30)1016; CHECK-BE-WACC-NEXT: stxv v4, 96(r30)1017; CHECK-BE-WACC-NEXT: stxv v3, 80(r30)1018; CHECK-BE-WACC-NEXT: stxv v2, 64(r30)1019; CHECK-BE-WACC-NEXT: ld r30, 176(r1) # 8-byte Folded Reload1020; CHECK-BE-WACC-NEXT: addi r1, r1, 1921021; CHECK-BE-WACC-NEXT: ld r0, 16(r1)1022; CHECK-BE-WACC-NEXT: mtlr r01023; CHECK-BE-WACC-NEXT: blr1024entry:1025 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()1026 store <512 x i1> %0, ptr %dst, align 641027 %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1028 %call = tail call signext i32 @testRedundantPrimeUnprimeF()1029 %add.ptr1 = getelementptr inbounds <512 x i1>, ptr %dst, i64 11030 store <512 x i1> %1, ptr %add.ptr1, align 641031 ret void1032}1033 1034declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)1035declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)1036 1037; Function Attrs: nofree nounwind1038define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {1039; CHECK-LABEL: test_ldst_1:1040; CHECK: # %bb.0: # %entry1041; CHECK-NEXT: lxv vs3, 0(r3)1042; CHECK-NEXT: lxv vs2, 16(r3)1043; CHECK-NEXT: lxv vs1, 32(r3)1044; CHECK-NEXT: lxv vs0, 48(r3)1045; CHECK-NEXT: plxvp vsp36, 8(r4), 01046; CHECK-NEXT: xxmtacc acc01047; CHECK-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 01048; CHECK-NEXT: xxmfacc acc01049; CHECK-NEXT: stxv vs0, 48(r7)1050; CHECK-NEXT: stxv vs1, 32(r7)1051; CHECK-NEXT: stxv vs2, 16(r7)1052; CHECK-NEXT: stxv vs3, 0(r7)1053; CHECK-NEXT: blr1054;1055; CHECK-BE-LABEL: test_ldst_1:1056; CHECK-BE: # %bb.0: # %entry1057; CHECK-BE-NEXT: lxv vs3, 48(r3)1058; CHECK-BE-NEXT: lxv vs2, 32(r3)1059; CHECK-BE-NEXT: lxv vs1, 16(r3)1060; CHECK-BE-NEXT: lxv vs0, 0(r3)1061; CHECK-BE-NEXT: plxvp vsp36, 8(r4), 01062; CHECK-BE-NEXT: xxmtacc acc01063; CHECK-BE-NEXT: pmxvf64gernn acc0, vsp36, v2, 0, 01064; CHECK-BE-NEXT: xxmfacc acc01065; CHECK-BE-NEXT: stxv vs1, 16(r7)1066; CHECK-BE-NEXT: stxv vs0, 0(r7)1067; CHECK-BE-NEXT: stxv vs3, 48(r7)1068; CHECK-BE-NEXT: stxv vs2, 32(r7)1069; CHECK-BE-NEXT: blr1070;1071; CHECK-WACC-LABEL: test_ldst_1:1072; CHECK-WACC: # %bb.0: # %entry1073; CHECK-WACC-NEXT: lxv v5, 0(r3)1074; CHECK-WACC-NEXT: lxv v1, 32(r3)1075; CHECK-WACC-NEXT: lxv v4, 16(r3)1076; CHECK-WACC-NEXT: lxv v0, 48(r3)1077; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01078; CHECK-WACC-NEXT: plxvp vsp36, 8(r4), 01079; CHECK-WACC-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 01080; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01081; CHECK-WACC-NEXT: stxv v4, 48(r7)1082; CHECK-WACC-NEXT: stxv v5, 32(r7)1083; CHECK-WACC-NEXT: stxv v2, 16(r7)1084; CHECK-WACC-NEXT: stxv v3, 0(r7)1085; CHECK-WACC-NEXT: blr1086;1087; CHECK-BE-WACC-LABEL: test_ldst_1:1088; CHECK-BE-WACC: # %bb.0: # %entry1089; CHECK-BE-WACC-NEXT: lxv v5, 48(r3)1090; CHECK-BE-WACC-NEXT: lxv v1, 16(r3)1091; CHECK-BE-WACC-NEXT: lxv v4, 32(r3)1092; CHECK-BE-WACC-NEXT: lxv v0, 0(r3)1093; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01094; CHECK-BE-WACC-NEXT: plxvp vsp36, 8(r4), 01095; CHECK-BE-WACC-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 01096; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01097; CHECK-BE-WACC-NEXT: stxv v5, 48(r7)1098; CHECK-BE-WACC-NEXT: stxv v4, 32(r7)1099; CHECK-BE-WACC-NEXT: stxv v3, 16(r7)1100; CHECK-BE-WACC-NEXT: stxv v2, 0(r7)1101; CHECK-BE-WACC-NEXT: blr1102entry:1103 %0 = load <512 x i1>, ptr %vqp, align 641104 %1 = getelementptr i8, ptr %vpp, i64 81105 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %1)1106 %3 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %2, <16 x i8> %vc, i32 0, i32 0)1107 store <512 x i1> %3, ptr %resp, align 641108 ret void1109}1110 1111; Function Attrs: nofree nounwind1112define void @test_ldst_2(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {1113; CHECK-LABEL: test_ldst_2:1114; CHECK: # %bb.0: # %entry1115; CHECK-NEXT: lxv vs3, 0(r3)1116; CHECK-NEXT: lxv vs2, 16(r3)1117; CHECK-NEXT: lxv vs1, 32(r3)1118; CHECK-NEXT: lxv vs0, 48(r3)1119; CHECK-NEXT: xxmtacc acc01120; CHECK-NEXT: lxvp vsp36, 0(r4)1121; CHECK-NEXT: xvf64gernp acc0, vsp36, v21122; CHECK-NEXT: xxmfacc acc01123; CHECK-NEXT: stxv vs0, 48(r7)1124; CHECK-NEXT: stxv vs1, 32(r7)1125; CHECK-NEXT: stxv vs2, 16(r7)1126; CHECK-NEXT: stxv vs3, 0(r7)1127; CHECK-NEXT: blr1128;1129; CHECK-BE-LABEL: test_ldst_2:1130; CHECK-BE: # %bb.0: # %entry1131; CHECK-BE-NEXT: lxv vs3, 48(r3)1132; CHECK-BE-NEXT: lxv vs2, 32(r3)1133; CHECK-BE-NEXT: lxv vs1, 16(r3)1134; CHECK-BE-NEXT: lxv vs0, 0(r3)1135; CHECK-BE-NEXT: xxmtacc acc01136; CHECK-BE-NEXT: lxvp vsp36, 0(r4)1137; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v21138; CHECK-BE-NEXT: xxmfacc acc01139; CHECK-BE-NEXT: stxv vs1, 16(r7)1140; CHECK-BE-NEXT: stxv vs0, 0(r7)1141; CHECK-BE-NEXT: stxv vs3, 48(r7)1142; CHECK-BE-NEXT: stxv vs2, 32(r7)1143; CHECK-BE-NEXT: blr1144;1145; CHECK-WACC-LABEL: test_ldst_2:1146; CHECK-WACC: # %bb.0: # %entry1147; CHECK-WACC-NEXT: lxv v5, 0(r3)1148; CHECK-WACC-NEXT: lxv v1, 32(r3)1149; CHECK-WACC-NEXT: lxv v4, 16(r3)1150; CHECK-WACC-NEXT: lxv v0, 48(r3)1151; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01152; CHECK-WACC-NEXT: lxvp vsp36, 0(r4)1153; CHECK-WACC-NEXT: xvf64gernp wacc0, vsp36, v21154; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01155; CHECK-WACC-NEXT: stxv v4, 48(r7)1156; CHECK-WACC-NEXT: stxv v5, 32(r7)1157; CHECK-WACC-NEXT: stxv v2, 16(r7)1158; CHECK-WACC-NEXT: stxv v3, 0(r7)1159; CHECK-WACC-NEXT: blr1160;1161; CHECK-BE-WACC-LABEL: test_ldst_2:1162; CHECK-BE-WACC: # %bb.0: # %entry1163; CHECK-BE-WACC-NEXT: lxv v5, 48(r3)1164; CHECK-BE-WACC-NEXT: lxv v1, 16(r3)1165; CHECK-BE-WACC-NEXT: lxv v4, 32(r3)1166; CHECK-BE-WACC-NEXT: lxv v0, 0(r3)1167; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01168; CHECK-BE-WACC-NEXT: lxvp vsp36, 0(r4)1169; CHECK-BE-WACC-NEXT: xvf64gernp wacc0, vsp36, v21170; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01171; CHECK-BE-WACC-NEXT: stxv v5, 48(r7)1172; CHECK-BE-WACC-NEXT: stxv v4, 32(r7)1173; CHECK-BE-WACC-NEXT: stxv v3, 16(r7)1174; CHECK-BE-WACC-NEXT: stxv v2, 0(r7)1175; CHECK-BE-WACC-NEXT: blr1176entry:1177 %0 = load <512 x i1>, ptr %vqp, align 641178 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %vpp)1179 %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)1180 store <512 x i1> %2, ptr %resp, align 641181 ret void1182}1183 1184; Function Attrs: nofree nounwind1185define void @test_ldst_3(ptr nocapture readonly %vqp, i64 %offs, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {1186; CHECK-LABEL: test_ldst_3:1187; CHECK: # %bb.0: # %entry1188; CHECK-NEXT: lxv vs3, 0(r3)1189; CHECK-NEXT: lxv vs2, 16(r3)1190; CHECK-NEXT: lxv vs1, 32(r3)1191; CHECK-NEXT: lxv vs0, 48(r3)1192; CHECK-NEXT: xxmtacc acc01193; CHECK-NEXT: lxvp vsp36, 0(r5)1194; CHECK-NEXT: xvf64gernp acc0, vsp36, v21195; CHECK-NEXT: xxmfacc acc01196; CHECK-NEXT: stxv vs0, 48(r9)1197; CHECK-NEXT: stxv vs1, 32(r9)1198; CHECK-NEXT: stxv vs2, 16(r9)1199; CHECK-NEXT: stxv vs3, 0(r9)1200; CHECK-NEXT: blr1201;1202; CHECK-BE-LABEL: test_ldst_3:1203; CHECK-BE: # %bb.0: # %entry1204; CHECK-BE-NEXT: lxv vs3, 48(r3)1205; CHECK-BE-NEXT: lxv vs2, 32(r3)1206; CHECK-BE-NEXT: lxv vs1, 16(r3)1207; CHECK-BE-NEXT: lxv vs0, 0(r3)1208; CHECK-BE-NEXT: xxmtacc acc01209; CHECK-BE-NEXT: lxvp vsp36, 0(r5)1210; CHECK-BE-NEXT: xvf64gernp acc0, vsp36, v21211; CHECK-BE-NEXT: xxmfacc acc01212; CHECK-BE-NEXT: stxv vs1, 16(r9)1213; CHECK-BE-NEXT: stxv vs0, 0(r9)1214; CHECK-BE-NEXT: stxv vs3, 48(r9)1215; CHECK-BE-NEXT: stxv vs2, 32(r9)1216; CHECK-BE-NEXT: blr1217;1218; CHECK-WACC-LABEL: test_ldst_3:1219; CHECK-WACC: # %bb.0: # %entry1220; CHECK-WACC-NEXT: lxv v5, 0(r3)1221; CHECK-WACC-NEXT: lxv v1, 32(r3)1222; CHECK-WACC-NEXT: lxv v4, 16(r3)1223; CHECK-WACC-NEXT: lxv v0, 48(r3)1224; CHECK-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01225; CHECK-WACC-NEXT: lxvp vsp36, 0(r5)1226; CHECK-WACC-NEXT: xvf64gernp wacc0, vsp36, v21227; CHECK-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01228; CHECK-WACC-NEXT: stxv v4, 48(r9)1229; CHECK-WACC-NEXT: stxv v5, 32(r9)1230; CHECK-WACC-NEXT: stxv v2, 16(r9)1231; CHECK-WACC-NEXT: stxv v3, 0(r9)1232; CHECK-WACC-NEXT: blr1233;1234; CHECK-BE-WACC-LABEL: test_ldst_3:1235; CHECK-BE-WACC: # %bb.0: # %entry1236; CHECK-BE-WACC-NEXT: lxv v5, 48(r3)1237; CHECK-BE-WACC-NEXT: lxv v1, 16(r3)1238; CHECK-BE-WACC-NEXT: lxv v4, 32(r3)1239; CHECK-BE-WACC-NEXT: lxv v0, 0(r3)1240; CHECK-BE-WACC-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01241; CHECK-BE-WACC-NEXT: lxvp vsp36, 0(r5)1242; CHECK-BE-WACC-NEXT: xvf64gernp wacc0, vsp36, v21243; CHECK-BE-WACC-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01244; CHECK-BE-WACC-NEXT: stxv v5, 48(r9)1245; CHECK-BE-WACC-NEXT: stxv v4, 32(r9)1246; CHECK-BE-WACC-NEXT: stxv v3, 16(r9)1247; CHECK-BE-WACC-NEXT: stxv v2, 0(r9)1248; CHECK-BE-WACC-NEXT: blr1249entry:1250 %0 = load <512 x i1>, ptr %vqp, align 641251 %1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %vpp)1252 %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)1253 store <512 x i1> %2, ptr %resp, align 641254 ret void1255}1256 1257declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)1258declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)1259