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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN:   -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \4; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN:   -mcpu=pwr10 -enable-subreg-liveness -ppc-asm-full-reg-names \7; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \9; RUN:   -mcpu=future -enable-subreg-liveness -ppc-asm-full-reg-names \10; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-WACC11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \12; RUN:   -mcpu=future -enable-subreg-liveness -ppc-asm-full-reg-names \13; RUN:   -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE-WACC14 15declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)16declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)17define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {18; CHECK-LABEL: intrinsics1:19; CHECK:       # %bb.0:20; CHECK-NEXT:    vmr v1, v421; CHECK-NEXT:    vmr v4, v322; CHECK-NEXT:    vmr v0, v223; CHECK-NEXT:    xxlor vs3, v5, v524; CHECK-NEXT:    ld r3, 96(r1)25; CHECK-NEXT:    xxlor vs2, v4, v426; CHECK-NEXT:    xxlor vs0, v0, v027; CHECK-NEXT:    xxlor vs1, v1, v128; CHECK-NEXT:    xxmtacc acc029; CHECK-NEXT:    xvi4ger8pp acc0, v2, v330; CHECK-NEXT:    xvf16ger2pp acc0, v2, v131; CHECK-NEXT:    pmxvf32gerpn acc0, v3, v5, 0, 032; CHECK-NEXT:    vmr v3, v233; CHECK-NEXT:    vmr v2, v534; CHECK-NEXT:    pmxvf64gernp acc0, vsp34, v0, 0, 035; CHECK-NEXT:    xxmfacc acc036; CHECK-NEXT:    stxv vs0, 48(r3)37; CHECK-NEXT:    stxv vs1, 32(r3)38; CHECK-NEXT:    stxv vs2, 16(r3)39; CHECK-NEXT:    stxv vs3, 0(r3)40; CHECK-NEXT:    blr41;42; CHECK-BE-LABEL: intrinsics1:43; CHECK-BE:       # %bb.0:44; CHECK-BE-NEXT:    vmr v1, v445; CHECK-BE-NEXT:    vmr v4, v346; CHECK-BE-NEXT:    vmr v0, v247; CHECK-BE-NEXT:    xxlor vs3, v5, v548; CHECK-BE-NEXT:    ld r3, 112(r1)49; CHECK-BE-NEXT:    xxlor vs2, v4, v450; CHECK-BE-NEXT:    xxlor vs0, v0, v051; CHECK-BE-NEXT:    xxlor vs1, v1, v152; CHECK-BE-NEXT:    xxmtacc acc053; CHECK-BE-NEXT:    xvi4ger8pp acc0, v2, v354; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v155; CHECK-BE-NEXT:    pmxvf32gerpn acc0, v3, v5, 0, 056; CHECK-BE-NEXT:    vmr v3, v257; CHECK-BE-NEXT:    vmr v2, v558; CHECK-BE-NEXT:    pmxvf64gernp acc0, vsp34, v0, 0, 059; CHECK-BE-NEXT:    xxmfacc acc060; CHECK-BE-NEXT:    stxv vs1, 16(r3)61; CHECK-BE-NEXT:    stxv vs0, 0(r3)62; CHECK-BE-NEXT:    stxv vs3, 48(r3)63; CHECK-BE-NEXT:    stxv vs2, 32(r3)64; CHECK-BE-NEXT:    blr65;66; CHECK-WACC-LABEL: intrinsics1:67; CHECK-WACC:       # %bb.0:68; CHECK-WACC-NEXT:    vmr v1, v469; CHECK-WACC-NEXT:    vmr v4, v370; CHECK-WACC-NEXT:    vmr v0, v271; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 072; CHECK-WACC-NEXT:    xvi4ger8pp wacc0, v2, v473; CHECK-WACC-NEXT:    ld r3, 96(r1)74; CHECK-WACC-NEXT:    xvf16ger2pp wacc0, v0, v175; CHECK-WACC-NEXT:    vmr v3, v276; CHECK-WACC-NEXT:    vmr v2, v577; CHECK-WACC-NEXT:    pmxvf32gerpn wacc0, v4, v5, 0, 078; CHECK-WACC-NEXT:    pmxvf64gernp wacc0, vsp34, v0, 0, 079; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 080; CHECK-WACC-NEXT:    stxv v4, 48(r3)81; CHECK-WACC-NEXT:    stxv v5, 32(r3)82; CHECK-WACC-NEXT:    stxv v2, 16(r3)83; CHECK-WACC-NEXT:    stxv v3, 0(r3)84; CHECK-WACC-NEXT:    blr85;86; CHECK-BE-WACC-LABEL: intrinsics1:87; CHECK-BE-WACC:       # %bb.0:88; CHECK-BE-WACC-NEXT:    vmr v1, v489; CHECK-BE-WACC-NEXT:    vmr v4, v390; CHECK-BE-WACC-NEXT:    vmr v0, v291; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 092; CHECK-BE-WACC-NEXT:    xvi4ger8pp wacc0, v2, v493; CHECK-BE-WACC-NEXT:    ld r3, 112(r1)94; CHECK-BE-WACC-NEXT:    xvf16ger2pp wacc0, v0, v195; CHECK-BE-WACC-NEXT:    vmr v3, v296; CHECK-BE-WACC-NEXT:    vmr v2, v597; CHECK-BE-WACC-NEXT:    pmxvf32gerpn wacc0, v4, v5, 0, 098; CHECK-BE-WACC-NEXT:    pmxvf64gernp wacc0, vsp34, v0, 0, 099; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0100; CHECK-BE-WACC-NEXT:    stxv v5, 48(r3)101; CHECK-BE-WACC-NEXT:    stxv v4, 32(r3)102; CHECK-BE-WACC-NEXT:    stxv v3, 16(r3)103; CHECK-BE-WACC-NEXT:    stxv v2, 0(r3)104; CHECK-BE-WACC-NEXT:    blr105  %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc3, <16 x i8> %vc2, <16 x i8> %vc4)106  %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)107  %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)108  %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)109  %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)110  %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)111  store <512 x i1> %6, ptr %ptr, align 64112  ret void113}114 115declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)116define void @intrinsics2(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4, ptr %ptr) {117; CHECK-LABEL: intrinsics2:118; CHECK:       # %bb.0:119; CHECK-NEXT:    lxv v2, 0(r3)120; CHECK-NEXT:    lxv v3, 0(r4)121; CHECK-NEXT:    xxlor vs0, v2, v2122; CHECK-NEXT:    lxv v4, 0(r5)123; CHECK-NEXT:    lxv v5, 0(r6)124; CHECK-NEXT:    xxlor vs2, v4, v4125; CHECK-NEXT:    xxlor vs3, v5, v5126; CHECK-NEXT:    xxlor vs1, v3, v3127; CHECK-NEXT:    vmr v1, v2128; CHECK-NEXT:    vmr v0, v5129; CHECK-NEXT:    xxmtacc acc0130; CHECK-NEXT:    xvi8ger4pp acc0, v2, v3131; CHECK-NEXT:    xvf16ger2pn acc0, v2, v4132; CHECK-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0133; CHECK-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0134; CHECK-NEXT:    xxmfacc acc0135; CHECK-NEXT:    stxv vs3, 0(r3)136; CHECK-NEXT:    stxv vs2, 0(r4)137; CHECK-NEXT:    stxv vs1, 0(r5)138; CHECK-NEXT:    stxv vs0, 0(r6)139; CHECK-NEXT:    blr140;141; CHECK-BE-LABEL: intrinsics2:142; CHECK-BE:       # %bb.0:143; CHECK-BE-NEXT:    lxv v2, 0(r3)144; CHECK-BE-NEXT:    lxv v3, 0(r4)145; CHECK-BE-NEXT:    xxlor vs0, v2, v2146; CHECK-BE-NEXT:    lxv v4, 0(r5)147; CHECK-BE-NEXT:    lxv v5, 0(r6)148; CHECK-BE-NEXT:    xxlor vs2, v4, v4149; CHECK-BE-NEXT:    xxlor vs3, v5, v5150; CHECK-BE-NEXT:    xxlor vs1, v3, v3151; CHECK-BE-NEXT:    vmr v1, v2152; CHECK-BE-NEXT:    vmr v0, v5153; CHECK-BE-NEXT:    xxmtacc acc0154; CHECK-BE-NEXT:    xvi8ger4pp acc0, v2, v3155; CHECK-BE-NEXT:    xvf16ger2pn acc0, v2, v4156; CHECK-BE-NEXT:    pmxvf32gernn acc0, v3, v5, 0, 0157; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp32, v2, 0, 0158; CHECK-BE-NEXT:    xxmfacc acc0159; CHECK-BE-NEXT:    stxv vs0, 0(r3)160; CHECK-BE-NEXT:    stxv vs1, 0(r4)161; CHECK-BE-NEXT:    stxv vs2, 0(r5)162; CHECK-BE-NEXT:    stxv vs3, 0(r6)163; CHECK-BE-NEXT:    blr164;165; CHECK-WACC-LABEL: intrinsics2:166; CHECK-WACC:       # %bb.0:167; CHECK-WACC-NEXT:    lxv v2, 0(r3)168; CHECK-WACC-NEXT:    lxv v4, 0(r5)169; CHECK-WACC-NEXT:    lxv v3, 0(r4)170; CHECK-WACC-NEXT:    lxv v5, 0(r6)171; CHECK-WACC-NEXT:    vmr v1, v2172; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp34, vsp36, 0173; CHECK-WACC-NEXT:    xvi8ger4pp wacc0, v2, v3174; CHECK-WACC-NEXT:    xvf16ger2pn wacc0, v2, v4175; CHECK-WACC-NEXT:    vmr v0, v5176; CHECK-WACC-NEXT:    pmxvf32gernn wacc0, v3, v5, 0, 0177; CHECK-WACC-NEXT:    pmxvf64gernn wacc0, vsp32, v2, 0, 0178; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0179; CHECK-WACC-NEXT:    stxv v5, 0(r3)180; CHECK-WACC-NEXT:    stxv v4, 0(r4)181; CHECK-WACC-NEXT:    stxv v3, 0(r5)182; CHECK-WACC-NEXT:    stxv v2, 0(r6)183; CHECK-WACC-NEXT:    blr184;185; CHECK-BE-WACC-LABEL: intrinsics2:186; CHECK-BE-WACC:       # %bb.0:187; CHECK-BE-WACC-NEXT:    lxv v2, 0(r3)188; CHECK-BE-WACC-NEXT:    lxv v4, 0(r5)189; CHECK-BE-WACC-NEXT:    lxv v3, 0(r4)190; CHECK-BE-WACC-NEXT:    lxv v5, 0(r6)191; CHECK-BE-WACC-NEXT:    vmr v1, v2192; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp34, vsp36, 0193; CHECK-BE-WACC-NEXT:    xvi8ger4pp wacc0, v2, v3194; CHECK-BE-WACC-NEXT:    xvf16ger2pn wacc0, v2, v4195; CHECK-BE-WACC-NEXT:    vmr v0, v5196; CHECK-BE-WACC-NEXT:    pmxvf32gernn wacc0, v3, v5, 0, 0197; CHECK-BE-WACC-NEXT:    pmxvf64gernn wacc0, vsp32, v2, 0, 0198; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0199; CHECK-BE-WACC-NEXT:    stxv v2, 0(r3)200; CHECK-BE-WACC-NEXT:    stxv v3, 0(r4)201; CHECK-BE-WACC-NEXT:    stxv v4, 0(r5)202; CHECK-BE-WACC-NEXT:    stxv v5, 0(r6)203; CHECK-BE-WACC-NEXT:    blr204  %vc1 = load <16 x i8>, ptr %ptr1, align 16205  %vc2 = load <16 x i8>, ptr %ptr2, align 16206  %vc3 = load <16 x i8>, ptr %ptr3, align 16207  %vc4 = load <16 x i8>, ptr %ptr4, align 16208  %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)209  %2 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc2)210  %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)211  %4 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %3, <16 x i8> %vc2, <16 x i8> %vc4, i32 0, i32 0)212  %5 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc4, <16 x i8> %vc1)213  %6 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %4, <256 x i1> %5, <16 x i8> %vc1, i32 0, i32 0)214  %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %6)215  %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 0216  %9 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 1217  %10 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 2218  %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %7, 3219  store <16 x i8> %8, ptr %ptr1, align 16220  store <16 x i8> %9, ptr %ptr2, align 16221  store <16 x i8> %10, ptr %ptr3, align 16222  store <16 x i8> %11, ptr %ptr4, align 16223  ret void224}225 226define void @test1(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {227; CHECK-LABEL: test1:228; CHECK:       # %bb.0: # %entry229; CHECK-NEXT:    xvi4ger8 acc0, v2, v2230; CHECK-NEXT:    xxmfacc acc0231; CHECK-NEXT:    stxv vs0, 48(r7)232; CHECK-NEXT:    stxv vs1, 32(r7)233; CHECK-NEXT:    stxv vs2, 16(r7)234; CHECK-NEXT:    stxv vs3, 0(r7)235; CHECK-NEXT:    blr236;237; CHECK-BE-LABEL: test1:238; CHECK-BE:       # %bb.0: # %entry239; CHECK-BE-NEXT:    xvi4ger8 acc0, v2, v2240; CHECK-BE-NEXT:    xxmfacc acc0241; CHECK-BE-NEXT:    stxv vs1, 16(r7)242; CHECK-BE-NEXT:    stxv vs0, 0(r7)243; CHECK-BE-NEXT:    stxv vs3, 48(r7)244; CHECK-BE-NEXT:    stxv vs2, 32(r7)245; CHECK-BE-NEXT:    blr246;247; CHECK-WACC-LABEL: test1:248; CHECK-WACC:       # %bb.0: # %entry249; CHECK-WACC-NEXT:    xvi4ger8 wacc0, v2, v2250; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0251; CHECK-WACC-NEXT:    stxv v4, 48(r7)252; CHECK-WACC-NEXT:    stxv v5, 32(r7)253; CHECK-WACC-NEXT:    stxv v2, 16(r7)254; CHECK-WACC-NEXT:    stxv v3, 0(r7)255; CHECK-WACC-NEXT:    blr256;257; CHECK-BE-WACC-LABEL: test1:258; CHECK-BE-WACC:       # %bb.0: # %entry259; CHECK-BE-WACC-NEXT:    xvi4ger8 wacc0, v2, v2260; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0261; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)262; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)263; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)264; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)265; CHECK-BE-WACC-NEXT:    blr266entry:267  %0 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8> %vc, <16 x i8> %vc)268  store <512 x i1> %0, ptr %resp, align 64269  ret void270}271 272 273declare <512 x i1> @llvm.ppc.mma.xvi4ger8(<16 x i8>, <16 x i8>)274 275define void @test2(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {276; CHECK-LABEL: test2:277; CHECK:       # %bb.0: # %entry278; CHECK-NEXT:    lxv vs3, 0(r3)279; CHECK-NEXT:    lxv vs2, 16(r3)280; CHECK-NEXT:    lxv vs1, 32(r3)281; CHECK-NEXT:    lxv vs0, 48(r3)282; CHECK-NEXT:    xxmtacc acc0283; CHECK-NEXT:    xvi4ger8pp acc0, v2, v2284; CHECK-NEXT:    xxmfacc acc0285; CHECK-NEXT:    stxv vs0, 48(r7)286; CHECK-NEXT:    stxv vs1, 32(r7)287; CHECK-NEXT:    stxv vs2, 16(r7)288; CHECK-NEXT:    stxv vs3, 0(r7)289; CHECK-NEXT:    blr290;291; CHECK-BE-LABEL: test2:292; CHECK-BE:       # %bb.0: # %entry293; CHECK-BE-NEXT:    lxv vs3, 48(r3)294; CHECK-BE-NEXT:    lxv vs2, 32(r3)295; CHECK-BE-NEXT:    lxv vs1, 16(r3)296; CHECK-BE-NEXT:    lxv vs0, 0(r3)297; CHECK-BE-NEXT:    xxmtacc acc0298; CHECK-BE-NEXT:    xvi4ger8pp acc0, v2, v2299; CHECK-BE-NEXT:    xxmfacc acc0300; CHECK-BE-NEXT:    stxv vs1, 16(r7)301; CHECK-BE-NEXT:    stxv vs0, 0(r7)302; CHECK-BE-NEXT:    stxv vs3, 48(r7)303; CHECK-BE-NEXT:    stxv vs2, 32(r7)304; CHECK-BE-NEXT:    blr305;306; CHECK-WACC-LABEL: test2:307; CHECK-WACC:       # %bb.0: # %entry308; CHECK-WACC-NEXT:    lxv v5, 0(r3)309; CHECK-WACC-NEXT:    lxv v1, 32(r3)310; CHECK-WACC-NEXT:    lxv v4, 16(r3)311; CHECK-WACC-NEXT:    lxv v0, 48(r3)312; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0313; CHECK-WACC-NEXT:    xvi4ger8pp wacc0, v2, v2314; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0315; CHECK-WACC-NEXT:    stxv v4, 48(r7)316; CHECK-WACC-NEXT:    stxv v5, 32(r7)317; CHECK-WACC-NEXT:    stxv v2, 16(r7)318; CHECK-WACC-NEXT:    stxv v3, 0(r7)319; CHECK-WACC-NEXT:    blr320;321; CHECK-BE-WACC-LABEL: test2:322; CHECK-BE-WACC:       # %bb.0: # %entry323; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)324; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)325; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)326; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)327; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0328; CHECK-BE-WACC-NEXT:    xvi4ger8pp wacc0, v2, v2329; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0330; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)331; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)332; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)333; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)334; CHECK-BE-WACC-NEXT:    blr335entry:336  %0 = load <512 x i1>, ptr %vqp, align 64337  %1 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)338  store <512 x i1> %1, ptr %resp, align 64339  ret void340}341 342 343declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)344 345define void @test3(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {346; CHECK-LABEL: test3:347; CHECK:       # %bb.0: # %entry348; CHECK-NEXT:    pmxvi4ger8 acc0, v2, v2, 0, 0, 0349; CHECK-NEXT:    xxmfacc acc0350; CHECK-NEXT:    stxv vs0, 48(r7)351; CHECK-NEXT:    stxv vs1, 32(r7)352; CHECK-NEXT:    stxv vs2, 16(r7)353; CHECK-NEXT:    stxv vs3, 0(r7)354; CHECK-NEXT:    blr355;356; CHECK-BE-LABEL: test3:357; CHECK-BE:       # %bb.0: # %entry358; CHECK-BE-NEXT:    pmxvi4ger8 acc0, v2, v2, 0, 0, 0359; CHECK-BE-NEXT:    xxmfacc acc0360; CHECK-BE-NEXT:    stxv vs1, 16(r7)361; CHECK-BE-NEXT:    stxv vs0, 0(r7)362; CHECK-BE-NEXT:    stxv vs3, 48(r7)363; CHECK-BE-NEXT:    stxv vs2, 32(r7)364; CHECK-BE-NEXT:    blr365;366; CHECK-WACC-LABEL: test3:367; CHECK-WACC:       # %bb.0: # %entry368; CHECK-WACC-NEXT:    pmxvi4ger8 wacc0, v2, v2, 0, 0, 0369; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0370; CHECK-WACC-NEXT:    stxv v4, 48(r7)371; CHECK-WACC-NEXT:    stxv v5, 32(r7)372; CHECK-WACC-NEXT:    stxv v2, 16(r7)373; CHECK-WACC-NEXT:    stxv v3, 0(r7)374; CHECK-WACC-NEXT:    blr375;376; CHECK-BE-WACC-LABEL: test3:377; CHECK-BE-WACC:       # %bb.0: # %entry378; CHECK-BE-WACC-NEXT:    pmxvi4ger8 wacc0, v2, v2, 0, 0, 0379; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0380; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)381; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)382; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)383; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)384; CHECK-BE-WACC-NEXT:    blr385entry:386  %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)387  store <512 x i1> %0, ptr %resp, align 64388  ret void389}390 391 392declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8(<16 x i8>, <16 x i8>, i32, i32, i32)393 394define void @test4(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {395; CHECK-LABEL: test4:396; CHECK:       # %bb.0: # %entry397; CHECK-NEXT:    lxv vs3, 0(r3)398; CHECK-NEXT:    lxv vs2, 16(r3)399; CHECK-NEXT:    lxv vs1, 32(r3)400; CHECK-NEXT:    lxv vs0, 48(r3)401; CHECK-NEXT:    xxmtacc acc0402; CHECK-NEXT:    pmxvi4ger8pp acc0, v2, v2, 0, 0, 0403; CHECK-NEXT:    xxmfacc acc0404; CHECK-NEXT:    stxv vs0, 48(r7)405; CHECK-NEXT:    stxv vs1, 32(r7)406; CHECK-NEXT:    stxv vs2, 16(r7)407; CHECK-NEXT:    stxv vs3, 0(r7)408; CHECK-NEXT:    blr409;410; CHECK-BE-LABEL: test4:411; CHECK-BE:       # %bb.0: # %entry412; CHECK-BE-NEXT:    lxv vs3, 48(r3)413; CHECK-BE-NEXT:    lxv vs2, 32(r3)414; CHECK-BE-NEXT:    lxv vs1, 16(r3)415; CHECK-BE-NEXT:    lxv vs0, 0(r3)416; CHECK-BE-NEXT:    xxmtacc acc0417; CHECK-BE-NEXT:    pmxvi4ger8pp acc0, v2, v2, 0, 0, 0418; CHECK-BE-NEXT:    xxmfacc acc0419; CHECK-BE-NEXT:    stxv vs1, 16(r7)420; CHECK-BE-NEXT:    stxv vs0, 0(r7)421; CHECK-BE-NEXT:    stxv vs3, 48(r7)422; CHECK-BE-NEXT:    stxv vs2, 32(r7)423; CHECK-BE-NEXT:    blr424;425; CHECK-WACC-LABEL: test4:426; CHECK-WACC:       # %bb.0: # %entry427; CHECK-WACC-NEXT:    lxv v5, 0(r3)428; CHECK-WACC-NEXT:    lxv v1, 32(r3)429; CHECK-WACC-NEXT:    lxv v4, 16(r3)430; CHECK-WACC-NEXT:    lxv v0, 48(r3)431; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0432; CHECK-WACC-NEXT:    pmxvi4ger8pp wacc0, v2, v2, 0, 0, 0433; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0434; CHECK-WACC-NEXT:    stxv v4, 48(r7)435; CHECK-WACC-NEXT:    stxv v5, 32(r7)436; CHECK-WACC-NEXT:    stxv v2, 16(r7)437; CHECK-WACC-NEXT:    stxv v3, 0(r7)438; CHECK-WACC-NEXT:    blr439;440; CHECK-BE-WACC-LABEL: test4:441; CHECK-BE-WACC:       # %bb.0: # %entry442; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)443; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)444; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)445; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)446; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0447; CHECK-BE-WACC-NEXT:    pmxvi4ger8pp wacc0, v2, v2, 0, 0, 0448; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0449; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)450; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)451; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)452; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)453; CHECK-BE-WACC-NEXT:    blr454entry:455  %0 = load <512 x i1>, ptr %vqp, align 64456  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)457  store <512 x i1> %1, ptr %resp, align 64458  ret void459}460 461 462declare <512 x i1> @llvm.ppc.mma.pmxvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)463 464define void @test5(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {465; CHECK-LABEL: test5:466; CHECK:       # %bb.0: # %entry467; CHECK-NEXT:    xvi8ger4 acc0, v2, v2468; CHECK-NEXT:    xxmfacc acc0469; CHECK-NEXT:    stxv vs0, 48(r7)470; CHECK-NEXT:    stxv vs1, 32(r7)471; CHECK-NEXT:    stxv vs2, 16(r7)472; CHECK-NEXT:    stxv vs3, 0(r7)473; CHECK-NEXT:    blr474;475; CHECK-BE-LABEL: test5:476; CHECK-BE:       # %bb.0: # %entry477; CHECK-BE-NEXT:    xvi8ger4 acc0, v2, v2478; CHECK-BE-NEXT:    xxmfacc acc0479; CHECK-BE-NEXT:    stxv vs1, 16(r7)480; CHECK-BE-NEXT:    stxv vs0, 0(r7)481; CHECK-BE-NEXT:    stxv vs3, 48(r7)482; CHECK-BE-NEXT:    stxv vs2, 32(r7)483; CHECK-BE-NEXT:    blr484;485; CHECK-WACC-LABEL: test5:486; CHECK-WACC:       # %bb.0: # %entry487; CHECK-WACC-NEXT:    xvi8ger4 wacc0, v2, v2488; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0489; CHECK-WACC-NEXT:    stxv v4, 48(r7)490; CHECK-WACC-NEXT:    stxv v5, 32(r7)491; CHECK-WACC-NEXT:    stxv v2, 16(r7)492; CHECK-WACC-NEXT:    stxv v3, 0(r7)493; CHECK-WACC-NEXT:    blr494;495; CHECK-BE-WACC-LABEL: test5:496; CHECK-BE-WACC:       # %bb.0: # %entry497; CHECK-BE-WACC-NEXT:    xvi8ger4 wacc0, v2, v2498; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0499; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)500; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)501; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)502; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)503; CHECK-BE-WACC-NEXT:    blr504entry:505  %0 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8> %vc, <16 x i8> %vc)506  store <512 x i1> %0, ptr %resp, align 64507  ret void508}509 510 511declare <512 x i1> @llvm.ppc.mma.xvi8ger4(<16 x i8>, <16 x i8>)512 513define void @test6(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {514; CHECK-LABEL: test6:515; CHECK:       # %bb.0: # %entry516; CHECK-NEXT:    lxv vs3, 0(r3)517; CHECK-NEXT:    lxv vs2, 16(r3)518; CHECK-NEXT:    lxv vs1, 32(r3)519; CHECK-NEXT:    lxv vs0, 48(r3)520; CHECK-NEXT:    xxmtacc acc0521; CHECK-NEXT:    xvi8ger4pp acc0, v2, v2522; CHECK-NEXT:    xxmfacc acc0523; CHECK-NEXT:    stxv vs0, 48(r7)524; CHECK-NEXT:    stxv vs1, 32(r7)525; CHECK-NEXT:    stxv vs2, 16(r7)526; CHECK-NEXT:    stxv vs3, 0(r7)527; CHECK-NEXT:    blr528;529; CHECK-BE-LABEL: test6:530; CHECK-BE:       # %bb.0: # %entry531; CHECK-BE-NEXT:    lxv vs3, 48(r3)532; CHECK-BE-NEXT:    lxv vs2, 32(r3)533; CHECK-BE-NEXT:    lxv vs1, 16(r3)534; CHECK-BE-NEXT:    lxv vs0, 0(r3)535; CHECK-BE-NEXT:    xxmtacc acc0536; CHECK-BE-NEXT:    xvi8ger4pp acc0, v2, v2537; CHECK-BE-NEXT:    xxmfacc acc0538; CHECK-BE-NEXT:    stxv vs1, 16(r7)539; CHECK-BE-NEXT:    stxv vs0, 0(r7)540; CHECK-BE-NEXT:    stxv vs3, 48(r7)541; CHECK-BE-NEXT:    stxv vs2, 32(r7)542; CHECK-BE-NEXT:    blr543;544; CHECK-WACC-LABEL: test6:545; CHECK-WACC:       # %bb.0: # %entry546; CHECK-WACC-NEXT:    lxv v5, 0(r3)547; CHECK-WACC-NEXT:    lxv v1, 32(r3)548; CHECK-WACC-NEXT:    lxv v4, 16(r3)549; CHECK-WACC-NEXT:    lxv v0, 48(r3)550; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0551; CHECK-WACC-NEXT:    xvi8ger4pp wacc0, v2, v2552; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0553; CHECK-WACC-NEXT:    stxv v4, 48(r7)554; CHECK-WACC-NEXT:    stxv v5, 32(r7)555; CHECK-WACC-NEXT:    stxv v2, 16(r7)556; CHECK-WACC-NEXT:    stxv v3, 0(r7)557; CHECK-WACC-NEXT:    blr558;559; CHECK-BE-WACC-LABEL: test6:560; CHECK-BE-WACC:       # %bb.0: # %entry561; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)562; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)563; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)564; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)565; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0566; CHECK-BE-WACC-NEXT:    xvi8ger4pp wacc0, v2, v2567; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0568; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)569; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)570; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)571; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)572; CHECK-BE-WACC-NEXT:    blr573entry:574  %0 = load <512 x i1>, ptr %vqp, align 64575  %1 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)576  store <512 x i1> %1, ptr %resp, align 64577  ret void578}579 580 581declare <512 x i1> @llvm.ppc.mma.xvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>)582 583define void @test7(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {584; CHECK-LABEL: test7:585; CHECK:       # %bb.0: # %entry586; CHECK-NEXT:    pmxvi8ger4 acc0, v2, v2, 0, 0, 0587; CHECK-NEXT:    xxmfacc acc0588; CHECK-NEXT:    stxv vs0, 48(r7)589; CHECK-NEXT:    stxv vs1, 32(r7)590; CHECK-NEXT:    stxv vs2, 16(r7)591; CHECK-NEXT:    stxv vs3, 0(r7)592; CHECK-NEXT:    blr593;594; CHECK-BE-LABEL: test7:595; CHECK-BE:       # %bb.0: # %entry596; CHECK-BE-NEXT:    pmxvi8ger4 acc0, v2, v2, 0, 0, 0597; CHECK-BE-NEXT:    xxmfacc acc0598; CHECK-BE-NEXT:    stxv vs1, 16(r7)599; CHECK-BE-NEXT:    stxv vs0, 0(r7)600; CHECK-BE-NEXT:    stxv vs3, 48(r7)601; CHECK-BE-NEXT:    stxv vs2, 32(r7)602; CHECK-BE-NEXT:    blr603;604; CHECK-WACC-LABEL: test7:605; CHECK-WACC:       # %bb.0: # %entry606; CHECK-WACC-NEXT:    pmxvi8ger4 wacc0, v2, v2, 0, 0, 0607; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0608; CHECK-WACC-NEXT:    stxv v4, 48(r7)609; CHECK-WACC-NEXT:    stxv v5, 32(r7)610; CHECK-WACC-NEXT:    stxv v2, 16(r7)611; CHECK-WACC-NEXT:    stxv v3, 0(r7)612; CHECK-WACC-NEXT:    blr613;614; CHECK-BE-WACC-LABEL: test7:615; CHECK-BE-WACC:       # %bb.0: # %entry616; CHECK-BE-WACC-NEXT:    pmxvi8ger4 wacc0, v2, v2, 0, 0, 0617; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0618; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)619; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)620; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)621; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)622; CHECK-BE-WACC-NEXT:    blr623entry:624  %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)625  store <512 x i1> %0, ptr %resp, align 64626  ret void627}628 629 630declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4(<16 x i8>, <16 x i8>, i32, i32, i32)631 632define void @test8(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {633; CHECK-LABEL: test8:634; CHECK:       # %bb.0: # %entry635; CHECK-NEXT:    lxv vs3, 0(r3)636; CHECK-NEXT:    lxv vs2, 16(r3)637; CHECK-NEXT:    lxv vs1, 32(r3)638; CHECK-NEXT:    lxv vs0, 48(r3)639; CHECK-NEXT:    xxmtacc acc0640; CHECK-NEXT:    pmxvi8ger4pp acc0, v2, v2, 0, 0, 0641; CHECK-NEXT:    xxmfacc acc0642; CHECK-NEXT:    stxv vs0, 48(r7)643; CHECK-NEXT:    stxv vs1, 32(r7)644; CHECK-NEXT:    stxv vs2, 16(r7)645; CHECK-NEXT:    stxv vs3, 0(r7)646; CHECK-NEXT:    blr647;648; CHECK-BE-LABEL: test8:649; CHECK-BE:       # %bb.0: # %entry650; CHECK-BE-NEXT:    lxv vs3, 48(r3)651; CHECK-BE-NEXT:    lxv vs2, 32(r3)652; CHECK-BE-NEXT:    lxv vs1, 16(r3)653; CHECK-BE-NEXT:    lxv vs0, 0(r3)654; CHECK-BE-NEXT:    xxmtacc acc0655; CHECK-BE-NEXT:    pmxvi8ger4pp acc0, v2, v2, 0, 0, 0656; CHECK-BE-NEXT:    xxmfacc acc0657; CHECK-BE-NEXT:    stxv vs1, 16(r7)658; CHECK-BE-NEXT:    stxv vs0, 0(r7)659; CHECK-BE-NEXT:    stxv vs3, 48(r7)660; CHECK-BE-NEXT:    stxv vs2, 32(r7)661; CHECK-BE-NEXT:    blr662;663; CHECK-WACC-LABEL: test8:664; CHECK-WACC:       # %bb.0: # %entry665; CHECK-WACC-NEXT:    lxv v5, 0(r3)666; CHECK-WACC-NEXT:    lxv v1, 32(r3)667; CHECK-WACC-NEXT:    lxv v4, 16(r3)668; CHECK-WACC-NEXT:    lxv v0, 48(r3)669; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0670; CHECK-WACC-NEXT:    pmxvi8ger4pp wacc0, v2, v2, 0, 0, 0671; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0672; CHECK-WACC-NEXT:    stxv v4, 48(r7)673; CHECK-WACC-NEXT:    stxv v5, 32(r7)674; CHECK-WACC-NEXT:    stxv v2, 16(r7)675; CHECK-WACC-NEXT:    stxv v3, 0(r7)676; CHECK-WACC-NEXT:    blr677;678; CHECK-BE-WACC-LABEL: test8:679; CHECK-BE-WACC:       # %bb.0: # %entry680; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)681; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)682; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)683; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)684; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0685; CHECK-BE-WACC-NEXT:    pmxvi8ger4pp wacc0, v2, v2, 0, 0, 0686; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0687; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)688; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)689; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)690; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)691; CHECK-BE-WACC-NEXT:    blr692entry:693  %0 = load <512 x i1>, ptr %vqp, align 64694  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)695  store <512 x i1> %1, ptr %resp, align 64696  ret void697}698 699 700declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)701 702define void @test9(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {703; CHECK-LABEL: test9:704; CHECK:       # %bb.0: # %entry705; CHECK-NEXT:    xvi16ger2s acc0, v2, v2706; CHECK-NEXT:    xxmfacc acc0707; CHECK-NEXT:    stxv vs0, 48(r7)708; CHECK-NEXT:    stxv vs1, 32(r7)709; CHECK-NEXT:    stxv vs2, 16(r7)710; CHECK-NEXT:    stxv vs3, 0(r7)711; CHECK-NEXT:    blr712;713; CHECK-BE-LABEL: test9:714; CHECK-BE:       # %bb.0: # %entry715; CHECK-BE-NEXT:    xvi16ger2s acc0, v2, v2716; CHECK-BE-NEXT:    xxmfacc acc0717; CHECK-BE-NEXT:    stxv vs1, 16(r7)718; CHECK-BE-NEXT:    stxv vs0, 0(r7)719; CHECK-BE-NEXT:    stxv vs3, 48(r7)720; CHECK-BE-NEXT:    stxv vs2, 32(r7)721; CHECK-BE-NEXT:    blr722;723; CHECK-WACC-LABEL: test9:724; CHECK-WACC:       # %bb.0: # %entry725; CHECK-WACC-NEXT:    xvi16ger2s wacc0, v2, v2726; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0727; CHECK-WACC-NEXT:    stxv v4, 48(r7)728; CHECK-WACC-NEXT:    stxv v5, 32(r7)729; CHECK-WACC-NEXT:    stxv v2, 16(r7)730; CHECK-WACC-NEXT:    stxv v3, 0(r7)731; CHECK-WACC-NEXT:    blr732;733; CHECK-BE-WACC-LABEL: test9:734; CHECK-BE-WACC:       # %bb.0: # %entry735; CHECK-BE-WACC-NEXT:    xvi16ger2s wacc0, v2, v2736; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0737; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)738; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)739; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)740; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)741; CHECK-BE-WACC-NEXT:    blr742entry:743  %0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8> %vc, <16 x i8> %vc)744  store <512 x i1> %0, ptr %resp, align 64745  ret void746}747 748 749declare <512 x i1> @llvm.ppc.mma.xvi16ger2s(<16 x i8>, <16 x i8>)750 751define void @test10(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {752; CHECK-LABEL: test10:753; CHECK:       # %bb.0: # %entry754; CHECK-NEXT:    lxv vs3, 0(r3)755; CHECK-NEXT:    lxv vs2, 16(r3)756; CHECK-NEXT:    lxv vs1, 32(r3)757; CHECK-NEXT:    lxv vs0, 48(r3)758; CHECK-NEXT:    xxmtacc acc0759; CHECK-NEXT:    xvi16ger2spp acc0, v2, v2760; CHECK-NEXT:    xxmfacc acc0761; CHECK-NEXT:    stxv vs0, 48(r7)762; CHECK-NEXT:    stxv vs1, 32(r7)763; CHECK-NEXT:    stxv vs2, 16(r7)764; CHECK-NEXT:    stxv vs3, 0(r7)765; CHECK-NEXT:    blr766;767; CHECK-BE-LABEL: test10:768; CHECK-BE:       # %bb.0: # %entry769; CHECK-BE-NEXT:    lxv vs3, 48(r3)770; CHECK-BE-NEXT:    lxv vs2, 32(r3)771; CHECK-BE-NEXT:    lxv vs1, 16(r3)772; CHECK-BE-NEXT:    lxv vs0, 0(r3)773; CHECK-BE-NEXT:    xxmtacc acc0774; CHECK-BE-NEXT:    xvi16ger2spp acc0, v2, v2775; CHECK-BE-NEXT:    xxmfacc acc0776; CHECK-BE-NEXT:    stxv vs1, 16(r7)777; CHECK-BE-NEXT:    stxv vs0, 0(r7)778; CHECK-BE-NEXT:    stxv vs3, 48(r7)779; CHECK-BE-NEXT:    stxv vs2, 32(r7)780; CHECK-BE-NEXT:    blr781;782; CHECK-WACC-LABEL: test10:783; CHECK-WACC:       # %bb.0: # %entry784; CHECK-WACC-NEXT:    lxv v5, 0(r3)785; CHECK-WACC-NEXT:    lxv v1, 32(r3)786; CHECK-WACC-NEXT:    lxv v4, 16(r3)787; CHECK-WACC-NEXT:    lxv v0, 48(r3)788; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0789; CHECK-WACC-NEXT:    xvi16ger2spp wacc0, v2, v2790; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0791; CHECK-WACC-NEXT:    stxv v4, 48(r7)792; CHECK-WACC-NEXT:    stxv v5, 32(r7)793; CHECK-WACC-NEXT:    stxv v2, 16(r7)794; CHECK-WACC-NEXT:    stxv v3, 0(r7)795; CHECK-WACC-NEXT:    blr796;797; CHECK-BE-WACC-LABEL: test10:798; CHECK-BE-WACC:       # %bb.0: # %entry799; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)800; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)801; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)802; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)803; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0804; CHECK-BE-WACC-NEXT:    xvi16ger2spp wacc0, v2, v2805; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0806; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)807; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)808; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)809; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)810; CHECK-BE-WACC-NEXT:    blr811entry:812  %0 = load <512 x i1>, ptr %vqp, align 64813  %1 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)814  store <512 x i1> %1, ptr %resp, align 64815  ret void816}817 818 819declare <512 x i1> @llvm.ppc.mma.xvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>)820 821define void @test11(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {822; CHECK-LABEL: test11:823; CHECK:       # %bb.0: # %entry824; CHECK-NEXT:    pmxvi16ger2s acc0, v2, v2, 0, 0, 0825; CHECK-NEXT:    xxmfacc acc0826; CHECK-NEXT:    stxv vs0, 48(r7)827; CHECK-NEXT:    stxv vs1, 32(r7)828; CHECK-NEXT:    stxv vs2, 16(r7)829; CHECK-NEXT:    stxv vs3, 0(r7)830; CHECK-NEXT:    blr831;832; CHECK-BE-LABEL: test11:833; CHECK-BE:       # %bb.0: # %entry834; CHECK-BE-NEXT:    pmxvi16ger2s acc0, v2, v2, 0, 0, 0835; CHECK-BE-NEXT:    xxmfacc acc0836; CHECK-BE-NEXT:    stxv vs1, 16(r7)837; CHECK-BE-NEXT:    stxv vs0, 0(r7)838; CHECK-BE-NEXT:    stxv vs3, 48(r7)839; CHECK-BE-NEXT:    stxv vs2, 32(r7)840; CHECK-BE-NEXT:    blr841;842; CHECK-WACC-LABEL: test11:843; CHECK-WACC:       # %bb.0: # %entry844; CHECK-WACC-NEXT:    pmxvi16ger2s wacc0, v2, v2, 0, 0, 0845; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0846; CHECK-WACC-NEXT:    stxv v4, 48(r7)847; CHECK-WACC-NEXT:    stxv v5, 32(r7)848; CHECK-WACC-NEXT:    stxv v2, 16(r7)849; CHECK-WACC-NEXT:    stxv v3, 0(r7)850; CHECK-WACC-NEXT:    blr851;852; CHECK-BE-WACC-LABEL: test11:853; CHECK-BE-WACC:       # %bb.0: # %entry854; CHECK-BE-WACC-NEXT:    pmxvi16ger2s wacc0, v2, v2, 0, 0, 0855; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0856; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)857; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)858; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)859; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)860; CHECK-BE-WACC-NEXT:    blr861entry:862  %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)863  store <512 x i1> %0, ptr %resp, align 64864  ret void865}866 867 868declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2s(<16 x i8>, <16 x i8>, i32, i32, i32)869 870define void @test12(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {871; CHECK-LABEL: test12:872; CHECK:       # %bb.0: # %entry873; CHECK-NEXT:    lxv vs3, 0(r3)874; CHECK-NEXT:    lxv vs2, 16(r3)875; CHECK-NEXT:    lxv vs1, 32(r3)876; CHECK-NEXT:    lxv vs0, 48(r3)877; CHECK-NEXT:    xxmtacc acc0878; CHECK-NEXT:    pmxvi16ger2spp acc0, v2, v2, 0, 0, 0879; CHECK-NEXT:    xxmfacc acc0880; CHECK-NEXT:    stxv vs0, 48(r7)881; CHECK-NEXT:    stxv vs1, 32(r7)882; CHECK-NEXT:    stxv vs2, 16(r7)883; CHECK-NEXT:    stxv vs3, 0(r7)884; CHECK-NEXT:    blr885;886; CHECK-BE-LABEL: test12:887; CHECK-BE:       # %bb.0: # %entry888; CHECK-BE-NEXT:    lxv vs3, 48(r3)889; CHECK-BE-NEXT:    lxv vs2, 32(r3)890; CHECK-BE-NEXT:    lxv vs1, 16(r3)891; CHECK-BE-NEXT:    lxv vs0, 0(r3)892; CHECK-BE-NEXT:    xxmtacc acc0893; CHECK-BE-NEXT:    pmxvi16ger2spp acc0, v2, v2, 0, 0, 0894; CHECK-BE-NEXT:    xxmfacc acc0895; CHECK-BE-NEXT:    stxv vs1, 16(r7)896; CHECK-BE-NEXT:    stxv vs0, 0(r7)897; CHECK-BE-NEXT:    stxv vs3, 48(r7)898; CHECK-BE-NEXT:    stxv vs2, 32(r7)899; CHECK-BE-NEXT:    blr900;901; CHECK-WACC-LABEL: test12:902; CHECK-WACC:       # %bb.0: # %entry903; CHECK-WACC-NEXT:    lxv v5, 0(r3)904; CHECK-WACC-NEXT:    lxv v1, 32(r3)905; CHECK-WACC-NEXT:    lxv v4, 16(r3)906; CHECK-WACC-NEXT:    lxv v0, 48(r3)907; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0908; CHECK-WACC-NEXT:    pmxvi16ger2spp wacc0, v2, v2, 0, 0, 0909; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0910; CHECK-WACC-NEXT:    stxv v4, 48(r7)911; CHECK-WACC-NEXT:    stxv v5, 32(r7)912; CHECK-WACC-NEXT:    stxv v2, 16(r7)913; CHECK-WACC-NEXT:    stxv v3, 0(r7)914; CHECK-WACC-NEXT:    blr915;916; CHECK-BE-WACC-LABEL: test12:917; CHECK-BE-WACC:       # %bb.0: # %entry918; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)919; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)920; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)921; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)922; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 0923; CHECK-BE-WACC-NEXT:    pmxvi16ger2spp wacc0, v2, v2, 0, 0, 0924; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0925; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)926; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)927; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)928; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)929; CHECK-BE-WACC-NEXT:    blr930entry:931  %0 = load <512 x i1>, ptr %vqp, align 64932  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)933  store <512 x i1> %1, ptr %resp, align 64934  ret void935}936 937 938declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)939 940define void @test13(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {941; CHECK-LABEL: test13:942; CHECK:       # %bb.0: # %entry943; CHECK-NEXT:    xvf16ger2 acc0, v2, v2944; CHECK-NEXT:    xxmfacc acc0945; CHECK-NEXT:    stxv vs0, 48(r7)946; CHECK-NEXT:    stxv vs1, 32(r7)947; CHECK-NEXT:    stxv vs2, 16(r7)948; CHECK-NEXT:    stxv vs3, 0(r7)949; CHECK-NEXT:    blr950;951; CHECK-BE-LABEL: test13:952; CHECK-BE:       # %bb.0: # %entry953; CHECK-BE-NEXT:    xvf16ger2 acc0, v2, v2954; CHECK-BE-NEXT:    xxmfacc acc0955; CHECK-BE-NEXT:    stxv vs1, 16(r7)956; CHECK-BE-NEXT:    stxv vs0, 0(r7)957; CHECK-BE-NEXT:    stxv vs3, 48(r7)958; CHECK-BE-NEXT:    stxv vs2, 32(r7)959; CHECK-BE-NEXT:    blr960;961; CHECK-WACC-LABEL: test13:962; CHECK-WACC:       # %bb.0: # %entry963; CHECK-WACC-NEXT:    xvf16ger2 wacc0, v2, v2964; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0965; CHECK-WACC-NEXT:    stxv v4, 48(r7)966; CHECK-WACC-NEXT:    stxv v5, 32(r7)967; CHECK-WACC-NEXT:    stxv v2, 16(r7)968; CHECK-WACC-NEXT:    stxv v3, 0(r7)969; CHECK-WACC-NEXT:    blr970;971; CHECK-BE-WACC-LABEL: test13:972; CHECK-BE-WACC:       # %bb.0: # %entry973; CHECK-BE-WACC-NEXT:    xvf16ger2 wacc0, v2, v2974; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 0975; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)976; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)977; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)978; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)979; CHECK-BE-WACC-NEXT:    blr980entry:981  %0 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8> %vc, <16 x i8> %vc)982  store <512 x i1> %0, ptr %resp, align 64983  ret void984}985 986 987declare <512 x i1> @llvm.ppc.mma.xvf16ger2(<16 x i8>, <16 x i8>)988 989define void @test14(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {990; CHECK-LABEL: test14:991; CHECK:       # %bb.0: # %entry992; CHECK-NEXT:    lxv vs3, 0(r3)993; CHECK-NEXT:    lxv vs2, 16(r3)994; CHECK-NEXT:    lxv vs1, 32(r3)995; CHECK-NEXT:    lxv vs0, 48(r3)996; CHECK-NEXT:    xxmtacc acc0997; CHECK-NEXT:    xvf16ger2pp acc0, v2, v2998; CHECK-NEXT:    xxmfacc acc0999; CHECK-NEXT:    stxv vs0, 48(r7)1000; CHECK-NEXT:    stxv vs1, 32(r7)1001; CHECK-NEXT:    stxv vs2, 16(r7)1002; CHECK-NEXT:    stxv vs3, 0(r7)1003; CHECK-NEXT:    blr1004;1005; CHECK-BE-LABEL: test14:1006; CHECK-BE:       # %bb.0: # %entry1007; CHECK-BE-NEXT:    lxv vs3, 48(r3)1008; CHECK-BE-NEXT:    lxv vs2, 32(r3)1009; CHECK-BE-NEXT:    lxv vs1, 16(r3)1010; CHECK-BE-NEXT:    lxv vs0, 0(r3)1011; CHECK-BE-NEXT:    xxmtacc acc01012; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v21013; CHECK-BE-NEXT:    xxmfacc acc01014; CHECK-BE-NEXT:    stxv vs1, 16(r7)1015; CHECK-BE-NEXT:    stxv vs0, 0(r7)1016; CHECK-BE-NEXT:    stxv vs3, 48(r7)1017; CHECK-BE-NEXT:    stxv vs2, 32(r7)1018; CHECK-BE-NEXT:    blr1019;1020; CHECK-WACC-LABEL: test14:1021; CHECK-WACC:       # %bb.0: # %entry1022; CHECK-WACC-NEXT:    lxv v5, 0(r3)1023; CHECK-WACC-NEXT:    lxv v1, 32(r3)1024; CHECK-WACC-NEXT:    lxv v4, 16(r3)1025; CHECK-WACC-NEXT:    lxv v0, 48(r3)1026; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01027; CHECK-WACC-NEXT:    xvf16ger2pp wacc0, v2, v21028; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01029; CHECK-WACC-NEXT:    stxv v4, 48(r7)1030; CHECK-WACC-NEXT:    stxv v5, 32(r7)1031; CHECK-WACC-NEXT:    stxv v2, 16(r7)1032; CHECK-WACC-NEXT:    stxv v3, 0(r7)1033; CHECK-WACC-NEXT:    blr1034;1035; CHECK-BE-WACC-LABEL: test14:1036; CHECK-BE-WACC:       # %bb.0: # %entry1037; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1038; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1039; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1040; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1041; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01042; CHECK-BE-WACC-NEXT:    xvf16ger2pp wacc0, v2, v21043; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01044; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1045; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1046; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1047; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1048; CHECK-BE-WACC-NEXT:    blr1049entry:1050  %0 = load <512 x i1>, ptr %vqp, align 641051  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1052  store <512 x i1> %1, ptr %resp, align 641053  ret void1054}1055 1056 1057declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)1058 1059define void @test15(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1060; CHECK-LABEL: test15:1061; CHECK:       # %bb.0: # %entry1062; CHECK-NEXT:    lxv vs3, 0(r3)1063; CHECK-NEXT:    lxv vs2, 16(r3)1064; CHECK-NEXT:    lxv vs1, 32(r3)1065; CHECK-NEXT:    lxv vs0, 48(r3)1066; CHECK-NEXT:    xxmtacc acc01067; CHECK-NEXT:    xvf16ger2pn acc0, v2, v21068; CHECK-NEXT:    xxmfacc acc01069; CHECK-NEXT:    stxv vs0, 48(r7)1070; CHECK-NEXT:    stxv vs1, 32(r7)1071; CHECK-NEXT:    stxv vs2, 16(r7)1072; CHECK-NEXT:    stxv vs3, 0(r7)1073; CHECK-NEXT:    blr1074;1075; CHECK-BE-LABEL: test15:1076; CHECK-BE:       # %bb.0: # %entry1077; CHECK-BE-NEXT:    lxv vs3, 48(r3)1078; CHECK-BE-NEXT:    lxv vs2, 32(r3)1079; CHECK-BE-NEXT:    lxv vs1, 16(r3)1080; CHECK-BE-NEXT:    lxv vs0, 0(r3)1081; CHECK-BE-NEXT:    xxmtacc acc01082; CHECK-BE-NEXT:    xvf16ger2pn acc0, v2, v21083; CHECK-BE-NEXT:    xxmfacc acc01084; CHECK-BE-NEXT:    stxv vs1, 16(r7)1085; CHECK-BE-NEXT:    stxv vs0, 0(r7)1086; CHECK-BE-NEXT:    stxv vs3, 48(r7)1087; CHECK-BE-NEXT:    stxv vs2, 32(r7)1088; CHECK-BE-NEXT:    blr1089;1090; CHECK-WACC-LABEL: test15:1091; CHECK-WACC:       # %bb.0: # %entry1092; CHECK-WACC-NEXT:    lxv v5, 0(r3)1093; CHECK-WACC-NEXT:    lxv v1, 32(r3)1094; CHECK-WACC-NEXT:    lxv v4, 16(r3)1095; CHECK-WACC-NEXT:    lxv v0, 48(r3)1096; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01097; CHECK-WACC-NEXT:    xvf16ger2pn wacc0, v2, v21098; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01099; CHECK-WACC-NEXT:    stxv v4, 48(r7)1100; CHECK-WACC-NEXT:    stxv v5, 32(r7)1101; CHECK-WACC-NEXT:    stxv v2, 16(r7)1102; CHECK-WACC-NEXT:    stxv v3, 0(r7)1103; CHECK-WACC-NEXT:    blr1104;1105; CHECK-BE-WACC-LABEL: test15:1106; CHECK-BE-WACC:       # %bb.0: # %entry1107; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1108; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1109; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1110; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1111; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01112; CHECK-BE-WACC-NEXT:    xvf16ger2pn wacc0, v2, v21113; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01114; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1115; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1116; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1117; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1118; CHECK-BE-WACC-NEXT:    blr1119entry:1120  %0 = load <512 x i1>, ptr %vqp, align 641121  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1122  store <512 x i1> %1, ptr %resp, align 641123  ret void1124}1125 1126 1127declare <512 x i1> @llvm.ppc.mma.xvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>)1128 1129define void @test16(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1130; CHECK-LABEL: test16:1131; CHECK:       # %bb.0: # %entry1132; CHECK-NEXT:    lxv vs3, 0(r3)1133; CHECK-NEXT:    lxv vs2, 16(r3)1134; CHECK-NEXT:    lxv vs1, 32(r3)1135; CHECK-NEXT:    lxv vs0, 48(r3)1136; CHECK-NEXT:    xxmtacc acc01137; CHECK-NEXT:    xvf16ger2np acc0, v2, v21138; CHECK-NEXT:    xxmfacc acc01139; CHECK-NEXT:    stxv vs0, 48(r7)1140; CHECK-NEXT:    stxv vs1, 32(r7)1141; CHECK-NEXT:    stxv vs2, 16(r7)1142; CHECK-NEXT:    stxv vs3, 0(r7)1143; CHECK-NEXT:    blr1144;1145; CHECK-BE-LABEL: test16:1146; CHECK-BE:       # %bb.0: # %entry1147; CHECK-BE-NEXT:    lxv vs3, 48(r3)1148; CHECK-BE-NEXT:    lxv vs2, 32(r3)1149; CHECK-BE-NEXT:    lxv vs1, 16(r3)1150; CHECK-BE-NEXT:    lxv vs0, 0(r3)1151; CHECK-BE-NEXT:    xxmtacc acc01152; CHECK-BE-NEXT:    xvf16ger2np acc0, v2, v21153; CHECK-BE-NEXT:    xxmfacc acc01154; CHECK-BE-NEXT:    stxv vs1, 16(r7)1155; CHECK-BE-NEXT:    stxv vs0, 0(r7)1156; CHECK-BE-NEXT:    stxv vs3, 48(r7)1157; CHECK-BE-NEXT:    stxv vs2, 32(r7)1158; CHECK-BE-NEXT:    blr1159;1160; CHECK-WACC-LABEL: test16:1161; CHECK-WACC:       # %bb.0: # %entry1162; CHECK-WACC-NEXT:    lxv v5, 0(r3)1163; CHECK-WACC-NEXT:    lxv v1, 32(r3)1164; CHECK-WACC-NEXT:    lxv v4, 16(r3)1165; CHECK-WACC-NEXT:    lxv v0, 48(r3)1166; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01167; CHECK-WACC-NEXT:    xvf16ger2np wacc0, v2, v21168; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01169; CHECK-WACC-NEXT:    stxv v4, 48(r7)1170; CHECK-WACC-NEXT:    stxv v5, 32(r7)1171; CHECK-WACC-NEXT:    stxv v2, 16(r7)1172; CHECK-WACC-NEXT:    stxv v3, 0(r7)1173; CHECK-WACC-NEXT:    blr1174;1175; CHECK-BE-WACC-LABEL: test16:1176; CHECK-BE-WACC:       # %bb.0: # %entry1177; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1178; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1179; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1180; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1181; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01182; CHECK-BE-WACC-NEXT:    xvf16ger2np wacc0, v2, v21183; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01184; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1185; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1186; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1187; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1188; CHECK-BE-WACC-NEXT:    blr1189entry:1190  %0 = load <512 x i1>, ptr %vqp, align 641191  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1192  store <512 x i1> %1, ptr %resp, align 641193  ret void1194}1195 1196 1197declare <512 x i1> @llvm.ppc.mma.xvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>)1198 1199define void @test17(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1200; CHECK-LABEL: test17:1201; CHECK:       # %bb.0: # %entry1202; CHECK-NEXT:    lxv vs3, 0(r3)1203; CHECK-NEXT:    lxv vs2, 16(r3)1204; CHECK-NEXT:    lxv vs1, 32(r3)1205; CHECK-NEXT:    lxv vs0, 48(r3)1206; CHECK-NEXT:    xxmtacc acc01207; CHECK-NEXT:    xvf16ger2nn acc0, v2, v21208; CHECK-NEXT:    xxmfacc acc01209; CHECK-NEXT:    stxv vs0, 48(r7)1210; CHECK-NEXT:    stxv vs1, 32(r7)1211; CHECK-NEXT:    stxv vs2, 16(r7)1212; CHECK-NEXT:    stxv vs3, 0(r7)1213; CHECK-NEXT:    blr1214;1215; CHECK-BE-LABEL: test17:1216; CHECK-BE:       # %bb.0: # %entry1217; CHECK-BE-NEXT:    lxv vs3, 48(r3)1218; CHECK-BE-NEXT:    lxv vs2, 32(r3)1219; CHECK-BE-NEXT:    lxv vs1, 16(r3)1220; CHECK-BE-NEXT:    lxv vs0, 0(r3)1221; CHECK-BE-NEXT:    xxmtacc acc01222; CHECK-BE-NEXT:    xvf16ger2nn acc0, v2, v21223; CHECK-BE-NEXT:    xxmfacc acc01224; CHECK-BE-NEXT:    stxv vs1, 16(r7)1225; CHECK-BE-NEXT:    stxv vs0, 0(r7)1226; CHECK-BE-NEXT:    stxv vs3, 48(r7)1227; CHECK-BE-NEXT:    stxv vs2, 32(r7)1228; CHECK-BE-NEXT:    blr1229;1230; CHECK-WACC-LABEL: test17:1231; CHECK-WACC:       # %bb.0: # %entry1232; CHECK-WACC-NEXT:    lxv v5, 0(r3)1233; CHECK-WACC-NEXT:    lxv v1, 32(r3)1234; CHECK-WACC-NEXT:    lxv v4, 16(r3)1235; CHECK-WACC-NEXT:    lxv v0, 48(r3)1236; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01237; CHECK-WACC-NEXT:    xvf16ger2nn wacc0, v2, v21238; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01239; CHECK-WACC-NEXT:    stxv v4, 48(r7)1240; CHECK-WACC-NEXT:    stxv v5, 32(r7)1241; CHECK-WACC-NEXT:    stxv v2, 16(r7)1242; CHECK-WACC-NEXT:    stxv v3, 0(r7)1243; CHECK-WACC-NEXT:    blr1244;1245; CHECK-BE-WACC-LABEL: test17:1246; CHECK-BE-WACC:       # %bb.0: # %entry1247; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1248; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1249; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1250; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1251; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01252; CHECK-BE-WACC-NEXT:    xvf16ger2nn wacc0, v2, v21253; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01254; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1255; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1256; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1257; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1258; CHECK-BE-WACC-NEXT:    blr1259entry:1260  %0 = load <512 x i1>, ptr %vqp, align 641261  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1262  store <512 x i1> %1, ptr %resp, align 641263  ret void1264}1265 1266 1267declare <512 x i1> @llvm.ppc.mma.xvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>)1268 1269define void @test18(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1270; CHECK-LABEL: test18:1271; CHECK:       # %bb.0: # %entry1272; CHECK-NEXT:    pmxvf16ger2 acc0, v2, v2, 0, 0, 01273; CHECK-NEXT:    xxmfacc acc01274; CHECK-NEXT:    stxv vs0, 48(r7)1275; CHECK-NEXT:    stxv vs1, 32(r7)1276; CHECK-NEXT:    stxv vs2, 16(r7)1277; CHECK-NEXT:    stxv vs3, 0(r7)1278; CHECK-NEXT:    blr1279;1280; CHECK-BE-LABEL: test18:1281; CHECK-BE:       # %bb.0: # %entry1282; CHECK-BE-NEXT:    pmxvf16ger2 acc0, v2, v2, 0, 0, 01283; CHECK-BE-NEXT:    xxmfacc acc01284; CHECK-BE-NEXT:    stxv vs1, 16(r7)1285; CHECK-BE-NEXT:    stxv vs0, 0(r7)1286; CHECK-BE-NEXT:    stxv vs3, 48(r7)1287; CHECK-BE-NEXT:    stxv vs2, 32(r7)1288; CHECK-BE-NEXT:    blr1289;1290; CHECK-WACC-LABEL: test18:1291; CHECK-WACC:       # %bb.0: # %entry1292; CHECK-WACC-NEXT:    pmxvf16ger2 wacc0, v2, v2, 0, 0, 01293; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01294; CHECK-WACC-NEXT:    stxv v4, 48(r7)1295; CHECK-WACC-NEXT:    stxv v5, 32(r7)1296; CHECK-WACC-NEXT:    stxv v2, 16(r7)1297; CHECK-WACC-NEXT:    stxv v3, 0(r7)1298; CHECK-WACC-NEXT:    blr1299;1300; CHECK-BE-WACC-LABEL: test18:1301; CHECK-BE-WACC:       # %bb.0: # %entry1302; CHECK-BE-WACC-NEXT:    pmxvf16ger2 wacc0, v2, v2, 0, 0, 01303; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01304; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1305; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1306; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1307; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1308; CHECK-BE-WACC-NEXT:    blr1309entry:1310  %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)1311  store <512 x i1> %0, ptr %resp, align 641312  ret void1313}1314 1315 1316declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2(<16 x i8>, <16 x i8>, i32, i32, i32)1317 1318define void @test19(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1319; CHECK-LABEL: test19:1320; CHECK:       # %bb.0: # %entry1321; CHECK-NEXT:    lxv vs3, 0(r3)1322; CHECK-NEXT:    lxv vs2, 16(r3)1323; CHECK-NEXT:    lxv vs1, 32(r3)1324; CHECK-NEXT:    lxv vs0, 48(r3)1325; CHECK-NEXT:    xxmtacc acc01326; CHECK-NEXT:    pmxvf16ger2pp acc0, v2, v2, 0, 0, 01327; CHECK-NEXT:    xxmfacc acc01328; CHECK-NEXT:    stxv vs0, 48(r7)1329; CHECK-NEXT:    stxv vs1, 32(r7)1330; CHECK-NEXT:    stxv vs2, 16(r7)1331; CHECK-NEXT:    stxv vs3, 0(r7)1332; CHECK-NEXT:    blr1333;1334; CHECK-BE-LABEL: test19:1335; CHECK-BE:       # %bb.0: # %entry1336; CHECK-BE-NEXT:    lxv vs3, 48(r3)1337; CHECK-BE-NEXT:    lxv vs2, 32(r3)1338; CHECK-BE-NEXT:    lxv vs1, 16(r3)1339; CHECK-BE-NEXT:    lxv vs0, 0(r3)1340; CHECK-BE-NEXT:    xxmtacc acc01341; CHECK-BE-NEXT:    pmxvf16ger2pp acc0, v2, v2, 0, 0, 01342; CHECK-BE-NEXT:    xxmfacc acc01343; CHECK-BE-NEXT:    stxv vs1, 16(r7)1344; CHECK-BE-NEXT:    stxv vs0, 0(r7)1345; CHECK-BE-NEXT:    stxv vs3, 48(r7)1346; CHECK-BE-NEXT:    stxv vs2, 32(r7)1347; CHECK-BE-NEXT:    blr1348;1349; CHECK-WACC-LABEL: test19:1350; CHECK-WACC:       # %bb.0: # %entry1351; CHECK-WACC-NEXT:    lxv v5, 0(r3)1352; CHECK-WACC-NEXT:    lxv v1, 32(r3)1353; CHECK-WACC-NEXT:    lxv v4, 16(r3)1354; CHECK-WACC-NEXT:    lxv v0, 48(r3)1355; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01356; CHECK-WACC-NEXT:    pmxvf16ger2pp wacc0, v2, v2, 0, 0, 01357; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01358; CHECK-WACC-NEXT:    stxv v4, 48(r7)1359; CHECK-WACC-NEXT:    stxv v5, 32(r7)1360; CHECK-WACC-NEXT:    stxv v2, 16(r7)1361; CHECK-WACC-NEXT:    stxv v3, 0(r7)1362; CHECK-WACC-NEXT:    blr1363;1364; CHECK-BE-WACC-LABEL: test19:1365; CHECK-BE-WACC:       # %bb.0: # %entry1366; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1367; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1368; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1369; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1370; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01371; CHECK-BE-WACC-NEXT:    pmxvf16ger2pp wacc0, v2, v2, 0, 0, 01372; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01373; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1374; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1375; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1376; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1377; CHECK-BE-WACC-NEXT:    blr1378entry:1379  %0 = load <512 x i1>, ptr %vqp, align 641380  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)1381  store <512 x i1> %1, ptr %resp, align 641382  ret void1383}1384 1385 1386declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)1387 1388define void @test20(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1389; CHECK-LABEL: test20:1390; CHECK:       # %bb.0: # %entry1391; CHECK-NEXT:    lxv vs3, 0(r3)1392; CHECK-NEXT:    lxv vs2, 16(r3)1393; CHECK-NEXT:    lxv vs1, 32(r3)1394; CHECK-NEXT:    lxv vs0, 48(r3)1395; CHECK-NEXT:    xxmtacc acc01396; CHECK-NEXT:    pmxvf16ger2pn acc0, v2, v2, 0, 0, 01397; CHECK-NEXT:    xxmfacc acc01398; CHECK-NEXT:    stxv vs0, 48(r7)1399; CHECK-NEXT:    stxv vs1, 32(r7)1400; CHECK-NEXT:    stxv vs2, 16(r7)1401; CHECK-NEXT:    stxv vs3, 0(r7)1402; CHECK-NEXT:    blr1403;1404; CHECK-BE-LABEL: test20:1405; CHECK-BE:       # %bb.0: # %entry1406; CHECK-BE-NEXT:    lxv vs3, 48(r3)1407; CHECK-BE-NEXT:    lxv vs2, 32(r3)1408; CHECK-BE-NEXT:    lxv vs1, 16(r3)1409; CHECK-BE-NEXT:    lxv vs0, 0(r3)1410; CHECK-BE-NEXT:    xxmtacc acc01411; CHECK-BE-NEXT:    pmxvf16ger2pn acc0, v2, v2, 0, 0, 01412; CHECK-BE-NEXT:    xxmfacc acc01413; CHECK-BE-NEXT:    stxv vs1, 16(r7)1414; CHECK-BE-NEXT:    stxv vs0, 0(r7)1415; CHECK-BE-NEXT:    stxv vs3, 48(r7)1416; CHECK-BE-NEXT:    stxv vs2, 32(r7)1417; CHECK-BE-NEXT:    blr1418;1419; CHECK-WACC-LABEL: test20:1420; CHECK-WACC:       # %bb.0: # %entry1421; CHECK-WACC-NEXT:    lxv v5, 0(r3)1422; CHECK-WACC-NEXT:    lxv v1, 32(r3)1423; CHECK-WACC-NEXT:    lxv v4, 16(r3)1424; CHECK-WACC-NEXT:    lxv v0, 48(r3)1425; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01426; CHECK-WACC-NEXT:    pmxvf16ger2pn wacc0, v2, v2, 0, 0, 01427; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01428; CHECK-WACC-NEXT:    stxv v4, 48(r7)1429; CHECK-WACC-NEXT:    stxv v5, 32(r7)1430; CHECK-WACC-NEXT:    stxv v2, 16(r7)1431; CHECK-WACC-NEXT:    stxv v3, 0(r7)1432; CHECK-WACC-NEXT:    blr1433;1434; CHECK-BE-WACC-LABEL: test20:1435; CHECK-BE-WACC:       # %bb.0: # %entry1436; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1437; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1438; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1439; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1440; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01441; CHECK-BE-WACC-NEXT:    pmxvf16ger2pn wacc0, v2, v2, 0, 0, 01442; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01443; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1444; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1445; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1446; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1447; CHECK-BE-WACC-NEXT:    blr1448entry:1449  %0 = load <512 x i1>, ptr %vqp, align 641450  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)1451  store <512 x i1> %1, ptr %resp, align 641452  ret void1453}1454 1455 1456declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2pn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)1457 1458define void @test21(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1459; CHECK-LABEL: test21:1460; CHECK:       # %bb.0: # %entry1461; CHECK-NEXT:    lxv vs3, 0(r3)1462; CHECK-NEXT:    lxv vs2, 16(r3)1463; CHECK-NEXT:    lxv vs1, 32(r3)1464; CHECK-NEXT:    lxv vs0, 48(r3)1465; CHECK-NEXT:    xxmtacc acc01466; CHECK-NEXT:    pmxvf16ger2np acc0, v2, v2, 0, 0, 01467; CHECK-NEXT:    xxmfacc acc01468; CHECK-NEXT:    stxv vs0, 48(r7)1469; CHECK-NEXT:    stxv vs1, 32(r7)1470; CHECK-NEXT:    stxv vs2, 16(r7)1471; CHECK-NEXT:    stxv vs3, 0(r7)1472; CHECK-NEXT:    blr1473;1474; CHECK-BE-LABEL: test21:1475; CHECK-BE:       # %bb.0: # %entry1476; CHECK-BE-NEXT:    lxv vs3, 48(r3)1477; CHECK-BE-NEXT:    lxv vs2, 32(r3)1478; CHECK-BE-NEXT:    lxv vs1, 16(r3)1479; CHECK-BE-NEXT:    lxv vs0, 0(r3)1480; CHECK-BE-NEXT:    xxmtacc acc01481; CHECK-BE-NEXT:    pmxvf16ger2np acc0, v2, v2, 0, 0, 01482; CHECK-BE-NEXT:    xxmfacc acc01483; CHECK-BE-NEXT:    stxv vs1, 16(r7)1484; CHECK-BE-NEXT:    stxv vs0, 0(r7)1485; CHECK-BE-NEXT:    stxv vs3, 48(r7)1486; CHECK-BE-NEXT:    stxv vs2, 32(r7)1487; CHECK-BE-NEXT:    blr1488;1489; CHECK-WACC-LABEL: test21:1490; CHECK-WACC:       # %bb.0: # %entry1491; CHECK-WACC-NEXT:    lxv v5, 0(r3)1492; CHECK-WACC-NEXT:    lxv v1, 32(r3)1493; CHECK-WACC-NEXT:    lxv v4, 16(r3)1494; CHECK-WACC-NEXT:    lxv v0, 48(r3)1495; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01496; CHECK-WACC-NEXT:    pmxvf16ger2np wacc0, v2, v2, 0, 0, 01497; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01498; CHECK-WACC-NEXT:    stxv v4, 48(r7)1499; CHECK-WACC-NEXT:    stxv v5, 32(r7)1500; CHECK-WACC-NEXT:    stxv v2, 16(r7)1501; CHECK-WACC-NEXT:    stxv v3, 0(r7)1502; CHECK-WACC-NEXT:    blr1503;1504; CHECK-BE-WACC-LABEL: test21:1505; CHECK-BE-WACC:       # %bb.0: # %entry1506; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1507; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1508; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1509; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1510; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01511; CHECK-BE-WACC-NEXT:    pmxvf16ger2np wacc0, v2, v2, 0, 0, 01512; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01513; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1514; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1515; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1516; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1517; CHECK-BE-WACC-NEXT:    blr1518entry:1519  %0 = load <512 x i1>, ptr %vqp, align 641520  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)1521  store <512 x i1> %1, ptr %resp, align 641522  ret void1523}1524 1525 1526declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2np(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)1527 1528define void @test22(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1529; CHECK-LABEL: test22:1530; CHECK:       # %bb.0: # %entry1531; CHECK-NEXT:    lxv vs3, 0(r3)1532; CHECK-NEXT:    lxv vs2, 16(r3)1533; CHECK-NEXT:    lxv vs1, 32(r3)1534; CHECK-NEXT:    lxv vs0, 48(r3)1535; CHECK-NEXT:    xxmtacc acc01536; CHECK-NEXT:    pmxvf16ger2nn acc0, v2, v2, 0, 0, 01537; CHECK-NEXT:    xxmfacc acc01538; CHECK-NEXT:    stxv vs0, 48(r7)1539; CHECK-NEXT:    stxv vs1, 32(r7)1540; CHECK-NEXT:    stxv vs2, 16(r7)1541; CHECK-NEXT:    stxv vs3, 0(r7)1542; CHECK-NEXT:    blr1543;1544; CHECK-BE-LABEL: test22:1545; CHECK-BE:       # %bb.0: # %entry1546; CHECK-BE-NEXT:    lxv vs3, 48(r3)1547; CHECK-BE-NEXT:    lxv vs2, 32(r3)1548; CHECK-BE-NEXT:    lxv vs1, 16(r3)1549; CHECK-BE-NEXT:    lxv vs0, 0(r3)1550; CHECK-BE-NEXT:    xxmtacc acc01551; CHECK-BE-NEXT:    pmxvf16ger2nn acc0, v2, v2, 0, 0, 01552; CHECK-BE-NEXT:    xxmfacc acc01553; CHECK-BE-NEXT:    stxv vs1, 16(r7)1554; CHECK-BE-NEXT:    stxv vs0, 0(r7)1555; CHECK-BE-NEXT:    stxv vs3, 48(r7)1556; CHECK-BE-NEXT:    stxv vs2, 32(r7)1557; CHECK-BE-NEXT:    blr1558;1559; CHECK-WACC-LABEL: test22:1560; CHECK-WACC:       # %bb.0: # %entry1561; CHECK-WACC-NEXT:    lxv v5, 0(r3)1562; CHECK-WACC-NEXT:    lxv v1, 32(r3)1563; CHECK-WACC-NEXT:    lxv v4, 16(r3)1564; CHECK-WACC-NEXT:    lxv v0, 48(r3)1565; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01566; CHECK-WACC-NEXT:    pmxvf16ger2nn wacc0, v2, v2, 0, 0, 01567; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01568; CHECK-WACC-NEXT:    stxv v4, 48(r7)1569; CHECK-WACC-NEXT:    stxv v5, 32(r7)1570; CHECK-WACC-NEXT:    stxv v2, 16(r7)1571; CHECK-WACC-NEXT:    stxv v3, 0(r7)1572; CHECK-WACC-NEXT:    blr1573;1574; CHECK-BE-WACC-LABEL: test22:1575; CHECK-BE-WACC:       # %bb.0: # %entry1576; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1577; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1578; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1579; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1580; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01581; CHECK-BE-WACC-NEXT:    pmxvf16ger2nn wacc0, v2, v2, 0, 0, 01582; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01583; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1584; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1585; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1586; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1587; CHECK-BE-WACC-NEXT:    blr1588entry:1589  %0 = load <512 x i1>, ptr %vqp, align 641590  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0)1591  store <512 x i1> %1, ptr %resp, align 641592  ret void1593}1594 1595 1596declare <512 x i1> @llvm.ppc.mma.pmxvf16ger2nn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32)1597 1598define void @test23(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1599; CHECK-LABEL: test23:1600; CHECK:       # %bb.0: # %entry1601; CHECK-NEXT:    xvf32ger acc0, v2, v21602; CHECK-NEXT:    xxmfacc acc01603; CHECK-NEXT:    stxv vs0, 48(r7)1604; CHECK-NEXT:    stxv vs1, 32(r7)1605; CHECK-NEXT:    stxv vs2, 16(r7)1606; CHECK-NEXT:    stxv vs3, 0(r7)1607; CHECK-NEXT:    blr1608;1609; CHECK-BE-LABEL: test23:1610; CHECK-BE:       # %bb.0: # %entry1611; CHECK-BE-NEXT:    xvf32ger acc0, v2, v21612; CHECK-BE-NEXT:    xxmfacc acc01613; CHECK-BE-NEXT:    stxv vs1, 16(r7)1614; CHECK-BE-NEXT:    stxv vs0, 0(r7)1615; CHECK-BE-NEXT:    stxv vs3, 48(r7)1616; CHECK-BE-NEXT:    stxv vs2, 32(r7)1617; CHECK-BE-NEXT:    blr1618;1619; CHECK-WACC-LABEL: test23:1620; CHECK-WACC:       # %bb.0: # %entry1621; CHECK-WACC-NEXT:    xvf32ger wacc0, v2, v21622; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01623; CHECK-WACC-NEXT:    stxv v4, 48(r7)1624; CHECK-WACC-NEXT:    stxv v5, 32(r7)1625; CHECK-WACC-NEXT:    stxv v2, 16(r7)1626; CHECK-WACC-NEXT:    stxv v3, 0(r7)1627; CHECK-WACC-NEXT:    blr1628;1629; CHECK-BE-WACC-LABEL: test23:1630; CHECK-BE-WACC:       # %bb.0: # %entry1631; CHECK-BE-WACC-NEXT:    xvf32ger wacc0, v2, v21632; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01633; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1634; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1635; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1636; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1637; CHECK-BE-WACC-NEXT:    blr1638entry:1639  %0 = tail call <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8> %vc, <16 x i8> %vc)1640  store <512 x i1> %0, ptr %resp, align 641641  ret void1642}1643 1644 1645declare <512 x i1> @llvm.ppc.mma.xvf32ger(<16 x i8>, <16 x i8>)1646 1647define void @test24(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1648; CHECK-LABEL: test24:1649; CHECK:       # %bb.0: # %entry1650; CHECK-NEXT:    lxv vs3, 0(r3)1651; CHECK-NEXT:    lxv vs2, 16(r3)1652; CHECK-NEXT:    lxv vs1, 32(r3)1653; CHECK-NEXT:    lxv vs0, 48(r3)1654; CHECK-NEXT:    xxmtacc acc01655; CHECK-NEXT:    xvf32gerpp acc0, v2, v21656; CHECK-NEXT:    xxmfacc acc01657; CHECK-NEXT:    stxv vs0, 48(r7)1658; CHECK-NEXT:    stxv vs1, 32(r7)1659; CHECK-NEXT:    stxv vs2, 16(r7)1660; CHECK-NEXT:    stxv vs3, 0(r7)1661; CHECK-NEXT:    blr1662;1663; CHECK-BE-LABEL: test24:1664; CHECK-BE:       # %bb.0: # %entry1665; CHECK-BE-NEXT:    lxv vs3, 48(r3)1666; CHECK-BE-NEXT:    lxv vs2, 32(r3)1667; CHECK-BE-NEXT:    lxv vs1, 16(r3)1668; CHECK-BE-NEXT:    lxv vs0, 0(r3)1669; CHECK-BE-NEXT:    xxmtacc acc01670; CHECK-BE-NEXT:    xvf32gerpp acc0, v2, v21671; CHECK-BE-NEXT:    xxmfacc acc01672; CHECK-BE-NEXT:    stxv vs1, 16(r7)1673; CHECK-BE-NEXT:    stxv vs0, 0(r7)1674; CHECK-BE-NEXT:    stxv vs3, 48(r7)1675; CHECK-BE-NEXT:    stxv vs2, 32(r7)1676; CHECK-BE-NEXT:    blr1677;1678; CHECK-WACC-LABEL: test24:1679; CHECK-WACC:       # %bb.0: # %entry1680; CHECK-WACC-NEXT:    lxv v5, 0(r3)1681; CHECK-WACC-NEXT:    lxv v1, 32(r3)1682; CHECK-WACC-NEXT:    lxv v4, 16(r3)1683; CHECK-WACC-NEXT:    lxv v0, 48(r3)1684; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01685; CHECK-WACC-NEXT:    xvf32gerpp wacc0, v2, v21686; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01687; CHECK-WACC-NEXT:    stxv v4, 48(r7)1688; CHECK-WACC-NEXT:    stxv v5, 32(r7)1689; CHECK-WACC-NEXT:    stxv v2, 16(r7)1690; CHECK-WACC-NEXT:    stxv v3, 0(r7)1691; CHECK-WACC-NEXT:    blr1692;1693; CHECK-BE-WACC-LABEL: test24:1694; CHECK-BE-WACC:       # %bb.0: # %entry1695; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1696; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1697; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1698; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1699; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01700; CHECK-BE-WACC-NEXT:    xvf32gerpp wacc0, v2, v21701; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01702; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1703; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1704; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1705; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1706; CHECK-BE-WACC-NEXT:    blr1707entry:1708  %0 = load <512 x i1>, ptr %vqp, align 641709  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1710  store <512 x i1> %1, ptr %resp, align 641711  ret void1712}1713 1714 1715declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)1716 1717define void @test25(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1718; CHECK-LABEL: test25:1719; CHECK:       # %bb.0: # %entry1720; CHECK-NEXT:    lxv vs3, 0(r3)1721; CHECK-NEXT:    lxv vs2, 16(r3)1722; CHECK-NEXT:    lxv vs1, 32(r3)1723; CHECK-NEXT:    lxv vs0, 48(r3)1724; CHECK-NEXT:    xxmtacc acc01725; CHECK-NEXT:    xvf32gerpn acc0, v2, v21726; CHECK-NEXT:    xxmfacc acc01727; CHECK-NEXT:    stxv vs0, 48(r7)1728; CHECK-NEXT:    stxv vs1, 32(r7)1729; CHECK-NEXT:    stxv vs2, 16(r7)1730; CHECK-NEXT:    stxv vs3, 0(r7)1731; CHECK-NEXT:    blr1732;1733; CHECK-BE-LABEL: test25:1734; CHECK-BE:       # %bb.0: # %entry1735; CHECK-BE-NEXT:    lxv vs3, 48(r3)1736; CHECK-BE-NEXT:    lxv vs2, 32(r3)1737; CHECK-BE-NEXT:    lxv vs1, 16(r3)1738; CHECK-BE-NEXT:    lxv vs0, 0(r3)1739; CHECK-BE-NEXT:    xxmtacc acc01740; CHECK-BE-NEXT:    xvf32gerpn acc0, v2, v21741; CHECK-BE-NEXT:    xxmfacc acc01742; CHECK-BE-NEXT:    stxv vs1, 16(r7)1743; CHECK-BE-NEXT:    stxv vs0, 0(r7)1744; CHECK-BE-NEXT:    stxv vs3, 48(r7)1745; CHECK-BE-NEXT:    stxv vs2, 32(r7)1746; CHECK-BE-NEXT:    blr1747;1748; CHECK-WACC-LABEL: test25:1749; CHECK-WACC:       # %bb.0: # %entry1750; CHECK-WACC-NEXT:    lxv v5, 0(r3)1751; CHECK-WACC-NEXT:    lxv v1, 32(r3)1752; CHECK-WACC-NEXT:    lxv v4, 16(r3)1753; CHECK-WACC-NEXT:    lxv v0, 48(r3)1754; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01755; CHECK-WACC-NEXT:    xvf32gerpn wacc0, v2, v21756; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01757; CHECK-WACC-NEXT:    stxv v4, 48(r7)1758; CHECK-WACC-NEXT:    stxv v5, 32(r7)1759; CHECK-WACC-NEXT:    stxv v2, 16(r7)1760; CHECK-WACC-NEXT:    stxv v3, 0(r7)1761; CHECK-WACC-NEXT:    blr1762;1763; CHECK-BE-WACC-LABEL: test25:1764; CHECK-BE-WACC:       # %bb.0: # %entry1765; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1766; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1767; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1768; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1769; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01770; CHECK-BE-WACC-NEXT:    xvf32gerpn wacc0, v2, v21771; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01772; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1773; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1774; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1775; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1776; CHECK-BE-WACC-NEXT:    blr1777entry:1778  %0 = load <512 x i1>, ptr %vqp, align 641779  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1780  store <512 x i1> %1, ptr %resp, align 641781  ret void1782}1783 1784 1785declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)1786 1787define void @test26(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1788; CHECK-LABEL: test26:1789; CHECK:       # %bb.0: # %entry1790; CHECK-NEXT:    lxv vs3, 0(r3)1791; CHECK-NEXT:    lxv vs2, 16(r3)1792; CHECK-NEXT:    lxv vs1, 32(r3)1793; CHECK-NEXT:    lxv vs0, 48(r3)1794; CHECK-NEXT:    xxmtacc acc01795; CHECK-NEXT:    xvf32gernp acc0, v2, v21796; CHECK-NEXT:    xxmfacc acc01797; CHECK-NEXT:    stxv vs0, 48(r7)1798; CHECK-NEXT:    stxv vs1, 32(r7)1799; CHECK-NEXT:    stxv vs2, 16(r7)1800; CHECK-NEXT:    stxv vs3, 0(r7)1801; CHECK-NEXT:    blr1802;1803; CHECK-BE-LABEL: test26:1804; CHECK-BE:       # %bb.0: # %entry1805; CHECK-BE-NEXT:    lxv vs3, 48(r3)1806; CHECK-BE-NEXT:    lxv vs2, 32(r3)1807; CHECK-BE-NEXT:    lxv vs1, 16(r3)1808; CHECK-BE-NEXT:    lxv vs0, 0(r3)1809; CHECK-BE-NEXT:    xxmtacc acc01810; CHECK-BE-NEXT:    xvf32gernp acc0, v2, v21811; CHECK-BE-NEXT:    xxmfacc acc01812; CHECK-BE-NEXT:    stxv vs1, 16(r7)1813; CHECK-BE-NEXT:    stxv vs0, 0(r7)1814; CHECK-BE-NEXT:    stxv vs3, 48(r7)1815; CHECK-BE-NEXT:    stxv vs2, 32(r7)1816; CHECK-BE-NEXT:    blr1817;1818; CHECK-WACC-LABEL: test26:1819; CHECK-WACC:       # %bb.0: # %entry1820; CHECK-WACC-NEXT:    lxv v5, 0(r3)1821; CHECK-WACC-NEXT:    lxv v1, 32(r3)1822; CHECK-WACC-NEXT:    lxv v4, 16(r3)1823; CHECK-WACC-NEXT:    lxv v0, 48(r3)1824; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01825; CHECK-WACC-NEXT:    xvf32gernp wacc0, v2, v21826; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01827; CHECK-WACC-NEXT:    stxv v4, 48(r7)1828; CHECK-WACC-NEXT:    stxv v5, 32(r7)1829; CHECK-WACC-NEXT:    stxv v2, 16(r7)1830; CHECK-WACC-NEXT:    stxv v3, 0(r7)1831; CHECK-WACC-NEXT:    blr1832;1833; CHECK-BE-WACC-LABEL: test26:1834; CHECK-BE-WACC:       # %bb.0: # %entry1835; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1836; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1837; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1838; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1839; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01840; CHECK-BE-WACC-NEXT:    xvf32gernp wacc0, v2, v21841; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01842; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1843; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1844; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1845; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1846; CHECK-BE-WACC-NEXT:    blr1847entry:1848  %0 = load <512 x i1>, ptr %vqp, align 641849  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1850  store <512 x i1> %1, ptr %resp, align 641851  ret void1852}1853 1854 1855declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)1856 1857define void @test27(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1858; CHECK-LABEL: test27:1859; CHECK:       # %bb.0: # %entry1860; CHECK-NEXT:    lxv vs3, 0(r3)1861; CHECK-NEXT:    lxv vs2, 16(r3)1862; CHECK-NEXT:    lxv vs1, 32(r3)1863; CHECK-NEXT:    lxv vs0, 48(r3)1864; CHECK-NEXT:    xxmtacc acc01865; CHECK-NEXT:    xvf32gernn acc0, v2, v21866; CHECK-NEXT:    xxmfacc acc01867; CHECK-NEXT:    stxv vs0, 48(r7)1868; CHECK-NEXT:    stxv vs1, 32(r7)1869; CHECK-NEXT:    stxv vs2, 16(r7)1870; CHECK-NEXT:    stxv vs3, 0(r7)1871; CHECK-NEXT:    blr1872;1873; CHECK-BE-LABEL: test27:1874; CHECK-BE:       # %bb.0: # %entry1875; CHECK-BE-NEXT:    lxv vs3, 48(r3)1876; CHECK-BE-NEXT:    lxv vs2, 32(r3)1877; CHECK-BE-NEXT:    lxv vs1, 16(r3)1878; CHECK-BE-NEXT:    lxv vs0, 0(r3)1879; CHECK-BE-NEXT:    xxmtacc acc01880; CHECK-BE-NEXT:    xvf32gernn acc0, v2, v21881; CHECK-BE-NEXT:    xxmfacc acc01882; CHECK-BE-NEXT:    stxv vs1, 16(r7)1883; CHECK-BE-NEXT:    stxv vs0, 0(r7)1884; CHECK-BE-NEXT:    stxv vs3, 48(r7)1885; CHECK-BE-NEXT:    stxv vs2, 32(r7)1886; CHECK-BE-NEXT:    blr1887;1888; CHECK-WACC-LABEL: test27:1889; CHECK-WACC:       # %bb.0: # %entry1890; CHECK-WACC-NEXT:    lxv v5, 0(r3)1891; CHECK-WACC-NEXT:    lxv v1, 32(r3)1892; CHECK-WACC-NEXT:    lxv v4, 16(r3)1893; CHECK-WACC-NEXT:    lxv v0, 48(r3)1894; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01895; CHECK-WACC-NEXT:    xvf32gernn wacc0, v2, v21896; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01897; CHECK-WACC-NEXT:    stxv v4, 48(r7)1898; CHECK-WACC-NEXT:    stxv v5, 32(r7)1899; CHECK-WACC-NEXT:    stxv v2, 16(r7)1900; CHECK-WACC-NEXT:    stxv v3, 0(r7)1901; CHECK-WACC-NEXT:    blr1902;1903; CHECK-BE-WACC-LABEL: test27:1904; CHECK-BE-WACC:       # %bb.0: # %entry1905; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)1906; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)1907; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)1908; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)1909; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 01910; CHECK-BE-WACC-NEXT:    xvf32gernn wacc0, v2, v21911; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01912; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1913; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1914; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1915; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1916; CHECK-BE-WACC-NEXT:    blr1917entry:1918  %0 = load <512 x i1>, ptr %vqp, align 641919  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1920  store <512 x i1> %1, ptr %resp, align 641921  ret void1922}1923 1924 1925declare <512 x i1> @llvm.ppc.mma.xvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>)1926 1927define void @test28(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1928; CHECK-LABEL: test28:1929; CHECK:       # %bb.0: # %entry1930; CHECK-NEXT:    pmxvf32ger acc0, v2, v2, 0, 01931; CHECK-NEXT:    xxmfacc acc01932; CHECK-NEXT:    stxv vs0, 48(r7)1933; CHECK-NEXT:    stxv vs1, 32(r7)1934; CHECK-NEXT:    stxv vs2, 16(r7)1935; CHECK-NEXT:    stxv vs3, 0(r7)1936; CHECK-NEXT:    blr1937;1938; CHECK-BE-LABEL: test28:1939; CHECK-BE:       # %bb.0: # %entry1940; CHECK-BE-NEXT:    pmxvf32ger acc0, v2, v2, 0, 01941; CHECK-BE-NEXT:    xxmfacc acc01942; CHECK-BE-NEXT:    stxv vs1, 16(r7)1943; CHECK-BE-NEXT:    stxv vs0, 0(r7)1944; CHECK-BE-NEXT:    stxv vs3, 48(r7)1945; CHECK-BE-NEXT:    stxv vs2, 32(r7)1946; CHECK-BE-NEXT:    blr1947;1948; CHECK-WACC-LABEL: test28:1949; CHECK-WACC:       # %bb.0: # %entry1950; CHECK-WACC-NEXT:    pmxvf32ger wacc0, v2, v2, 0, 01951; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01952; CHECK-WACC-NEXT:    stxv v4, 48(r7)1953; CHECK-WACC-NEXT:    stxv v5, 32(r7)1954; CHECK-WACC-NEXT:    stxv v2, 16(r7)1955; CHECK-WACC-NEXT:    stxv v3, 0(r7)1956; CHECK-WACC-NEXT:    blr1957;1958; CHECK-BE-WACC-LABEL: test28:1959; CHECK-BE-WACC:       # %bb.0: # %entry1960; CHECK-BE-WACC-NEXT:    pmxvf32ger wacc0, v2, v2, 0, 01961; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 01962; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)1963; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)1964; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)1965; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)1966; CHECK-BE-WACC-NEXT:    blr1967entry:1968  %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)1969  store <512 x i1> %0, ptr %resp, align 641970  ret void1971}1972 1973 1974declare <512 x i1> @llvm.ppc.mma.pmxvf32ger(<16 x i8>, <16 x i8>, i32, i32)1975 1976define void @test29(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {1977; CHECK-LABEL: test29:1978; CHECK:       # %bb.0: # %entry1979; CHECK-NEXT:    lxv vs3, 0(r3)1980; CHECK-NEXT:    lxv vs2, 16(r3)1981; CHECK-NEXT:    lxv vs1, 32(r3)1982; CHECK-NEXT:    lxv vs0, 48(r3)1983; CHECK-NEXT:    xxmtacc acc01984; CHECK-NEXT:    pmxvf32gerpp acc0, v2, v2, 0, 01985; CHECK-NEXT:    xxmfacc acc01986; CHECK-NEXT:    stxv vs0, 48(r7)1987; CHECK-NEXT:    stxv vs1, 32(r7)1988; CHECK-NEXT:    stxv vs2, 16(r7)1989; CHECK-NEXT:    stxv vs3, 0(r7)1990; CHECK-NEXT:    blr1991;1992; CHECK-BE-LABEL: test29:1993; CHECK-BE:       # %bb.0: # %entry1994; CHECK-BE-NEXT:    lxv vs3, 48(r3)1995; CHECK-BE-NEXT:    lxv vs2, 32(r3)1996; CHECK-BE-NEXT:    lxv vs1, 16(r3)1997; CHECK-BE-NEXT:    lxv vs0, 0(r3)1998; CHECK-BE-NEXT:    xxmtacc acc01999; CHECK-BE-NEXT:    pmxvf32gerpp acc0, v2, v2, 0, 02000; CHECK-BE-NEXT:    xxmfacc acc02001; CHECK-BE-NEXT:    stxv vs1, 16(r7)2002; CHECK-BE-NEXT:    stxv vs0, 0(r7)2003; CHECK-BE-NEXT:    stxv vs3, 48(r7)2004; CHECK-BE-NEXT:    stxv vs2, 32(r7)2005; CHECK-BE-NEXT:    blr2006;2007; CHECK-WACC-LABEL: test29:2008; CHECK-WACC:       # %bb.0: # %entry2009; CHECK-WACC-NEXT:    lxv v5, 0(r3)2010; CHECK-WACC-NEXT:    lxv v1, 32(r3)2011; CHECK-WACC-NEXT:    lxv v4, 16(r3)2012; CHECK-WACC-NEXT:    lxv v0, 48(r3)2013; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02014; CHECK-WACC-NEXT:    pmxvf32gerpp wacc0, v2, v2, 0, 02015; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02016; CHECK-WACC-NEXT:    stxv v4, 48(r7)2017; CHECK-WACC-NEXT:    stxv v5, 32(r7)2018; CHECK-WACC-NEXT:    stxv v2, 16(r7)2019; CHECK-WACC-NEXT:    stxv v3, 0(r7)2020; CHECK-WACC-NEXT:    blr2021;2022; CHECK-BE-WACC-LABEL: test29:2023; CHECK-BE-WACC:       # %bb.0: # %entry2024; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2025; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2026; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2027; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2028; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02029; CHECK-BE-WACC-NEXT:    pmxvf32gerpp wacc0, v2, v2, 0, 02030; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02031; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2032; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2033; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2034; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2035; CHECK-BE-WACC-NEXT:    blr2036entry:2037  %0 = load <512 x i1>, ptr %vqp, align 642038  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)2039  store <512 x i1> %1, ptr %resp, align 642040  ret void2041}2042 2043 2044declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)2045 2046define void @test30(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2047; CHECK-LABEL: test30:2048; CHECK:       # %bb.0: # %entry2049; CHECK-NEXT:    lxv vs3, 0(r3)2050; CHECK-NEXT:    lxv vs2, 16(r3)2051; CHECK-NEXT:    lxv vs1, 32(r3)2052; CHECK-NEXT:    lxv vs0, 48(r3)2053; CHECK-NEXT:    xxmtacc acc02054; CHECK-NEXT:    pmxvf32gerpn acc0, v2, v2, 0, 02055; CHECK-NEXT:    xxmfacc acc02056; CHECK-NEXT:    stxv vs0, 48(r7)2057; CHECK-NEXT:    stxv vs1, 32(r7)2058; CHECK-NEXT:    stxv vs2, 16(r7)2059; CHECK-NEXT:    stxv vs3, 0(r7)2060; CHECK-NEXT:    blr2061;2062; CHECK-BE-LABEL: test30:2063; CHECK-BE:       # %bb.0: # %entry2064; CHECK-BE-NEXT:    lxv vs3, 48(r3)2065; CHECK-BE-NEXT:    lxv vs2, 32(r3)2066; CHECK-BE-NEXT:    lxv vs1, 16(r3)2067; CHECK-BE-NEXT:    lxv vs0, 0(r3)2068; CHECK-BE-NEXT:    xxmtacc acc02069; CHECK-BE-NEXT:    pmxvf32gerpn acc0, v2, v2, 0, 02070; CHECK-BE-NEXT:    xxmfacc acc02071; CHECK-BE-NEXT:    stxv vs1, 16(r7)2072; CHECK-BE-NEXT:    stxv vs0, 0(r7)2073; CHECK-BE-NEXT:    stxv vs3, 48(r7)2074; CHECK-BE-NEXT:    stxv vs2, 32(r7)2075; CHECK-BE-NEXT:    blr2076;2077; CHECK-WACC-LABEL: test30:2078; CHECK-WACC:       # %bb.0: # %entry2079; CHECK-WACC-NEXT:    lxv v5, 0(r3)2080; CHECK-WACC-NEXT:    lxv v1, 32(r3)2081; CHECK-WACC-NEXT:    lxv v4, 16(r3)2082; CHECK-WACC-NEXT:    lxv v0, 48(r3)2083; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02084; CHECK-WACC-NEXT:    pmxvf32gerpn wacc0, v2, v2, 0, 02085; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02086; CHECK-WACC-NEXT:    stxv v4, 48(r7)2087; CHECK-WACC-NEXT:    stxv v5, 32(r7)2088; CHECK-WACC-NEXT:    stxv v2, 16(r7)2089; CHECK-WACC-NEXT:    stxv v3, 0(r7)2090; CHECK-WACC-NEXT:    blr2091;2092; CHECK-BE-WACC-LABEL: test30:2093; CHECK-BE-WACC:       # %bb.0: # %entry2094; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2095; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2096; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2097; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2098; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02099; CHECK-BE-WACC-NEXT:    pmxvf32gerpn wacc0, v2, v2, 0, 02100; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02101; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2102; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2103; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2104; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2105; CHECK-BE-WACC-NEXT:    blr2106entry:2107  %0 = load <512 x i1>, ptr %vqp, align 642108  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)2109  store <512 x i1> %1, ptr %resp, align 642110  ret void2111}2112 2113 2114declare <512 x i1> @llvm.ppc.mma.pmxvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)2115 2116define void @test31(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2117; CHECK-LABEL: test31:2118; CHECK:       # %bb.0: # %entry2119; CHECK-NEXT:    lxv vs3, 0(r3)2120; CHECK-NEXT:    lxv vs2, 16(r3)2121; CHECK-NEXT:    lxv vs1, 32(r3)2122; CHECK-NEXT:    lxv vs0, 48(r3)2123; CHECK-NEXT:    xxmtacc acc02124; CHECK-NEXT:    pmxvf32gernp acc0, v2, v2, 0, 02125; CHECK-NEXT:    xxmfacc acc02126; CHECK-NEXT:    stxv vs0, 48(r7)2127; CHECK-NEXT:    stxv vs1, 32(r7)2128; CHECK-NEXT:    stxv vs2, 16(r7)2129; CHECK-NEXT:    stxv vs3, 0(r7)2130; CHECK-NEXT:    blr2131;2132; CHECK-BE-LABEL: test31:2133; CHECK-BE:       # %bb.0: # %entry2134; CHECK-BE-NEXT:    lxv vs3, 48(r3)2135; CHECK-BE-NEXT:    lxv vs2, 32(r3)2136; CHECK-BE-NEXT:    lxv vs1, 16(r3)2137; CHECK-BE-NEXT:    lxv vs0, 0(r3)2138; CHECK-BE-NEXT:    xxmtacc acc02139; CHECK-BE-NEXT:    pmxvf32gernp acc0, v2, v2, 0, 02140; CHECK-BE-NEXT:    xxmfacc acc02141; CHECK-BE-NEXT:    stxv vs1, 16(r7)2142; CHECK-BE-NEXT:    stxv vs0, 0(r7)2143; CHECK-BE-NEXT:    stxv vs3, 48(r7)2144; CHECK-BE-NEXT:    stxv vs2, 32(r7)2145; CHECK-BE-NEXT:    blr2146;2147; CHECK-WACC-LABEL: test31:2148; CHECK-WACC:       # %bb.0: # %entry2149; CHECK-WACC-NEXT:    lxv v5, 0(r3)2150; CHECK-WACC-NEXT:    lxv v1, 32(r3)2151; CHECK-WACC-NEXT:    lxv v4, 16(r3)2152; CHECK-WACC-NEXT:    lxv v0, 48(r3)2153; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02154; CHECK-WACC-NEXT:    pmxvf32gernp wacc0, v2, v2, 0, 02155; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02156; CHECK-WACC-NEXT:    stxv v4, 48(r7)2157; CHECK-WACC-NEXT:    stxv v5, 32(r7)2158; CHECK-WACC-NEXT:    stxv v2, 16(r7)2159; CHECK-WACC-NEXT:    stxv v3, 0(r7)2160; CHECK-WACC-NEXT:    blr2161;2162; CHECK-BE-WACC-LABEL: test31:2163; CHECK-BE-WACC:       # %bb.0: # %entry2164; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2165; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2166; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2167; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2168; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02169; CHECK-BE-WACC-NEXT:    pmxvf32gernp wacc0, v2, v2, 0, 02170; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02171; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2172; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2173; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2174; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2175; CHECK-BE-WACC-NEXT:    blr2176entry:2177  %0 = load <512 x i1>, ptr %vqp, align 642178  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)2179  store <512 x i1> %1, ptr %resp, align 642180  ret void2181}2182 2183 2184declare <512 x i1> @llvm.ppc.mma.pmxvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)2185 2186define void @test32(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2187; CHECK-LABEL: test32:2188; CHECK:       # %bb.0: # %entry2189; CHECK-NEXT:    lxv vs3, 0(r3)2190; CHECK-NEXT:    lxv vs2, 16(r3)2191; CHECK-NEXT:    lxv vs1, 32(r3)2192; CHECK-NEXT:    lxv vs0, 48(r3)2193; CHECK-NEXT:    xxmtacc acc02194; CHECK-NEXT:    pmxvf32gernn acc0, v2, v2, 0, 02195; CHECK-NEXT:    xxmfacc acc02196; CHECK-NEXT:    stxv vs0, 48(r7)2197; CHECK-NEXT:    stxv vs1, 32(r7)2198; CHECK-NEXT:    stxv vs2, 16(r7)2199; CHECK-NEXT:    stxv vs3, 0(r7)2200; CHECK-NEXT:    blr2201;2202; CHECK-BE-LABEL: test32:2203; CHECK-BE:       # %bb.0: # %entry2204; CHECK-BE-NEXT:    lxv vs3, 48(r3)2205; CHECK-BE-NEXT:    lxv vs2, 32(r3)2206; CHECK-BE-NEXT:    lxv vs1, 16(r3)2207; CHECK-BE-NEXT:    lxv vs0, 0(r3)2208; CHECK-BE-NEXT:    xxmtacc acc02209; CHECK-BE-NEXT:    pmxvf32gernn acc0, v2, v2, 0, 02210; CHECK-BE-NEXT:    xxmfacc acc02211; CHECK-BE-NEXT:    stxv vs1, 16(r7)2212; CHECK-BE-NEXT:    stxv vs0, 0(r7)2213; CHECK-BE-NEXT:    stxv vs3, 48(r7)2214; CHECK-BE-NEXT:    stxv vs2, 32(r7)2215; CHECK-BE-NEXT:    blr2216;2217; CHECK-WACC-LABEL: test32:2218; CHECK-WACC:       # %bb.0: # %entry2219; CHECK-WACC-NEXT:    lxv v5, 0(r3)2220; CHECK-WACC-NEXT:    lxv v1, 32(r3)2221; CHECK-WACC-NEXT:    lxv v4, 16(r3)2222; CHECK-WACC-NEXT:    lxv v0, 48(r3)2223; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02224; CHECK-WACC-NEXT:    pmxvf32gernn wacc0, v2, v2, 0, 02225; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02226; CHECK-WACC-NEXT:    stxv v4, 48(r7)2227; CHECK-WACC-NEXT:    stxv v5, 32(r7)2228; CHECK-WACC-NEXT:    stxv v2, 16(r7)2229; CHECK-WACC-NEXT:    stxv v3, 0(r7)2230; CHECK-WACC-NEXT:    blr2231;2232; CHECK-BE-WACC-LABEL: test32:2233; CHECK-BE-WACC:       # %bb.0: # %entry2234; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2235; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2236; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2237; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2238; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02239; CHECK-BE-WACC-NEXT:    pmxvf32gernn wacc0, v2, v2, 0, 02240; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02241; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2242; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2243; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2244; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2245; CHECK-BE-WACC-NEXT:    blr2246entry:2247  %0 = load <512 x i1>, ptr %vqp, align 642248  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0)2249  store <512 x i1> %1, ptr %resp, align 642250  ret void2251}2252 2253 2254declare <512 x i1> @llvm.ppc.mma.pmxvf32gernn(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32)2255 2256define void @test33(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2257; CHECK-LABEL: test33:2258; CHECK:       # %bb.0: # %entry2259; CHECK-NEXT:    lxv v4, 16(r4)2260; CHECK-NEXT:    lxv v5, 0(r4)2261; CHECK-NEXT:    xvf64ger acc0, vsp36, v22262; CHECK-NEXT:    xxmfacc acc02263; CHECK-NEXT:    stxv vs0, 48(r7)2264; CHECK-NEXT:    stxv vs1, 32(r7)2265; CHECK-NEXT:    stxv vs2, 16(r7)2266; CHECK-NEXT:    stxv vs3, 0(r7)2267; CHECK-NEXT:    blr2268;2269; CHECK-BE-LABEL: test33:2270; CHECK-BE:       # %bb.0: # %entry2271; CHECK-BE-NEXT:    lxv v4, 0(r4)2272; CHECK-BE-NEXT:    lxv v5, 16(r4)2273; CHECK-BE-NEXT:    xvf64ger acc0, vsp36, v22274; CHECK-BE-NEXT:    xxmfacc acc02275; CHECK-BE-NEXT:    stxv vs1, 16(r7)2276; CHECK-BE-NEXT:    stxv vs0, 0(r7)2277; CHECK-BE-NEXT:    stxv vs3, 48(r7)2278; CHECK-BE-NEXT:    stxv vs2, 32(r7)2279; CHECK-BE-NEXT:    blr2280;2281; CHECK-WACC-LABEL: test33:2282; CHECK-WACC:       # %bb.0: # %entry2283; CHECK-WACC-NEXT:    lxv v4, 16(r4)2284; CHECK-WACC-NEXT:    lxv v5, 0(r4)2285; CHECK-WACC-NEXT:    xvf64ger wacc0, vsp36, v22286; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02287; CHECK-WACC-NEXT:    stxv v4, 48(r7)2288; CHECK-WACC-NEXT:    stxv v5, 32(r7)2289; CHECK-WACC-NEXT:    stxv v2, 16(r7)2290; CHECK-WACC-NEXT:    stxv v3, 0(r7)2291; CHECK-WACC-NEXT:    blr2292;2293; CHECK-BE-WACC-LABEL: test33:2294; CHECK-BE-WACC:       # %bb.0: # %entry2295; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2296; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2297; CHECK-BE-WACC-NEXT:    xvf64ger wacc0, vsp36, v22298; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02299; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2300; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2301; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2302; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2303; CHECK-BE-WACC-NEXT:    blr2304entry:2305  %0 = load <256 x i1>, ptr %vpp, align 322306  %1 = tail call <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1> %0, <16 x i8> %vc)2307  store <512 x i1> %1, ptr %resp, align 642308  ret void2309}2310 2311 2312declare <512 x i1> @llvm.ppc.mma.xvf64ger(<256 x i1>, <16 x i8>)2313 2314define void @test34(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2315; CHECK-LABEL: test34:2316; CHECK:       # %bb.0: # %entry2317; CHECK-NEXT:    lxv vs3, 0(r3)2318; CHECK-NEXT:    lxv vs2, 16(r3)2319; CHECK-NEXT:    lxv vs1, 32(r3)2320; CHECK-NEXT:    lxv vs0, 48(r3)2321; CHECK-NEXT:    lxv v4, 16(r4)2322; CHECK-NEXT:    xxmtacc acc02323; CHECK-NEXT:    lxv v5, 0(r4)2324; CHECK-NEXT:    xvf64gerpp acc0, vsp36, v22325; CHECK-NEXT:    xxmfacc acc02326; CHECK-NEXT:    stxv vs0, 48(r7)2327; CHECK-NEXT:    stxv vs1, 32(r7)2328; CHECK-NEXT:    stxv vs2, 16(r7)2329; CHECK-NEXT:    stxv vs3, 0(r7)2330; CHECK-NEXT:    blr2331;2332; CHECK-BE-LABEL: test34:2333; CHECK-BE:       # %bb.0: # %entry2334; CHECK-BE-NEXT:    lxv vs3, 48(r3)2335; CHECK-BE-NEXT:    lxv vs2, 32(r3)2336; CHECK-BE-NEXT:    lxv vs1, 16(r3)2337; CHECK-BE-NEXT:    lxv vs0, 0(r3)2338; CHECK-BE-NEXT:    lxv v4, 0(r4)2339; CHECK-BE-NEXT:    xxmtacc acc02340; CHECK-BE-NEXT:    lxv v5, 16(r4)2341; CHECK-BE-NEXT:    xvf64gerpp acc0, vsp36, v22342; CHECK-BE-NEXT:    xxmfacc acc02343; CHECK-BE-NEXT:    stxv vs1, 16(r7)2344; CHECK-BE-NEXT:    stxv vs0, 0(r7)2345; CHECK-BE-NEXT:    stxv vs3, 48(r7)2346; CHECK-BE-NEXT:    stxv vs2, 32(r7)2347; CHECK-BE-NEXT:    blr2348;2349; CHECK-WACC-LABEL: test34:2350; CHECK-WACC:       # %bb.0: # %entry2351; CHECK-WACC-NEXT:    lxv v5, 0(r3)2352; CHECK-WACC-NEXT:    lxv v1, 32(r3)2353; CHECK-WACC-NEXT:    lxv v4, 16(r3)2354; CHECK-WACC-NEXT:    lxv v0, 48(r3)2355; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02356; CHECK-WACC-NEXT:    lxv v4, 16(r4)2357; CHECK-WACC-NEXT:    lxv v5, 0(r4)2358; CHECK-WACC-NEXT:    xvf64gerpp wacc0, vsp36, v22359; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02360; CHECK-WACC-NEXT:    stxv v4, 48(r7)2361; CHECK-WACC-NEXT:    stxv v5, 32(r7)2362; CHECK-WACC-NEXT:    stxv v2, 16(r7)2363; CHECK-WACC-NEXT:    stxv v3, 0(r7)2364; CHECK-WACC-NEXT:    blr2365;2366; CHECK-BE-WACC-LABEL: test34:2367; CHECK-BE-WACC:       # %bb.0: # %entry2368; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2369; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2370; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2371; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2372; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02373; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2374; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2375; CHECK-BE-WACC-NEXT:    xvf64gerpp wacc0, vsp36, v22376; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02377; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2378; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2379; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2380; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2381; CHECK-BE-WACC-NEXT:    blr2382entry:2383  %0 = load <512 x i1>, ptr %vqp, align 642384  %1 = load <256 x i1>, ptr %vpp, align 322385  %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)2386  store <512 x i1> %2, ptr %resp, align 642387  ret void2388}2389 2390 2391declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)2392 2393define void @test35(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2394; CHECK-LABEL: test35:2395; CHECK:       # %bb.0: # %entry2396; CHECK-NEXT:    lxv vs3, 0(r3)2397; CHECK-NEXT:    lxv vs2, 16(r3)2398; CHECK-NEXT:    lxv vs1, 32(r3)2399; CHECK-NEXT:    lxv vs0, 48(r3)2400; CHECK-NEXT:    lxv v4, 16(r4)2401; CHECK-NEXT:    xxmtacc acc02402; CHECK-NEXT:    lxv v5, 0(r4)2403; CHECK-NEXT:    xvf64gerpn acc0, vsp36, v22404; CHECK-NEXT:    xxmfacc acc02405; CHECK-NEXT:    stxv vs0, 48(r7)2406; CHECK-NEXT:    stxv vs1, 32(r7)2407; CHECK-NEXT:    stxv vs2, 16(r7)2408; CHECK-NEXT:    stxv vs3, 0(r7)2409; CHECK-NEXT:    blr2410;2411; CHECK-BE-LABEL: test35:2412; CHECK-BE:       # %bb.0: # %entry2413; CHECK-BE-NEXT:    lxv vs3, 48(r3)2414; CHECK-BE-NEXT:    lxv vs2, 32(r3)2415; CHECK-BE-NEXT:    lxv vs1, 16(r3)2416; CHECK-BE-NEXT:    lxv vs0, 0(r3)2417; CHECK-BE-NEXT:    lxv v4, 0(r4)2418; CHECK-BE-NEXT:    xxmtacc acc02419; CHECK-BE-NEXT:    lxv v5, 16(r4)2420; CHECK-BE-NEXT:    xvf64gerpn acc0, vsp36, v22421; CHECK-BE-NEXT:    xxmfacc acc02422; CHECK-BE-NEXT:    stxv vs1, 16(r7)2423; CHECK-BE-NEXT:    stxv vs0, 0(r7)2424; CHECK-BE-NEXT:    stxv vs3, 48(r7)2425; CHECK-BE-NEXT:    stxv vs2, 32(r7)2426; CHECK-BE-NEXT:    blr2427;2428; CHECK-WACC-LABEL: test35:2429; CHECK-WACC:       # %bb.0: # %entry2430; CHECK-WACC-NEXT:    lxv v5, 0(r3)2431; CHECK-WACC-NEXT:    lxv v1, 32(r3)2432; CHECK-WACC-NEXT:    lxv v4, 16(r3)2433; CHECK-WACC-NEXT:    lxv v0, 48(r3)2434; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02435; CHECK-WACC-NEXT:    lxv v4, 16(r4)2436; CHECK-WACC-NEXT:    lxv v5, 0(r4)2437; CHECK-WACC-NEXT:    xvf64gerpn wacc0, vsp36, v22438; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02439; CHECK-WACC-NEXT:    stxv v4, 48(r7)2440; CHECK-WACC-NEXT:    stxv v5, 32(r7)2441; CHECK-WACC-NEXT:    stxv v2, 16(r7)2442; CHECK-WACC-NEXT:    stxv v3, 0(r7)2443; CHECK-WACC-NEXT:    blr2444;2445; CHECK-BE-WACC-LABEL: test35:2446; CHECK-BE-WACC:       # %bb.0: # %entry2447; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2448; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2449; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2450; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2451; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02452; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2453; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2454; CHECK-BE-WACC-NEXT:    xvf64gerpn wacc0, vsp36, v22455; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02456; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2457; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2458; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2459; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2460; CHECK-BE-WACC-NEXT:    blr2461entry:2462  %0 = load <512 x i1>, ptr %vqp, align 642463  %1 = load <256 x i1>, ptr %vpp, align 322464  %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)2465  store <512 x i1> %2, ptr %resp, align 642466  ret void2467}2468 2469 2470declare <512 x i1> @llvm.ppc.mma.xvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>)2471 2472define void @test36(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2473; CHECK-LABEL: test36:2474; CHECK:       # %bb.0: # %entry2475; CHECK-NEXT:    lxv vs3, 0(r3)2476; CHECK-NEXT:    lxv vs2, 16(r3)2477; CHECK-NEXT:    lxv vs1, 32(r3)2478; CHECK-NEXT:    lxv vs0, 48(r3)2479; CHECK-NEXT:    lxv v4, 16(r4)2480; CHECK-NEXT:    xxmtacc acc02481; CHECK-NEXT:    lxv v5, 0(r4)2482; CHECK-NEXT:    xvf64gernp acc0, vsp36, v22483; CHECK-NEXT:    xxmfacc acc02484; CHECK-NEXT:    stxv vs0, 48(r7)2485; CHECK-NEXT:    stxv vs1, 32(r7)2486; CHECK-NEXT:    stxv vs2, 16(r7)2487; CHECK-NEXT:    stxv vs3, 0(r7)2488; CHECK-NEXT:    blr2489;2490; CHECK-BE-LABEL: test36:2491; CHECK-BE:       # %bb.0: # %entry2492; CHECK-BE-NEXT:    lxv vs3, 48(r3)2493; CHECK-BE-NEXT:    lxv vs2, 32(r3)2494; CHECK-BE-NEXT:    lxv vs1, 16(r3)2495; CHECK-BE-NEXT:    lxv vs0, 0(r3)2496; CHECK-BE-NEXT:    lxv v4, 0(r4)2497; CHECK-BE-NEXT:    xxmtacc acc02498; CHECK-BE-NEXT:    lxv v5, 16(r4)2499; CHECK-BE-NEXT:    xvf64gernp acc0, vsp36, v22500; CHECK-BE-NEXT:    xxmfacc acc02501; CHECK-BE-NEXT:    stxv vs1, 16(r7)2502; CHECK-BE-NEXT:    stxv vs0, 0(r7)2503; CHECK-BE-NEXT:    stxv vs3, 48(r7)2504; CHECK-BE-NEXT:    stxv vs2, 32(r7)2505; CHECK-BE-NEXT:    blr2506;2507; CHECK-WACC-LABEL: test36:2508; CHECK-WACC:       # %bb.0: # %entry2509; CHECK-WACC-NEXT:    lxv v5, 0(r3)2510; CHECK-WACC-NEXT:    lxv v1, 32(r3)2511; CHECK-WACC-NEXT:    lxv v4, 16(r3)2512; CHECK-WACC-NEXT:    lxv v0, 48(r3)2513; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02514; CHECK-WACC-NEXT:    lxv v4, 16(r4)2515; CHECK-WACC-NEXT:    lxv v5, 0(r4)2516; CHECK-WACC-NEXT:    xvf64gernp wacc0, vsp36, v22517; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02518; CHECK-WACC-NEXT:    stxv v4, 48(r7)2519; CHECK-WACC-NEXT:    stxv v5, 32(r7)2520; CHECK-WACC-NEXT:    stxv v2, 16(r7)2521; CHECK-WACC-NEXT:    stxv v3, 0(r7)2522; CHECK-WACC-NEXT:    blr2523;2524; CHECK-BE-WACC-LABEL: test36:2525; CHECK-BE-WACC:       # %bb.0: # %entry2526; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2527; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2528; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2529; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2530; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02531; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2532; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2533; CHECK-BE-WACC-NEXT:    xvf64gernp wacc0, vsp36, v22534; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02535; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2536; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2537; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2538; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2539; CHECK-BE-WACC-NEXT:    blr2540entry:2541  %0 = load <512 x i1>, ptr %vqp, align 642542  %1 = load <256 x i1>, ptr %vpp, align 322543  %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)2544  store <512 x i1> %2, ptr %resp, align 642545  ret void2546}2547 2548 2549declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)2550 2551define void @test37(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2552; CHECK-LABEL: test37:2553; CHECK:       # %bb.0: # %entry2554; CHECK-NEXT:    lxv vs3, 0(r3)2555; CHECK-NEXT:    lxv vs2, 16(r3)2556; CHECK-NEXT:    lxv vs1, 32(r3)2557; CHECK-NEXT:    lxv vs0, 48(r3)2558; CHECK-NEXT:    lxv v4, 16(r4)2559; CHECK-NEXT:    xxmtacc acc02560; CHECK-NEXT:    lxv v5, 0(r4)2561; CHECK-NEXT:    xvf64gernn acc0, vsp36, v22562; CHECK-NEXT:    xxmfacc acc02563; CHECK-NEXT:    stxv vs0, 48(r7)2564; CHECK-NEXT:    stxv vs1, 32(r7)2565; CHECK-NEXT:    stxv vs2, 16(r7)2566; CHECK-NEXT:    stxv vs3, 0(r7)2567; CHECK-NEXT:    blr2568;2569; CHECK-BE-LABEL: test37:2570; CHECK-BE:       # %bb.0: # %entry2571; CHECK-BE-NEXT:    lxv vs3, 48(r3)2572; CHECK-BE-NEXT:    lxv vs2, 32(r3)2573; CHECK-BE-NEXT:    lxv vs1, 16(r3)2574; CHECK-BE-NEXT:    lxv vs0, 0(r3)2575; CHECK-BE-NEXT:    lxv v4, 0(r4)2576; CHECK-BE-NEXT:    xxmtacc acc02577; CHECK-BE-NEXT:    lxv v5, 16(r4)2578; CHECK-BE-NEXT:    xvf64gernn acc0, vsp36, v22579; CHECK-BE-NEXT:    xxmfacc acc02580; CHECK-BE-NEXT:    stxv vs1, 16(r7)2581; CHECK-BE-NEXT:    stxv vs0, 0(r7)2582; CHECK-BE-NEXT:    stxv vs3, 48(r7)2583; CHECK-BE-NEXT:    stxv vs2, 32(r7)2584; CHECK-BE-NEXT:    blr2585;2586; CHECK-WACC-LABEL: test37:2587; CHECK-WACC:       # %bb.0: # %entry2588; CHECK-WACC-NEXT:    lxv v5, 0(r3)2589; CHECK-WACC-NEXT:    lxv v1, 32(r3)2590; CHECK-WACC-NEXT:    lxv v4, 16(r3)2591; CHECK-WACC-NEXT:    lxv v0, 48(r3)2592; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02593; CHECK-WACC-NEXT:    lxv v4, 16(r4)2594; CHECK-WACC-NEXT:    lxv v5, 0(r4)2595; CHECK-WACC-NEXT:    xvf64gernn wacc0, vsp36, v22596; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02597; CHECK-WACC-NEXT:    stxv v4, 48(r7)2598; CHECK-WACC-NEXT:    stxv v5, 32(r7)2599; CHECK-WACC-NEXT:    stxv v2, 16(r7)2600; CHECK-WACC-NEXT:    stxv v3, 0(r7)2601; CHECK-WACC-NEXT:    blr2602;2603; CHECK-BE-WACC-LABEL: test37:2604; CHECK-BE-WACC:       # %bb.0: # %entry2605; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2606; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2607; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2608; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2609; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02610; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2611; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2612; CHECK-BE-WACC-NEXT:    xvf64gernn wacc0, vsp36, v22613; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02614; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2615; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2616; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2617; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2618; CHECK-BE-WACC-NEXT:    blr2619entry:2620  %0 = load <512 x i1>, ptr %vqp, align 642621  %1 = load <256 x i1>, ptr %vpp, align 322622  %2 = tail call <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc)2623  store <512 x i1> %2, ptr %resp, align 642624  ret void2625}2626 2627 2628declare <512 x i1> @llvm.ppc.mma.xvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>)2629 2630define void @test38(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2631; CHECK-LABEL: test38:2632; CHECK:       # %bb.0: # %entry2633; CHECK-NEXT:    lxv v4, 16(r4)2634; CHECK-NEXT:    lxv v5, 0(r4)2635; CHECK-NEXT:    pmxvf64ger acc0, vsp36, v2, 0, 02636; CHECK-NEXT:    xxmfacc acc02637; CHECK-NEXT:    stxv vs0, 48(r7)2638; CHECK-NEXT:    stxv vs1, 32(r7)2639; CHECK-NEXT:    stxv vs2, 16(r7)2640; CHECK-NEXT:    stxv vs3, 0(r7)2641; CHECK-NEXT:    blr2642;2643; CHECK-BE-LABEL: test38:2644; CHECK-BE:       # %bb.0: # %entry2645; CHECK-BE-NEXT:    lxv v4, 0(r4)2646; CHECK-BE-NEXT:    lxv v5, 16(r4)2647; CHECK-BE-NEXT:    pmxvf64ger acc0, vsp36, v2, 0, 02648; CHECK-BE-NEXT:    xxmfacc acc02649; CHECK-BE-NEXT:    stxv vs1, 16(r7)2650; CHECK-BE-NEXT:    stxv vs0, 0(r7)2651; CHECK-BE-NEXT:    stxv vs3, 48(r7)2652; CHECK-BE-NEXT:    stxv vs2, 32(r7)2653; CHECK-BE-NEXT:    blr2654;2655; CHECK-WACC-LABEL: test38:2656; CHECK-WACC:       # %bb.0: # %entry2657; CHECK-WACC-NEXT:    lxv v4, 16(r4)2658; CHECK-WACC-NEXT:    lxv v5, 0(r4)2659; CHECK-WACC-NEXT:    pmxvf64ger wacc0, vsp36, v2, 0, 02660; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02661; CHECK-WACC-NEXT:    stxv v4, 48(r7)2662; CHECK-WACC-NEXT:    stxv v5, 32(r7)2663; CHECK-WACC-NEXT:    stxv v2, 16(r7)2664; CHECK-WACC-NEXT:    stxv v3, 0(r7)2665; CHECK-WACC-NEXT:    blr2666;2667; CHECK-BE-WACC-LABEL: test38:2668; CHECK-BE-WACC:       # %bb.0: # %entry2669; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2670; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2671; CHECK-BE-WACC-NEXT:    pmxvf64ger wacc0, vsp36, v2, 0, 02672; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02673; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2674; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2675; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2676; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2677; CHECK-BE-WACC-NEXT:    blr2678entry:2679  %0 = load <256 x i1>, ptr %vpp, align 322680  %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1> %0, <16 x i8> %vc, i32 0, i32 0)2681  store <512 x i1> %1, ptr %resp, align 642682  ret void2683}2684 2685 2686declare <512 x i1> @llvm.ppc.mma.pmxvf64ger(<256 x i1>, <16 x i8>, i32, i32)2687 2688define void @test39(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2689; CHECK-LABEL: test39:2690; CHECK:       # %bb.0: # %entry2691; CHECK-NEXT:    lxv vs3, 0(r3)2692; CHECK-NEXT:    lxv vs2, 16(r3)2693; CHECK-NEXT:    lxv vs1, 32(r3)2694; CHECK-NEXT:    lxv vs0, 48(r3)2695; CHECK-NEXT:    lxv v4, 16(r4)2696; CHECK-NEXT:    xxmtacc acc02697; CHECK-NEXT:    lxv v5, 0(r4)2698; CHECK-NEXT:    pmxvf64gerpp acc0, vsp36, v2, 0, 02699; CHECK-NEXT:    xxmfacc acc02700; CHECK-NEXT:    stxv vs0, 48(r7)2701; CHECK-NEXT:    stxv vs1, 32(r7)2702; CHECK-NEXT:    stxv vs2, 16(r7)2703; CHECK-NEXT:    stxv vs3, 0(r7)2704; CHECK-NEXT:    blr2705;2706; CHECK-BE-LABEL: test39:2707; CHECK-BE:       # %bb.0: # %entry2708; CHECK-BE-NEXT:    lxv vs3, 48(r3)2709; CHECK-BE-NEXT:    lxv vs2, 32(r3)2710; CHECK-BE-NEXT:    lxv vs1, 16(r3)2711; CHECK-BE-NEXT:    lxv vs0, 0(r3)2712; CHECK-BE-NEXT:    lxv v4, 0(r4)2713; CHECK-BE-NEXT:    xxmtacc acc02714; CHECK-BE-NEXT:    lxv v5, 16(r4)2715; CHECK-BE-NEXT:    pmxvf64gerpp acc0, vsp36, v2, 0, 02716; CHECK-BE-NEXT:    xxmfacc acc02717; CHECK-BE-NEXT:    stxv vs1, 16(r7)2718; CHECK-BE-NEXT:    stxv vs0, 0(r7)2719; CHECK-BE-NEXT:    stxv vs3, 48(r7)2720; CHECK-BE-NEXT:    stxv vs2, 32(r7)2721; CHECK-BE-NEXT:    blr2722;2723; CHECK-WACC-LABEL: test39:2724; CHECK-WACC:       # %bb.0: # %entry2725; CHECK-WACC-NEXT:    lxv v5, 0(r3)2726; CHECK-WACC-NEXT:    lxv v1, 32(r3)2727; CHECK-WACC-NEXT:    lxv v4, 16(r3)2728; CHECK-WACC-NEXT:    lxv v0, 48(r3)2729; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02730; CHECK-WACC-NEXT:    lxv v4, 16(r4)2731; CHECK-WACC-NEXT:    lxv v5, 0(r4)2732; CHECK-WACC-NEXT:    pmxvf64gerpp wacc0, vsp36, v2, 0, 02733; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02734; CHECK-WACC-NEXT:    stxv v4, 48(r7)2735; CHECK-WACC-NEXT:    stxv v5, 32(r7)2736; CHECK-WACC-NEXT:    stxv v2, 16(r7)2737; CHECK-WACC-NEXT:    stxv v3, 0(r7)2738; CHECK-WACC-NEXT:    blr2739;2740; CHECK-BE-WACC-LABEL: test39:2741; CHECK-BE-WACC:       # %bb.0: # %entry2742; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2743; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2744; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2745; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2746; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02747; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2748; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2749; CHECK-BE-WACC-NEXT:    pmxvf64gerpp wacc0, vsp36, v2, 0, 02750; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02751; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2752; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2753; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2754; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2755; CHECK-BE-WACC-NEXT:    blr2756entry:2757  %0 = load <512 x i1>, ptr %vqp, align 642758  %1 = load <256 x i1>, ptr %vpp, align 322759  %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)2760  store <512 x i1> %2, ptr %resp, align 642761  ret void2762}2763 2764 2765declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)2766 2767define void @test40(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2768; CHECK-LABEL: test40:2769; CHECK:       # %bb.0: # %entry2770; CHECK-NEXT:    lxv vs3, 0(r3)2771; CHECK-NEXT:    lxv vs2, 16(r3)2772; CHECK-NEXT:    lxv vs1, 32(r3)2773; CHECK-NEXT:    lxv vs0, 48(r3)2774; CHECK-NEXT:    lxv v4, 16(r4)2775; CHECK-NEXT:    xxmtacc acc02776; CHECK-NEXT:    lxv v5, 0(r4)2777; CHECK-NEXT:    pmxvf64gerpn acc0, vsp36, v2, 0, 02778; CHECK-NEXT:    xxmfacc acc02779; CHECK-NEXT:    stxv vs0, 48(r7)2780; CHECK-NEXT:    stxv vs1, 32(r7)2781; CHECK-NEXT:    stxv vs2, 16(r7)2782; CHECK-NEXT:    stxv vs3, 0(r7)2783; CHECK-NEXT:    blr2784;2785; CHECK-BE-LABEL: test40:2786; CHECK-BE:       # %bb.0: # %entry2787; CHECK-BE-NEXT:    lxv vs3, 48(r3)2788; CHECK-BE-NEXT:    lxv vs2, 32(r3)2789; CHECK-BE-NEXT:    lxv vs1, 16(r3)2790; CHECK-BE-NEXT:    lxv vs0, 0(r3)2791; CHECK-BE-NEXT:    lxv v4, 0(r4)2792; CHECK-BE-NEXT:    xxmtacc acc02793; CHECK-BE-NEXT:    lxv v5, 16(r4)2794; CHECK-BE-NEXT:    pmxvf64gerpn acc0, vsp36, v2, 0, 02795; CHECK-BE-NEXT:    xxmfacc acc02796; CHECK-BE-NEXT:    stxv vs1, 16(r7)2797; CHECK-BE-NEXT:    stxv vs0, 0(r7)2798; CHECK-BE-NEXT:    stxv vs3, 48(r7)2799; CHECK-BE-NEXT:    stxv vs2, 32(r7)2800; CHECK-BE-NEXT:    blr2801;2802; CHECK-WACC-LABEL: test40:2803; CHECK-WACC:       # %bb.0: # %entry2804; CHECK-WACC-NEXT:    lxv v5, 0(r3)2805; CHECK-WACC-NEXT:    lxv v1, 32(r3)2806; CHECK-WACC-NEXT:    lxv v4, 16(r3)2807; CHECK-WACC-NEXT:    lxv v0, 48(r3)2808; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02809; CHECK-WACC-NEXT:    lxv v4, 16(r4)2810; CHECK-WACC-NEXT:    lxv v5, 0(r4)2811; CHECK-WACC-NEXT:    pmxvf64gerpn wacc0, vsp36, v2, 0, 02812; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02813; CHECK-WACC-NEXT:    stxv v4, 48(r7)2814; CHECK-WACC-NEXT:    stxv v5, 32(r7)2815; CHECK-WACC-NEXT:    stxv v2, 16(r7)2816; CHECK-WACC-NEXT:    stxv v3, 0(r7)2817; CHECK-WACC-NEXT:    blr2818;2819; CHECK-BE-WACC-LABEL: test40:2820; CHECK-BE-WACC:       # %bb.0: # %entry2821; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2822; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2823; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2824; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2825; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02826; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2827; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2828; CHECK-BE-WACC-NEXT:    pmxvf64gerpn wacc0, vsp36, v2, 0, 02829; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02830; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2831; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2832; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2833; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2834; CHECK-BE-WACC-NEXT:    blr2835entry:2836  %0 = load <512 x i1>, ptr %vqp, align 642837  %1 = load <256 x i1>, ptr %vpp, align 322838  %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)2839  store <512 x i1> %2, ptr %resp, align 642840  ret void2841}2842 2843 2844declare <512 x i1> @llvm.ppc.mma.pmxvf64gerpn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)2845 2846define void @test41(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2847; CHECK-LABEL: test41:2848; CHECK:       # %bb.0: # %entry2849; CHECK-NEXT:    lxv vs3, 0(r3)2850; CHECK-NEXT:    lxv vs2, 16(r3)2851; CHECK-NEXT:    lxv vs1, 32(r3)2852; CHECK-NEXT:    lxv vs0, 48(r3)2853; CHECK-NEXT:    lxv v4, 16(r4)2854; CHECK-NEXT:    xxmtacc acc02855; CHECK-NEXT:    lxv v5, 0(r4)2856; CHECK-NEXT:    pmxvf64gernp acc0, vsp36, v2, 0, 02857; CHECK-NEXT:    xxmfacc acc02858; CHECK-NEXT:    stxv vs0, 48(r7)2859; CHECK-NEXT:    stxv vs1, 32(r7)2860; CHECK-NEXT:    stxv vs2, 16(r7)2861; CHECK-NEXT:    stxv vs3, 0(r7)2862; CHECK-NEXT:    blr2863;2864; CHECK-BE-LABEL: test41:2865; CHECK-BE:       # %bb.0: # %entry2866; CHECK-BE-NEXT:    lxv vs3, 48(r3)2867; CHECK-BE-NEXT:    lxv vs2, 32(r3)2868; CHECK-BE-NEXT:    lxv vs1, 16(r3)2869; CHECK-BE-NEXT:    lxv vs0, 0(r3)2870; CHECK-BE-NEXT:    lxv v4, 0(r4)2871; CHECK-BE-NEXT:    xxmtacc acc02872; CHECK-BE-NEXT:    lxv v5, 16(r4)2873; CHECK-BE-NEXT:    pmxvf64gernp acc0, vsp36, v2, 0, 02874; CHECK-BE-NEXT:    xxmfacc acc02875; CHECK-BE-NEXT:    stxv vs1, 16(r7)2876; CHECK-BE-NEXT:    stxv vs0, 0(r7)2877; CHECK-BE-NEXT:    stxv vs3, 48(r7)2878; CHECK-BE-NEXT:    stxv vs2, 32(r7)2879; CHECK-BE-NEXT:    blr2880;2881; CHECK-WACC-LABEL: test41:2882; CHECK-WACC:       # %bb.0: # %entry2883; CHECK-WACC-NEXT:    lxv v5, 0(r3)2884; CHECK-WACC-NEXT:    lxv v1, 32(r3)2885; CHECK-WACC-NEXT:    lxv v4, 16(r3)2886; CHECK-WACC-NEXT:    lxv v0, 48(r3)2887; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02888; CHECK-WACC-NEXT:    lxv v4, 16(r4)2889; CHECK-WACC-NEXT:    lxv v5, 0(r4)2890; CHECK-WACC-NEXT:    pmxvf64gernp wacc0, vsp36, v2, 0, 02891; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02892; CHECK-WACC-NEXT:    stxv v4, 48(r7)2893; CHECK-WACC-NEXT:    stxv v5, 32(r7)2894; CHECK-WACC-NEXT:    stxv v2, 16(r7)2895; CHECK-WACC-NEXT:    stxv v3, 0(r7)2896; CHECK-WACC-NEXT:    blr2897;2898; CHECK-BE-WACC-LABEL: test41:2899; CHECK-BE-WACC:       # %bb.0: # %entry2900; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2901; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2902; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2903; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2904; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02905; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2906; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2907; CHECK-BE-WACC-NEXT:    pmxvf64gernp wacc0, vsp36, v2, 0, 02908; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02909; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2910; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2911; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2912; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2913; CHECK-BE-WACC-NEXT:    blr2914entry:2915  %0 = load <512 x i1>, ptr %vqp, align 642916  %1 = load <256 x i1>, ptr %vpp, align 322917  %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)2918  store <512 x i1> %2, ptr %resp, align 642919  ret void2920}2921 2922 2923declare <512 x i1> @llvm.ppc.mma.pmxvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)2924 2925define void @test42(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {2926; CHECK-LABEL: test42:2927; CHECK:       # %bb.0: # %entry2928; CHECK-NEXT:    lxv vs3, 0(r3)2929; CHECK-NEXT:    lxv vs2, 16(r3)2930; CHECK-NEXT:    lxv vs1, 32(r3)2931; CHECK-NEXT:    lxv vs0, 48(r3)2932; CHECK-NEXT:    lxv v4, 16(r4)2933; CHECK-NEXT:    xxmtacc acc02934; CHECK-NEXT:    lxv v5, 0(r4)2935; CHECK-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 02936; CHECK-NEXT:    xxmfacc acc02937; CHECK-NEXT:    stxv vs0, 48(r7)2938; CHECK-NEXT:    stxv vs1, 32(r7)2939; CHECK-NEXT:    stxv vs2, 16(r7)2940; CHECK-NEXT:    stxv vs3, 0(r7)2941; CHECK-NEXT:    blr2942;2943; CHECK-BE-LABEL: test42:2944; CHECK-BE:       # %bb.0: # %entry2945; CHECK-BE-NEXT:    lxv vs3, 48(r3)2946; CHECK-BE-NEXT:    lxv vs2, 32(r3)2947; CHECK-BE-NEXT:    lxv vs1, 16(r3)2948; CHECK-BE-NEXT:    lxv vs0, 0(r3)2949; CHECK-BE-NEXT:    lxv v4, 0(r4)2950; CHECK-BE-NEXT:    xxmtacc acc02951; CHECK-BE-NEXT:    lxv v5, 16(r4)2952; CHECK-BE-NEXT:    pmxvf64gernn acc0, vsp36, v2, 0, 02953; CHECK-BE-NEXT:    xxmfacc acc02954; CHECK-BE-NEXT:    stxv vs1, 16(r7)2955; CHECK-BE-NEXT:    stxv vs0, 0(r7)2956; CHECK-BE-NEXT:    stxv vs3, 48(r7)2957; CHECK-BE-NEXT:    stxv vs2, 32(r7)2958; CHECK-BE-NEXT:    blr2959;2960; CHECK-WACC-LABEL: test42:2961; CHECK-WACC:       # %bb.0: # %entry2962; CHECK-WACC-NEXT:    lxv v5, 0(r3)2963; CHECK-WACC-NEXT:    lxv v1, 32(r3)2964; CHECK-WACC-NEXT:    lxv v4, 16(r3)2965; CHECK-WACC-NEXT:    lxv v0, 48(r3)2966; CHECK-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02967; CHECK-WACC-NEXT:    lxv v4, 16(r4)2968; CHECK-WACC-NEXT:    lxv v5, 0(r4)2969; CHECK-WACC-NEXT:    pmxvf64gernn wacc0, vsp36, v2, 0, 02970; CHECK-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02971; CHECK-WACC-NEXT:    stxv v4, 48(r7)2972; CHECK-WACC-NEXT:    stxv v5, 32(r7)2973; CHECK-WACC-NEXT:    stxv v2, 16(r7)2974; CHECK-WACC-NEXT:    stxv v3, 0(r7)2975; CHECK-WACC-NEXT:    blr2976;2977; CHECK-BE-WACC-LABEL: test42:2978; CHECK-BE-WACC:       # %bb.0: # %entry2979; CHECK-BE-WACC-NEXT:    lxv v5, 48(r3)2980; CHECK-BE-WACC-NEXT:    lxv v1, 16(r3)2981; CHECK-BE-WACC-NEXT:    lxv v4, 32(r3)2982; CHECK-BE-WACC-NEXT:    lxv v0, 0(r3)2983; CHECK-BE-WACC-NEXT:    dmxxinstdmr512 wacc0, vsp32, vsp36, 02984; CHECK-BE-WACC-NEXT:    lxv v4, 0(r4)2985; CHECK-BE-WACC-NEXT:    lxv v5, 16(r4)2986; CHECK-BE-WACC-NEXT:    pmxvf64gernn wacc0, vsp36, v2, 0, 02987; CHECK-BE-WACC-NEXT:    dmxxextfdmr512 vsp34, vsp36, wacc0, 02988; CHECK-BE-WACC-NEXT:    stxv v5, 48(r7)2989; CHECK-BE-WACC-NEXT:    stxv v4, 32(r7)2990; CHECK-BE-WACC-NEXT:    stxv v3, 16(r7)2991; CHECK-BE-WACC-NEXT:    stxv v2, 0(r7)2992; CHECK-BE-WACC-NEXT:    blr2993entry:2994  %0 = load <512 x i1>, ptr %vqp, align 642995  %1 = load <256 x i1>, ptr %vpp, align 322996  %2 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %1, <16 x i8> %vc, i32 0, i32 0)2997  store <512 x i1> %2, ptr %resp, align 642998  ret void2999}3000 3001 3002declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)3003