1176 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; This test is a copy of mma-intrinsics.ll except that it uses mcpu=future.3; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \4; RUN: -mcpu=future -ppc-asm-full-reg-names \5; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -mcpu=future -ppc-asm-full-reg-names \8; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE9; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \10; RUN: -mcpu=future -ppc-asm-full-reg-names \11; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O012; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \13; RUN: -mcpu=future -ppc-asm-full-reg-names \14; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0-BE15; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix- \16; RUN: -mcpu=future -vec-extabi \17; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX6418; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix- \19; RUN: -mcpu=future -vec-extabi \20; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX3221 22; TODO: This test is missing some of the tests from mma-intrinsics.ll because23; those tests do not work for mcpu=future. Once the fixes are in they24; should be added back to this file.25 26; assemble_acc27declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)28define void @ass_acc(ptr %ptr, <16 x i8> %vc) {29; CHECK-LABEL: ass_acc:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: vmr v3, v232; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 033; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 034; CHECK-NEXT: stxv v4, 48(r3)35; CHECK-NEXT: stxv v5, 32(r3)36; CHECK-NEXT: stxv v2, 16(r3)37; CHECK-NEXT: stxv v3, 0(r3)38; CHECK-NEXT: blr39;40; CHECK-BE-LABEL: ass_acc:41; CHECK-BE: # %bb.0: # %entry42; CHECK-BE-NEXT: vmr v3, v243; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 044; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 045; CHECK-BE-NEXT: stxv v5, 48(r3)46; CHECK-BE-NEXT: stxv v4, 32(r3)47; CHECK-BE-NEXT: stxv v3, 16(r3)48; CHECK-BE-NEXT: stxv v2, 0(r3)49; CHECK-BE-NEXT: blr50;51; CHECK-O0-LABEL: ass_acc:52; CHECK-O0: # %bb.0: # %entry53; CHECK-O0-NEXT: vmr v4, v254; CHECK-O0-NEXT: # implicit-def: $vsrp1755; CHECK-O0-NEXT: vmr v3, v456; CHECK-O0-NEXT: vmr v2, v457; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 058; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 059; CHECK-O0-NEXT: xxlor vs0, v4, v460; CHECK-O0-NEXT: stxv vs0, 48(r3)61; CHECK-O0-NEXT: xxlor vs0, v5, v562; CHECK-O0-NEXT: stxv vs0, 32(r3)63; CHECK-O0-NEXT: xxlor vs0, v2, v264; CHECK-O0-NEXT: stxv vs0, 16(r3)65; CHECK-O0-NEXT: xxlor vs0, v3, v366; CHECK-O0-NEXT: stxv vs0, 0(r3)67; CHECK-O0-NEXT: blr68;69; CHECK-O0-BE-LABEL: ass_acc:70; CHECK-O0-BE: # %bb.0: # %entry71; CHECK-O0-BE-NEXT: vmr v4, v272; CHECK-O0-BE-NEXT: # implicit-def: $vsrp1773; CHECK-O0-BE-NEXT: vmr v3, v474; CHECK-O0-BE-NEXT: vmr v2, v475; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp34, 076; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 077; CHECK-O0-BE-NEXT: xxlor vs0, v5, v578; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)79; CHECK-O0-BE-NEXT: xxlor vs0, v4, v480; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)81; CHECK-O0-BE-NEXT: xxlor vs0, v3, v382; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)83; CHECK-O0-BE-NEXT: xxlor vs0, v2, v284; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)85; CHECK-O0-BE-NEXT: blr86;87; CHECK-AIX64-LABEL: ass_acc:88; CHECK-AIX64: # %bb.0: # %entry89; CHECK-AIX64-NEXT: vmr 3, 290; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 34, 34, 091; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 092; CHECK-AIX64-NEXT: stxv 5, 48(3)93; CHECK-AIX64-NEXT: stxv 4, 32(3)94; CHECK-AIX64-NEXT: stxv 3, 16(3)95; CHECK-AIX64-NEXT: stxv 2, 0(3)96; CHECK-AIX64-NEXT: blr97;98; CHECK-AIX32-LABEL: ass_acc:99; CHECK-AIX32: # %bb.0: # %entry100; CHECK-AIX32-NEXT: vmr 3, 2101; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 34, 34, 0102; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0103; CHECK-AIX32-NEXT: stxv 5, 48(3)104; CHECK-AIX32-NEXT: stxv 4, 32(3)105; CHECK-AIX32-NEXT: stxv 3, 16(3)106; CHECK-AIX32-NEXT: stxv 2, 0(3)107; CHECK-AIX32-NEXT: blr108entry:109 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)110 store <512 x i1> %0, ptr %ptr, align 64111 ret void112}113 114; xxmtacc with a loaded and stored vector quad.115define void @ld_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {116; CHECK-LABEL: ld_st_xxmtacc:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: lxv v3, 0(r3)119; CHECK-NEXT: lxv v5, 32(r3)120; CHECK-NEXT: lxv v2, 16(r3)121; CHECK-NEXT: lxv v4, 48(r3)122; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0123; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0124; CHECK-NEXT: stxv v4, 48(r7)125; CHECK-NEXT: stxv v5, 32(r7)126; CHECK-NEXT: stxv v2, 16(r7)127; CHECK-NEXT: stxv v3, 0(r7)128; CHECK-NEXT: blr129;130; CHECK-BE-LABEL: ld_st_xxmtacc:131; CHECK-BE: # %bb.0: # %entry132; CHECK-BE-NEXT: lxv v3, 48(r3)133; CHECK-BE-NEXT: lxv v5, 16(r3)134; CHECK-BE-NEXT: lxv v2, 32(r3)135; CHECK-BE-NEXT: lxv v4, 0(r3)136; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0137; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0138; CHECK-BE-NEXT: stxv v5, 48(r7)139; CHECK-BE-NEXT: stxv v4, 32(r7)140; CHECK-BE-NEXT: stxv v3, 16(r7)141; CHECK-BE-NEXT: stxv v2, 0(r7)142; CHECK-BE-NEXT: blr143;144; CHECK-O0-LABEL: ld_st_xxmtacc:145; CHECK-O0: # %bb.0: # %entry146; CHECK-O0-NEXT: lxv vs0, 0(r3)147; CHECK-O0-NEXT: # implicit-def: $vsrp18148; CHECK-O0-NEXT: xxlor v5, vs0, vs0149; CHECK-O0-NEXT: lxv vs0, 16(r3)150; CHECK-O0-NEXT: xxlor v4, vs0, vs0151; CHECK-O0-NEXT: lxv vs0, 32(r3)152; CHECK-O0-NEXT: # implicit-def: $vsrp17153; CHECK-O0-NEXT: xxlor v3, vs0, vs0154; CHECK-O0-NEXT: lxv vs0, 48(r3)155; CHECK-O0-NEXT: xxlor v2, vs0, vs0156; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0157; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0158; CHECK-O0-NEXT: xxlor vs0, v4, v4159; CHECK-O0-NEXT: stxv vs0, 48(r7)160; CHECK-O0-NEXT: xxlor vs0, v5, v5161; CHECK-O0-NEXT: stxv vs0, 32(r7)162; CHECK-O0-NEXT: xxlor vs0, v2, v2163; CHECK-O0-NEXT: stxv vs0, 16(r7)164; CHECK-O0-NEXT: xxlor vs0, v3, v3165; CHECK-O0-NEXT: stxv vs0, 0(r7)166; CHECK-O0-NEXT: blr167;168; CHECK-O0-BE-LABEL: ld_st_xxmtacc:169; CHECK-O0-BE: # %bb.0: # %entry170; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)171; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18172; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0173; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)174; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0175; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)176; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17177; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0178; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)179; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0180; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0181; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0182; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5183; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)184; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4185; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)186; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3187; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)188; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2189; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)190; CHECK-O0-BE-NEXT: blr191;192; CHECK-AIX64-LABEL: ld_st_xxmtacc:193; CHECK-AIX64: # %bb.0: # %entry194; CHECK-AIX64-NEXT: lxv 3, 48(3)195; CHECK-AIX64-NEXT: lxv 5, 16(3)196; CHECK-AIX64-NEXT: lxv 2, 32(3)197; CHECK-AIX64-NEXT: lxv 4, 0(3)198; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 36, 34, 0199; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0200; CHECK-AIX64-NEXT: stxv 5, 48(5)201; CHECK-AIX64-NEXT: stxv 4, 32(5)202; CHECK-AIX64-NEXT: stxv 3, 16(5)203; CHECK-AIX64-NEXT: stxv 2, 0(5)204; CHECK-AIX64-NEXT: blr205;206; CHECK-AIX32-LABEL: ld_st_xxmtacc:207; CHECK-AIX32: # %bb.0: # %entry208; CHECK-AIX32-NEXT: lxv 3, 48(3)209; CHECK-AIX32-NEXT: lxv 5, 16(3)210; CHECK-AIX32-NEXT: lxv 2, 32(3)211; CHECK-AIX32-NEXT: lxv 4, 0(3)212; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 36, 34, 0213; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0214; CHECK-AIX32-NEXT: stxv 5, 48(5)215; CHECK-AIX32-NEXT: stxv 4, 32(5)216; CHECK-AIX32-NEXT: stxv 3, 16(5)217; CHECK-AIX32-NEXT: stxv 2, 0(5)218; CHECK-AIX32-NEXT: blr219entry:220 %0 = load <512 x i1>, ptr %vqp, align 64221 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)222 store <512 x i1> %1, ptr %resp, align 64223 ret void224}225 226declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)227 228; xxmtacc used with an instruction that is not a load or store.229define void @ld_op_st_xxmtacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {230; CHECK-LABEL: ld_op_st_xxmtacc:231; CHECK: # %bb.0: # %entry232; CHECK-NEXT: lxv v5, 0(r3)233; CHECK-NEXT: lxv v1, 32(r3)234; CHECK-NEXT: lxv v4, 16(r3)235; CHECK-NEXT: lxv v0, 48(r3)236; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0237; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2238; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0239; CHECK-NEXT: stxv v4, 48(r7)240; CHECK-NEXT: stxv v5, 32(r7)241; CHECK-NEXT: stxv v2, 16(r7)242; CHECK-NEXT: stxv v3, 0(r7)243; CHECK-NEXT: blr244;245; CHECK-BE-LABEL: ld_op_st_xxmtacc:246; CHECK-BE: # %bb.0: # %entry247; CHECK-BE-NEXT: lxv v5, 48(r3)248; CHECK-BE-NEXT: lxv v1, 16(r3)249; CHECK-BE-NEXT: lxv v4, 32(r3)250; CHECK-BE-NEXT: lxv v0, 0(r3)251; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0252; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2253; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0254; CHECK-BE-NEXT: stxv v5, 48(r7)255; CHECK-BE-NEXT: stxv v4, 32(r7)256; CHECK-BE-NEXT: stxv v3, 16(r7)257; CHECK-BE-NEXT: stxv v2, 0(r7)258; CHECK-BE-NEXT: blr259;260; CHECK-O0-LABEL: ld_op_st_xxmtacc:261; CHECK-O0: # %bb.0: # %entry262; CHECK-O0-NEXT: lxv vs0, 0(r3)263; CHECK-O0-NEXT: # implicit-def: $vsrp16264; CHECK-O0-NEXT: xxlor v1, vs0, vs0265; CHECK-O0-NEXT: lxv vs0, 16(r3)266; CHECK-O0-NEXT: xxlor v0, vs0, vs0267; CHECK-O0-NEXT: lxv vs0, 32(r3)268; CHECK-O0-NEXT: # implicit-def: $vsrp18269; CHECK-O0-NEXT: xxlor v5, vs0, vs0270; CHECK-O0-NEXT: lxv vs0, 48(r3)271; CHECK-O0-NEXT: xxlor v4, vs0, vs0272; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0273; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2274; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0275; CHECK-O0-NEXT: xxlor vs0, v4, v4276; CHECK-O0-NEXT: stxv vs0, 48(r7)277; CHECK-O0-NEXT: xxlor vs0, v5, v5278; CHECK-O0-NEXT: stxv vs0, 32(r7)279; CHECK-O0-NEXT: xxlor vs0, v2, v2280; CHECK-O0-NEXT: stxv vs0, 16(r7)281; CHECK-O0-NEXT: xxlor vs0, v3, v3282; CHECK-O0-NEXT: stxv vs0, 0(r7)283; CHECK-O0-NEXT: blr284;285; CHECK-O0-BE-LABEL: ld_op_st_xxmtacc:286; CHECK-O0-BE: # %bb.0: # %entry287; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)288; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16289; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs0290; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)291; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs0292; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)293; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18294; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0295; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)296; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0297; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0298; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2299; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0300; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5301; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)302; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4303; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)304; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3305; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)306; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2307; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)308; CHECK-O0-BE-NEXT: blr309;310; CHECK-AIX64-LABEL: ld_op_st_xxmtacc:311; CHECK-AIX64: # %bb.0: # %entry312; CHECK-AIX64-NEXT: lxv 5, 48(3)313; CHECK-AIX64-NEXT: lxv 1, 16(3)314; CHECK-AIX64-NEXT: lxv 4, 32(3)315; CHECK-AIX64-NEXT: lxv 0, 0(3)316; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 0317; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2318; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0319; CHECK-AIX64-NEXT: stxv 5, 48(5)320; CHECK-AIX64-NEXT: stxv 4, 32(5)321; CHECK-AIX64-NEXT: stxv 3, 16(5)322; CHECK-AIX64-NEXT: stxv 2, 0(5)323; CHECK-AIX64-NEXT: blr324;325; CHECK-AIX32-LABEL: ld_op_st_xxmtacc:326; CHECK-AIX32: # %bb.0: # %entry327; CHECK-AIX32-NEXT: lxv 5, 48(3)328; CHECK-AIX32-NEXT: lxv 1, 16(3)329; CHECK-AIX32-NEXT: lxv 4, 32(3)330; CHECK-AIX32-NEXT: lxv 0, 0(3)331; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 0332; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2333; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0334; CHECK-AIX32-NEXT: stxv 5, 48(5)335; CHECK-AIX32-NEXT: stxv 4, 32(5)336; CHECK-AIX32-NEXT: stxv 3, 16(5)337; CHECK-AIX32-NEXT: stxv 2, 0(5)338; CHECK-AIX32-NEXT: blr339entry:340 %0 = load <512 x i1>, ptr %vqp, align 64341 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)342 %2 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)343 store <512 x i1> %2, ptr %resp, align 64344 ret void345}346 347declare <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1>, <16 x i8>, <16 x i8>)348 349; xxmfacc with a loaded and stored vector quad.350define void @ld_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {351; CHECK-LABEL: ld_st_xxmfacc:352; CHECK: # %bb.0: # %entry353; CHECK-NEXT: lxv v3, 0(r3)354; CHECK-NEXT: lxv v5, 32(r3)355; CHECK-NEXT: lxv v2, 16(r3)356; CHECK-NEXT: lxv v4, 48(r3)357; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0358; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0359; CHECK-NEXT: stxv v4, 48(r3)360; CHECK-NEXT: stxv v5, 32(r3)361; CHECK-NEXT: stxv v2, 16(r3)362; CHECK-NEXT: stxv v3, 0(r3)363; CHECK-NEXT: stxv v4, 48(r7)364; CHECK-NEXT: stxv v5, 32(r7)365; CHECK-NEXT: stxv v2, 16(r7)366; CHECK-NEXT: stxv v3, 0(r7)367; CHECK-NEXT: blr368;369; CHECK-BE-LABEL: ld_st_xxmfacc:370; CHECK-BE: # %bb.0: # %entry371; CHECK-BE-NEXT: lxv v3, 48(r3)372; CHECK-BE-NEXT: lxv v5, 16(r3)373; CHECK-BE-NEXT: lxv v2, 32(r3)374; CHECK-BE-NEXT: lxv v4, 0(r3)375; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp34, 0376; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0377; CHECK-BE-NEXT: stxv v5, 48(r3)378; CHECK-BE-NEXT: stxv v4, 32(r3)379; CHECK-BE-NEXT: stxv v3, 16(r3)380; CHECK-BE-NEXT: stxv v2, 0(r3)381; CHECK-BE-NEXT: stxv v5, 48(r7)382; CHECK-BE-NEXT: stxv v4, 32(r7)383; CHECK-BE-NEXT: stxv v3, 16(r7)384; CHECK-BE-NEXT: stxv v2, 0(r7)385; CHECK-BE-NEXT: blr386;387; CHECK-O0-LABEL: ld_st_xxmfacc:388; CHECK-O0: # %bb.0: # %entry389; CHECK-O0-NEXT: lxv vs0, 0(r3)390; CHECK-O0-NEXT: # implicit-def: $vsrp18391; CHECK-O0-NEXT: xxlor v5, vs0, vs0392; CHECK-O0-NEXT: lxv vs0, 16(r3)393; CHECK-O0-NEXT: xxlor v4, vs0, vs0394; CHECK-O0-NEXT: lxv vs0, 32(r3)395; CHECK-O0-NEXT: # implicit-def: $vsrp17396; CHECK-O0-NEXT: xxlor v3, vs0, vs0397; CHECK-O0-NEXT: lxv vs0, 48(r3)398; CHECK-O0-NEXT: xxlor v2, vs0, vs0399; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0400; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0401; CHECK-O0-NEXT: xxlor vs3, v4, v4402; CHECK-O0-NEXT: stxv vs3, 48(r3)403; CHECK-O0-NEXT: xxlor vs2, v5, v5404; CHECK-O0-NEXT: stxv vs2, 32(r3)405; CHECK-O0-NEXT: xxlor vs1, v2, v2406; CHECK-O0-NEXT: stxv vs1, 16(r3)407; CHECK-O0-NEXT: xxlor vs0, v3, v3408; CHECK-O0-NEXT: stxv vs0, 0(r3)409; CHECK-O0-NEXT: stxv vs3, 48(r7)410; CHECK-O0-NEXT: stxv vs2, 32(r7)411; CHECK-O0-NEXT: stxv vs1, 16(r7)412; CHECK-O0-NEXT: stxv vs0, 0(r7)413; CHECK-O0-NEXT: blr414;415; CHECK-O0-BE-LABEL: ld_st_xxmfacc:416; CHECK-O0-BE: # %bb.0: # %entry417; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)418; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18419; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0420; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)421; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0422; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)423; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17424; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs0425; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)426; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs0427; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp36, 0428; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0429; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5430; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)431; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4432; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)433; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3434; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)435; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2436; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)437; CHECK-O0-BE-NEXT: stxv vs3, 48(r7)438; CHECK-O0-BE-NEXT: stxv vs2, 32(r7)439; CHECK-O0-BE-NEXT: stxv vs1, 16(r7)440; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)441; CHECK-O0-BE-NEXT: blr442;443; CHECK-AIX64-LABEL: ld_st_xxmfacc:444; CHECK-AIX64: # %bb.0: # %entry445; CHECK-AIX64-NEXT: lxv 3, 48(3)446; CHECK-AIX64-NEXT: lxv 5, 16(3)447; CHECK-AIX64-NEXT: lxv 2, 32(3)448; CHECK-AIX64-NEXT: lxv 4, 0(3)449; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 36, 34, 0450; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0451; CHECK-AIX64-NEXT: stxv 5, 48(3)452; CHECK-AIX64-NEXT: stxv 4, 32(3)453; CHECK-AIX64-NEXT: stxv 3, 16(3)454; CHECK-AIX64-NEXT: stxv 2, 0(3)455; CHECK-AIX64-NEXT: stxv 5, 48(5)456; CHECK-AIX64-NEXT: stxv 4, 32(5)457; CHECK-AIX64-NEXT: stxv 3, 16(5)458; CHECK-AIX64-NEXT: stxv 2, 0(5)459; CHECK-AIX64-NEXT: blr460;461; CHECK-AIX32-LABEL: ld_st_xxmfacc:462; CHECK-AIX32: # %bb.0: # %entry463; CHECK-AIX32-NEXT: lxv 3, 48(3)464; CHECK-AIX32-NEXT: lxv 5, 16(3)465; CHECK-AIX32-NEXT: lxv 2, 32(3)466; CHECK-AIX32-NEXT: lxv 4, 0(3)467; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 36, 34, 0468; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0469; CHECK-AIX32-NEXT: stxv 5, 48(3)470; CHECK-AIX32-NEXT: stxv 4, 32(3)471; CHECK-AIX32-NEXT: stxv 3, 16(3)472; CHECK-AIX32-NEXT: stxv 2, 0(3)473; CHECK-AIX32-NEXT: stxv 5, 48(5)474; CHECK-AIX32-NEXT: stxv 4, 32(5)475; CHECK-AIX32-NEXT: stxv 3, 16(5)476; CHECK-AIX32-NEXT: stxv 2, 0(5)477; CHECK-AIX32-NEXT: blr478entry:479 %0 = load <512 x i1>, ptr %vqp, align 64480 %1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)481 store <512 x i1> %1, ptr %vqp, align 64482 store <512 x i1> %1, ptr %resp, align 64483 ret void484}485 486declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)487 488; xxmfacc used with an instruction that is not a load or store.489define void @ld_op_st_xxmfacc(ptr %vqp, ptr %vpp, <16 x i8> %vc, ptr %resp) {490; CHECK-LABEL: ld_op_st_xxmfacc:491; CHECK: # %bb.0: # %entry492; CHECK-NEXT: lxv v5, 0(r3)493; CHECK-NEXT: lxv v1, 32(r3)494; CHECK-NEXT: lxv v4, 16(r3)495; CHECK-NEXT: lxv v0, 48(r3)496; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0497; CHECK-NEXT: xvi4ger8pp wacc0, v2, v2498; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0499; CHECK-NEXT: stxv v4, 48(r7)500; CHECK-NEXT: stxv v5, 32(r7)501; CHECK-NEXT: stxv v2, 16(r7)502; CHECK-NEXT: stxv v3, 0(r7)503; CHECK-NEXT: blr504;505; CHECK-BE-LABEL: ld_op_st_xxmfacc:506; CHECK-BE: # %bb.0: # %entry507; CHECK-BE-NEXT: lxv v5, 48(r3)508; CHECK-BE-NEXT: lxv v1, 16(r3)509; CHECK-BE-NEXT: lxv v4, 32(r3)510; CHECK-BE-NEXT: lxv v0, 0(r3)511; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 0512; CHECK-BE-NEXT: xvi4ger8pp wacc0, v2, v2513; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0514; CHECK-BE-NEXT: stxv v5, 48(r7)515; CHECK-BE-NEXT: stxv v4, 32(r7)516; CHECK-BE-NEXT: stxv v3, 16(r7)517; CHECK-BE-NEXT: stxv v2, 0(r7)518; CHECK-BE-NEXT: blr519;520; CHECK-O0-LABEL: ld_op_st_xxmfacc:521; CHECK-O0: # %bb.0: # %entry522; CHECK-O0-NEXT: lxv vs0, 0(r3)523; CHECK-O0-NEXT: # implicit-def: $vsrp16524; CHECK-O0-NEXT: xxlor v1, vs0, vs0525; CHECK-O0-NEXT: lxv vs0, 16(r3)526; CHECK-O0-NEXT: xxlor v0, vs0, vs0527; CHECK-O0-NEXT: lxv vs0, 32(r3)528; CHECK-O0-NEXT: # implicit-def: $vsrp18529; CHECK-O0-NEXT: xxlor v5, vs0, vs0530; CHECK-O0-NEXT: lxv vs0, 48(r3)531; CHECK-O0-NEXT: xxlor v4, vs0, vs0532; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0533; CHECK-O0-NEXT: xvi4ger8pp wacc0, v2, v2534; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0535; CHECK-O0-NEXT: xxlor vs0, v4, v4536; CHECK-O0-NEXT: stxv vs0, 48(r7)537; CHECK-O0-NEXT: xxlor vs0, v5, v5538; CHECK-O0-NEXT: stxv vs0, 32(r7)539; CHECK-O0-NEXT: xxlor vs0, v2, v2540; CHECK-O0-NEXT: stxv vs0, 16(r7)541; CHECK-O0-NEXT: xxlor vs0, v3, v3542; CHECK-O0-NEXT: stxv vs0, 0(r7)543; CHECK-O0-NEXT: blr544;545; CHECK-O0-BE-LABEL: ld_op_st_xxmfacc:546; CHECK-O0-BE: # %bb.0: # %entry547; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)548; CHECK-O0-BE-NEXT: # implicit-def: $vsrp16549; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs0550; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)551; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs0552; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)553; CHECK-O0-BE-NEXT: # implicit-def: $vsrp18554; CHECK-O0-BE-NEXT: xxlor v5, vs0, vs0555; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)556; CHECK-O0-BE-NEXT: xxlor v4, vs0, vs0557; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp36, vsp32, 0558; CHECK-O0-BE-NEXT: xvi4ger8pp wacc0, v2, v2559; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0560; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5561; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)562; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4563; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)564; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3565; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)566; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2567; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)568; CHECK-O0-BE-NEXT: blr569;570; CHECK-AIX64-LABEL: ld_op_st_xxmfacc:571; CHECK-AIX64: # %bb.0: # %entry572; CHECK-AIX64-NEXT: lxv 5, 48(3)573; CHECK-AIX64-NEXT: lxv 1, 16(3)574; CHECK-AIX64-NEXT: lxv 4, 32(3)575; CHECK-AIX64-NEXT: lxv 0, 0(3)576; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 0577; CHECK-AIX64-NEXT: xvi4ger8pp 0, 2, 2578; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0579; CHECK-AIX64-NEXT: stxv 5, 48(5)580; CHECK-AIX64-NEXT: stxv 4, 32(5)581; CHECK-AIX64-NEXT: stxv 3, 16(5)582; CHECK-AIX64-NEXT: stxv 2, 0(5)583; CHECK-AIX64-NEXT: blr584;585; CHECK-AIX32-LABEL: ld_op_st_xxmfacc:586; CHECK-AIX32: # %bb.0: # %entry587; CHECK-AIX32-NEXT: lxv 5, 48(3)588; CHECK-AIX32-NEXT: lxv 1, 16(3)589; CHECK-AIX32-NEXT: lxv 4, 32(3)590; CHECK-AIX32-NEXT: lxv 0, 0(3)591; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 0592; CHECK-AIX32-NEXT: xvi4ger8pp 0, 2, 2593; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0594; CHECK-AIX32-NEXT: stxv 5, 48(5)595; CHECK-AIX32-NEXT: stxv 4, 32(5)596; CHECK-AIX32-NEXT: stxv 3, 16(5)597; CHECK-AIX32-NEXT: stxv 2, 0(5)598; CHECK-AIX32-NEXT: blr599entry:600 %0 = load <512 x i1>, ptr %vqp, align 64601 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi4ger8pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)602 %2 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %1)603 store <512 x i1> %2, ptr %resp, align 64604 ret void605}606 607; xxmtacc and xxmfacc used interleaved in more complexed mma code.608define void @cmplx_xxmacc(ptr %ptr1, ptr %ptr2, <16 x i8> %vc1, <16 x i8> %vc2) {609; CHECK-LABEL: cmplx_xxmacc:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: lxv v1, 0(r3)612; CHECK-NEXT: lxv v7, 32(r3)613; CHECK-NEXT: lxv v0, 16(r3)614; CHECK-NEXT: lxv v6, 48(r3)615; CHECK-NEXT: vmr v4, v3616; CHECK-NEXT: vmr v3, v2617; CHECK-NEXT: vmr v5, v2618; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0619; CHECK-NEXT: xvf64gerpp wacc0, vsp34, v2620; CHECK-NEXT: xvf64gerpp wacc0, vsp36, v4621; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0622; CHECK-NEXT: stxv v4, 48(r3)623; CHECK-NEXT: stxv v5, 32(r3)624; CHECK-NEXT: stxv v2, 16(r3)625; CHECK-NEXT: stxv v3, 0(r3)626; CHECK-NEXT: blr627;628; CHECK-BE-LABEL: cmplx_xxmacc:629; CHECK-BE: # %bb.0: # %entry630; CHECK-BE-NEXT: lxv v1, 48(r3)631; CHECK-BE-NEXT: lxv v7, 16(r3)632; CHECK-BE-NEXT: lxv v0, 32(r3)633; CHECK-BE-NEXT: lxv v6, 0(r3)634; CHECK-BE-NEXT: vmr v4, v3635; CHECK-BE-NEXT: vmr v3, v2636; CHECK-BE-NEXT: vmr v5, v2637; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp32, 0638; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp34, v2639; CHECK-BE-NEXT: xvf64gerpp wacc0, vsp36, v4640; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0641; CHECK-BE-NEXT: stxv v5, 48(r3)642; CHECK-BE-NEXT: stxv v4, 32(r3)643; CHECK-BE-NEXT: stxv v3, 16(r3)644; CHECK-BE-NEXT: stxv v2, 0(r3)645; CHECK-BE-NEXT: blr646;647; CHECK-O0-LABEL: cmplx_xxmacc:648; CHECK-O0: # %bb.0: # %entry649; CHECK-O0-NEXT: vmr v4, v3650; CHECK-O0-NEXT: vmr v5, v2651; CHECK-O0-NEXT: vmr v3, v5652; CHECK-O0-NEXT: vmr v2, v4653; CHECK-O0-NEXT: vmr v1, v5654; CHECK-O0-NEXT: vmr v0, v5655; CHECK-O0-NEXT: lxv vs0, 0(r3)656; CHECK-O0-NEXT: # implicit-def: $vsrp20657; CHECK-O0-NEXT: xxlor v9, vs0, vs0658; CHECK-O0-NEXT: lxv vs0, 16(r3)659; CHECK-O0-NEXT: xxlor v8, vs0, vs0660; CHECK-O0-NEXT: lxv vs0, 32(r3)661; CHECK-O0-NEXT: # implicit-def: $vsrp19662; CHECK-O0-NEXT: xxlor v7, vs0, vs0663; CHECK-O0-NEXT: lxv vs0, 48(r3)664; CHECK-O0-NEXT: xxlor v6, vs0, vs0665; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp40, 0666; CHECK-O0-NEXT: xxlor vs0, v5, v5667; CHECK-O0-NEXT: xvf64gerpp wacc0, vsp32, vs0668; CHECK-O0-NEXT: xxlor vs0, v4, v4669; CHECK-O0-NEXT: xvf64gerpp wacc0, vsp34, vs0670; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0671; CHECK-O0-NEXT: xxlor vs0, v4, v4672; CHECK-O0-NEXT: stxv vs0, 48(r3)673; CHECK-O0-NEXT: xxlor vs0, v5, v5674; CHECK-O0-NEXT: stxv vs0, 32(r3)675; CHECK-O0-NEXT: xxlor vs0, v2, v2676; CHECK-O0-NEXT: stxv vs0, 16(r3)677; CHECK-O0-NEXT: xxlor vs0, v3, v3678; CHECK-O0-NEXT: stxv vs0, 0(r3)679; CHECK-O0-NEXT: blr680;681; CHECK-O0-BE-LABEL: cmplx_xxmacc:682; CHECK-O0-BE: # %bb.0: # %entry683; CHECK-O0-BE-NEXT: vmr v4, v3684; CHECK-O0-BE-NEXT: vmr v5, v2685; CHECK-O0-BE-NEXT: vmr v3, v5686; CHECK-O0-BE-NEXT: vmr v2, v4687; CHECK-O0-BE-NEXT: vmr v1, v5688; CHECK-O0-BE-NEXT: vmr v0, v5689; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)690; CHECK-O0-BE-NEXT: # implicit-def: $vsrp20691; CHECK-O0-BE-NEXT: xxlor v9, vs0, vs0692; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)693; CHECK-O0-BE-NEXT: xxlor v8, vs0, vs0694; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)695; CHECK-O0-BE-NEXT: # implicit-def: $vsrp19696; CHECK-O0-BE-NEXT: xxlor v7, vs0, vs0697; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)698; CHECK-O0-BE-NEXT: xxlor v6, vs0, vs0699; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp38, vsp40, 0700; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5701; CHECK-O0-BE-NEXT: xvf64gerpp wacc0, vsp32, vs0702; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4703; CHECK-O0-BE-NEXT: xvf64gerpp wacc0, vsp34, vs0704; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0705; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5706; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)707; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4708; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)709; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3710; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)711; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2712; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)713; CHECK-O0-BE-NEXT: blr714;715; CHECK-AIX64-LABEL: cmplx_xxmacc:716; CHECK-AIX64: # %bb.0: # %entry717; CHECK-AIX64-NEXT: lxv 1, 48(3)718; CHECK-AIX64-NEXT: lxv 7, 16(3)719; CHECK-AIX64-NEXT: lxv 0, 32(3)720; CHECK-AIX64-NEXT: lxv 6, 0(3)721; CHECK-AIX64-NEXT: vmr 4, 3722; CHECK-AIX64-NEXT: vmr 3, 2723; CHECK-AIX64-NEXT: vmr 5, 2724; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 38, 32, 0725; CHECK-AIX64-NEXT: xvf64gerpp 0, 34, 2726; CHECK-AIX64-NEXT: xvf64gerpp 0, 36, 4727; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0728; CHECK-AIX64-NEXT: stxv 5, 48(3)729; CHECK-AIX64-NEXT: stxv 4, 32(3)730; CHECK-AIX64-NEXT: stxv 3, 16(3)731; CHECK-AIX64-NEXT: stxv 2, 0(3)732; CHECK-AIX64-NEXT: blr733;734; CHECK-AIX32-LABEL: cmplx_xxmacc:735; CHECK-AIX32: # %bb.0: # %entry736; CHECK-AIX32-NEXT: lxv 1, 48(3)737; CHECK-AIX32-NEXT: lxv 7, 16(3)738; CHECK-AIX32-NEXT: lxv 0, 32(3)739; CHECK-AIX32-NEXT: lxv 6, 0(3)740; CHECK-AIX32-NEXT: vmr 4, 3741; CHECK-AIX32-NEXT: vmr 3, 2742; CHECK-AIX32-NEXT: vmr 5, 2743; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 38, 32, 0744; CHECK-AIX32-NEXT: xvf64gerpp 0, 34, 2745; CHECK-AIX32-NEXT: xvf64gerpp 0, 36, 4746; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0747; CHECK-AIX32-NEXT: stxv 5, 48(3)748; CHECK-AIX32-NEXT: stxv 4, 32(3)749; CHECK-AIX32-NEXT: stxv 3, 16(3)750; CHECK-AIX32-NEXT: stxv 2, 0(3)751; CHECK-AIX32-NEXT: blr752entry:753 %0 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc2, <16 x i8> %vc1)754 %1 = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> %vc1, <16 x i8> %vc1)755 %2 = load <512 x i1>, ptr %ptr1, align 64756 %3 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %2)757 %4 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %3, <256 x i1> %1, <16 x i8> %vc1)758 %5 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %4)759 %6 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> %5, <256 x i1> %0, <16 x i8> %vc2)760 store <512 x i1> %6, ptr %ptr1, align 64761 ret void762}763 764declare <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8>, <16 x i8>)765declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>)766 767; xxsetaccz768declare <512 x i1> @llvm.ppc.mma.xxsetaccz()769define void @int_xxsetaccz(ptr %ptr) {770; CHECK-LABEL: int_xxsetaccz:771; CHECK: # %bb.0: # %entry772; CHECK-NEXT: dmxxsetaccz wacc0773; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0774; CHECK-NEXT: stxv v4, 48(r3)775; CHECK-NEXT: stxv v5, 32(r3)776; CHECK-NEXT: stxv v2, 16(r3)777; CHECK-NEXT: stxv v3, 0(r3)778; CHECK-NEXT: blr779;780; CHECK-BE-LABEL: int_xxsetaccz:781; CHECK-BE: # %bb.0: # %entry782; CHECK-BE-NEXT: dmxxsetaccz wacc0783; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0784; CHECK-BE-NEXT: stxv v5, 48(r3)785; CHECK-BE-NEXT: stxv v4, 32(r3)786; CHECK-BE-NEXT: stxv v3, 16(r3)787; CHECK-BE-NEXT: stxv v2, 0(r3)788; CHECK-BE-NEXT: blr789;790; CHECK-O0-LABEL: int_xxsetaccz:791; CHECK-O0: # %bb.0: # %entry792; CHECK-O0-NEXT: dmxxsetaccz wacc0793; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0794; CHECK-O0-NEXT: xxlor vs0, v4, v4795; CHECK-O0-NEXT: stxv vs0, 48(r3)796; CHECK-O0-NEXT: xxlor vs0, v5, v5797; CHECK-O0-NEXT: stxv vs0, 32(r3)798; CHECK-O0-NEXT: xxlor vs0, v2, v2799; CHECK-O0-NEXT: stxv vs0, 16(r3)800; CHECK-O0-NEXT: xxlor vs0, v3, v3801; CHECK-O0-NEXT: stxv vs0, 0(r3)802; CHECK-O0-NEXT: blr803;804; CHECK-O0-BE-LABEL: int_xxsetaccz:805; CHECK-O0-BE: # %bb.0: # %entry806; CHECK-O0-BE-NEXT: dmxxsetaccz wacc0807; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0808; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5809; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)810; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4811; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)812; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3813; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)814; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2815; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)816; CHECK-O0-BE-NEXT: blr817;818; CHECK-AIX64-LABEL: int_xxsetaccz:819; CHECK-AIX64: # %bb.0: # %entry820; CHECK-AIX64-NEXT: dmxxsetaccz 0821; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0822; CHECK-AIX64-NEXT: stxv 5, 48(3)823; CHECK-AIX64-NEXT: stxv 4, 32(3)824; CHECK-AIX64-NEXT: stxv 3, 16(3)825; CHECK-AIX64-NEXT: stxv 2, 0(3)826; CHECK-AIX64-NEXT: blr827;828; CHECK-AIX32-LABEL: int_xxsetaccz:829; CHECK-AIX32: # %bb.0: # %entry830; CHECK-AIX32-NEXT: dmxxsetaccz 0831; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0832; CHECK-AIX32-NEXT: stxv 5, 48(3)833; CHECK-AIX32-NEXT: stxv 4, 32(3)834; CHECK-AIX32-NEXT: stxv 3, 16(3)835; CHECK-AIX32-NEXT: stxv 2, 0(3)836; CHECK-AIX32-NEXT: blr837entry:838 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()839 store <512 x i1> %0, ptr %ptr, align 64840 ret void841}842 843; disassemble_acc844declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)845define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {846; CHECK-LABEL: disass_acc:847; CHECK: # %bb.0: # %entry848; CHECK-NEXT: dmxxsetaccz wacc0849; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0850; CHECK-NEXT: stxv v5, 0(r3)851; CHECK-NEXT: stxv v4, 0(r4)852; CHECK-NEXT: stxv v3, 0(r5)853; CHECK-NEXT: stxv v2, 0(r6)854; CHECK-NEXT: blr855;856; CHECK-BE-LABEL: disass_acc:857; CHECK-BE: # %bb.0: # %entry858; CHECK-BE-NEXT: dmxxsetaccz wacc0859; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0860; CHECK-BE-NEXT: stxv v2, 0(r3)861; CHECK-BE-NEXT: stxv v3, 0(r4)862; CHECK-BE-NEXT: stxv v4, 0(r5)863; CHECK-BE-NEXT: stxv v5, 0(r6)864; CHECK-BE-NEXT: blr865;866; CHECK-O0-LABEL: disass_acc:867; CHECK-O0: # %bb.0: # %entry868; CHECK-O0-NEXT: dmxxsetaccz wacc0869; CHECK-O0-NEXT: dmxxextfdmr512 vsp32, vsp36, wacc0, 0870; CHECK-O0-NEXT: vmr v2, v0871; CHECK-O0-NEXT: xxlor vs0, v1, v1872; CHECK-O0-NEXT: xxlor vs1, v4, v4873; CHECK-O0-NEXT: xxlor vs2, v5, v5874; CHECK-O0-NEXT: stxv vs2, 0(r3)875; CHECK-O0-NEXT: stxv vs1, 0(r4)876; CHECK-O0-NEXT: stxv vs0, 0(r5)877; CHECK-O0-NEXT: stxv v2, 0(r6)878; CHECK-O0-NEXT: blr879;880; CHECK-O0-BE-LABEL: disass_acc:881; CHECK-O0-BE: # %bb.0: # %entry882; CHECK-O0-BE-NEXT: dmxxsetaccz wacc0883; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp36, vsp32, wacc0, 0884; CHECK-O0-BE-NEXT: vmr v2, v1885; CHECK-O0-BE-NEXT: xxlor vs0, v0, v0886; CHECK-O0-BE-NEXT: xxlor vs1, v5, v5887; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4888; CHECK-O0-BE-NEXT: stxv vs2, 0(r3)889; CHECK-O0-BE-NEXT: stxv vs1, 0(r4)890; CHECK-O0-BE-NEXT: stxv vs0, 0(r5)891; CHECK-O0-BE-NEXT: stxv v2, 0(r6)892; CHECK-O0-BE-NEXT: blr893;894; CHECK-AIX64-LABEL: disass_acc:895; CHECK-AIX64: # %bb.0: # %entry896; CHECK-AIX64-NEXT: dmxxsetaccz 0897; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 0898; CHECK-AIX64-NEXT: stxv 2, 0(3)899; CHECK-AIX64-NEXT: stxv 3, 0(4)900; CHECK-AIX64-NEXT: stxv 4, 0(5)901; CHECK-AIX64-NEXT: stxv 5, 0(6)902; CHECK-AIX64-NEXT: blr903;904; CHECK-AIX32-LABEL: disass_acc:905; CHECK-AIX32: # %bb.0: # %entry906; CHECK-AIX32-NEXT: dmxxsetaccz 0907; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 0908; CHECK-AIX32-NEXT: stxv 2, 0(3)909; CHECK-AIX32-NEXT: stxv 3, 0(4)910; CHECK-AIX32-NEXT: stxv 4, 0(5)911; CHECK-AIX32-NEXT: stxv 5, 0(6)912; CHECK-AIX32-NEXT: blr913entry:914 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()915 %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)916 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0917 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1918 %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2919 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3920 store <16 x i8> %2, ptr %ptr1, align 16921 store <16 x i8> %3, ptr %ptr2, align 16922 store <16 x i8> %4, ptr %ptr3, align 16923 store <16 x i8> %5, ptr %ptr4, align 16924 ret void925}926 927declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)928declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)929declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)930 931define void @testcse(ptr %res, <16 x i8> %vc) {932; CHECK-LABEL: testcse:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: dmxxsetaccz wacc0935; CHECK-NEXT: xvf32gerpp wacc0, v2, v2936; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0937; CHECK-NEXT: stxv v4, 48(r3)938; CHECK-NEXT: stxv v5, 32(r3)939; CHECK-NEXT: stxv v2, 16(r3)940; CHECK-NEXT: stxv v3, 0(r3)941; CHECK-NEXT: stxv v4, 112(r3)942; CHECK-NEXT: stxv v5, 96(r3)943; CHECK-NEXT: stxv v2, 80(r3)944; CHECK-NEXT: stxv v3, 64(r3)945; CHECK-NEXT: blr946;947; CHECK-BE-LABEL: testcse:948; CHECK-BE: # %bb.0: # %entry949; CHECK-BE-NEXT: dmxxsetaccz wacc0950; CHECK-BE-NEXT: xvf32gerpp wacc0, v2, v2951; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0952; CHECK-BE-NEXT: stxv v5, 48(r3)953; CHECK-BE-NEXT: stxv v4, 32(r3)954; CHECK-BE-NEXT: stxv v3, 16(r3)955; CHECK-BE-NEXT: stxv v2, 0(r3)956; CHECK-BE-NEXT: stxv v5, 112(r3)957; CHECK-BE-NEXT: stxv v4, 96(r3)958; CHECK-BE-NEXT: stxv v3, 80(r3)959; CHECK-BE-NEXT: stxv v2, 64(r3)960; CHECK-BE-NEXT: blr961;962; CHECK-O0-LABEL: testcse:963; CHECK-O0: # %bb.0: # %entry964; CHECK-O0-NEXT: dmxxsetaccz wacc0965; CHECK-O0-NEXT: xvf32gerpp wacc0, v2, v2966; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0967; CHECK-O0-NEXT: xxlor vs3, v4, v4968; CHECK-O0-NEXT: stxv vs3, 48(r3)969; CHECK-O0-NEXT: xxlor vs2, v5, v5970; CHECK-O0-NEXT: stxv vs2, 32(r3)971; CHECK-O0-NEXT: xxlor vs1, v2, v2972; CHECK-O0-NEXT: stxv vs1, 16(r3)973; CHECK-O0-NEXT: xxlor vs0, v3, v3974; CHECK-O0-NEXT: stxv vs0, 0(r3)975; CHECK-O0-NEXT: stxv vs3, 112(r3)976; CHECK-O0-NEXT: stxv vs2, 96(r3)977; CHECK-O0-NEXT: stxv vs1, 80(r3)978; CHECK-O0-NEXT: stxv vs0, 64(r3)979; CHECK-O0-NEXT: blr980;981; CHECK-O0-BE-LABEL: testcse:982; CHECK-O0-BE: # %bb.0: # %entry983; CHECK-O0-BE-NEXT: dmxxsetaccz wacc0984; CHECK-O0-BE-NEXT: xvf32gerpp wacc0, v2, v2985; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 0986; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5987; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)988; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4989; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)990; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3991; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)992; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2993; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)994; CHECK-O0-BE-NEXT: stxv vs3, 112(r3)995; CHECK-O0-BE-NEXT: stxv vs2, 96(r3)996; CHECK-O0-BE-NEXT: stxv vs1, 80(r3)997; CHECK-O0-BE-NEXT: stxv vs0, 64(r3)998; CHECK-O0-BE-NEXT: blr999;1000; CHECK-AIX64-LABEL: testcse:1001; CHECK-AIX64: # %bb.0: # %entry1002; CHECK-AIX64-NEXT: dmxxsetaccz 01003; CHECK-AIX64-NEXT: xvf32gerpp 0, 2, 21004; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 01005; CHECK-AIX64-NEXT: stxv 5, 48(3)1006; CHECK-AIX64-NEXT: stxv 4, 32(3)1007; CHECK-AIX64-NEXT: stxv 3, 16(3)1008; CHECK-AIX64-NEXT: stxv 2, 0(3)1009; CHECK-AIX64-NEXT: stxv 5, 112(3)1010; CHECK-AIX64-NEXT: stxv 4, 96(3)1011; CHECK-AIX64-NEXT: stxv 3, 80(3)1012; CHECK-AIX64-NEXT: stxv 2, 64(3)1013; CHECK-AIX64-NEXT: blr1014;1015; CHECK-AIX32-LABEL: testcse:1016; CHECK-AIX32: # %bb.0: # %entry1017; CHECK-AIX32-NEXT: dmxxsetaccz 01018; CHECK-AIX32-NEXT: xvf32gerpp 0, 2, 21019; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 01020; CHECK-AIX32-NEXT: stxv 5, 48(3)1021; CHECK-AIX32-NEXT: stxv 4, 32(3)1022; CHECK-AIX32-NEXT: stxv 3, 16(3)1023; CHECK-AIX32-NEXT: stxv 2, 0(3)1024; CHECK-AIX32-NEXT: stxv 5, 112(3)1025; CHECK-AIX32-NEXT: stxv 4, 96(3)1026; CHECK-AIX32-NEXT: stxv 3, 80(3)1027; CHECK-AIX32-NEXT: stxv 2, 64(3)1028; CHECK-AIX32-NEXT: blr1029entry:1030 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()1031 %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()1032 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)1033 %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)1034 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 01035 %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 11036 store <512 x i1> %2, ptr %4, align 641037 store <512 x i1> %3, ptr %5, align 641038 ret void1039}1040 1041declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)1042declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)1043 1044; Function Attrs: nofree nounwind1045define void @test_ldst_1(ptr nocapture readonly %vqp, ptr %vpp, <16 x i8> %vc, ptr nocapture %resp) {1046; CHECK-LABEL: test_ldst_1:1047; CHECK: # %bb.0: # %entry1048; CHECK-NEXT: lxv v5, 0(r3)1049; CHECK-NEXT: lxv v1, 32(r3)1050; CHECK-NEXT: lxv v4, 16(r3)1051; CHECK-NEXT: lxv v0, 48(r3)1052; CHECK-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01053; CHECK-NEXT: plxvp vsp36, 8(r4), 01054; CHECK-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 01055; CHECK-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01056; CHECK-NEXT: stxv v4, 48(r7)1057; CHECK-NEXT: stxv v5, 32(r7)1058; CHECK-NEXT: stxv v2, 16(r7)1059; CHECK-NEXT: stxv v3, 0(r7)1060; CHECK-NEXT: blr1061;1062; CHECK-BE-LABEL: test_ldst_1:1063; CHECK-BE: # %bb.0: # %entry1064; CHECK-BE-NEXT: lxv v5, 48(r3)1065; CHECK-BE-NEXT: lxv v1, 16(r3)1066; CHECK-BE-NEXT: lxv v4, 32(r3)1067; CHECK-BE-NEXT: lxv v0, 0(r3)1068; CHECK-BE-NEXT: dmxxinstdmr512 wacc0, vsp32, vsp36, 01069; CHECK-BE-NEXT: plxvp vsp36, 8(r4), 01070; CHECK-BE-NEXT: pmxvf64gernn wacc0, vsp36, v2, 0, 01071; CHECK-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01072; CHECK-BE-NEXT: stxv v5, 48(r7)1073; CHECK-BE-NEXT: stxv v4, 32(r7)1074; CHECK-BE-NEXT: stxv v3, 16(r7)1075; CHECK-BE-NEXT: stxv v2, 0(r7)1076; CHECK-BE-NEXT: blr1077;1078; CHECK-O0-LABEL: test_ldst_1:1079; CHECK-O0: # %bb.0: # %entry1080; CHECK-O0-NEXT: vmr v4, v21081; CHECK-O0-NEXT: lxv vs0, 0(r3)1082; CHECK-O0-NEXT: # implicit-def: $vsrp161083; CHECK-O0-NEXT: xxlor v1, vs0, vs01084; CHECK-O0-NEXT: lxv vs0, 16(r3)1085; CHECK-O0-NEXT: xxlor v0, vs0, vs01086; CHECK-O0-NEXT: lxv vs0, 32(r3)1087; CHECK-O0-NEXT: # implicit-def: $vsrp171088; CHECK-O0-NEXT: xxlor v3, vs0, vs01089; CHECK-O0-NEXT: lxv vs0, 48(r3)1090; CHECK-O0-NEXT: xxlor v2, vs0, vs01091; CHECK-O0-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp32, 01092; CHECK-O0-NEXT: plxvp vsp34, 8(r4), 01093; CHECK-O0-NEXT: xxlor vs0, v4, v41094; CHECK-O0-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 01095; CHECK-O0-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01096; CHECK-O0-NEXT: xxlor vs0, v4, v41097; CHECK-O0-NEXT: stxv vs0, 48(r7)1098; CHECK-O0-NEXT: xxlor vs0, v5, v51099; CHECK-O0-NEXT: stxv vs0, 32(r7)1100; CHECK-O0-NEXT: xxlor vs0, v2, v21101; CHECK-O0-NEXT: stxv vs0, 16(r7)1102; CHECK-O0-NEXT: xxlor vs0, v3, v31103; CHECK-O0-NEXT: stxv vs0, 0(r7)1104; CHECK-O0-NEXT: blr1105;1106; CHECK-O0-BE-LABEL: test_ldst_1:1107; CHECK-O0-BE: # %bb.0: # %entry1108; CHECK-O0-BE-NEXT: vmr v4, v21109; CHECK-O0-BE-NEXT: lxv vs0, 48(r3)1110; CHECK-O0-BE-NEXT: # implicit-def: $vsrp161111; CHECK-O0-BE-NEXT: xxlor v1, vs0, vs01112; CHECK-O0-BE-NEXT: lxv vs0, 32(r3)1113; CHECK-O0-BE-NEXT: xxlor v0, vs0, vs01114; CHECK-O0-BE-NEXT: lxv vs0, 16(r3)1115; CHECK-O0-BE-NEXT: # implicit-def: $vsrp171116; CHECK-O0-BE-NEXT: xxlor v3, vs0, vs01117; CHECK-O0-BE-NEXT: lxv vs0, 0(r3)1118; CHECK-O0-BE-NEXT: xxlor v2, vs0, vs01119; CHECK-O0-BE-NEXT: dmxxinstdmr512 wacc0, vsp34, vsp32, 01120; CHECK-O0-BE-NEXT: plxvp vsp34, 8(r4), 01121; CHECK-O0-BE-NEXT: xxlor vs0, v4, v41122; CHECK-O0-BE-NEXT: pmxvf64gernn wacc0, vsp34, vs0, 0, 01123; CHECK-O0-BE-NEXT: dmxxextfdmr512 vsp34, vsp36, wacc0, 01124; CHECK-O0-BE-NEXT: xxlor vs0, v5, v51125; CHECK-O0-BE-NEXT: stxv vs0, 48(r7)1126; CHECK-O0-BE-NEXT: xxlor vs0, v4, v41127; CHECK-O0-BE-NEXT: stxv vs0, 32(r7)1128; CHECK-O0-BE-NEXT: xxlor vs0, v3, v31129; CHECK-O0-BE-NEXT: stxv vs0, 16(r7)1130; CHECK-O0-BE-NEXT: xxlor vs0, v2, v21131; CHECK-O0-BE-NEXT: stxv vs0, 0(r7)1132; CHECK-O0-BE-NEXT: blr1133;1134; CHECK-AIX64-LABEL: test_ldst_1:1135; CHECK-AIX64: # %bb.0: # %entry1136; CHECK-AIX64-NEXT: lxv 5, 48(3)1137; CHECK-AIX64-NEXT: lxv 1, 16(3)1138; CHECK-AIX64-NEXT: lxv 4, 32(3)1139; CHECK-AIX64-NEXT: lxv 0, 0(3)1140; CHECK-AIX64-NEXT: dmxxinstdmr512 0, 32, 36, 01141; CHECK-AIX64-NEXT: plxvp 36, 8(4), 01142; CHECK-AIX64-NEXT: pmxvf64gernn 0, 36, 2, 0, 01143; CHECK-AIX64-NEXT: dmxxextfdmr512 34, 36, 0, 01144; CHECK-AIX64-NEXT: stxv 5, 48(5)1145; CHECK-AIX64-NEXT: stxv 4, 32(5)1146; CHECK-AIX64-NEXT: stxv 3, 16(5)1147; CHECK-AIX64-NEXT: stxv 2, 0(5)1148; CHECK-AIX64-NEXT: blr1149;1150; CHECK-AIX32-LABEL: test_ldst_1:1151; CHECK-AIX32: # %bb.0: # %entry1152; CHECK-AIX32-NEXT: lxv 5, 48(3)1153; CHECK-AIX32-NEXT: lxv 1, 16(3)1154; CHECK-AIX32-NEXT: lxv 4, 32(3)1155; CHECK-AIX32-NEXT: lxv 0, 0(3)1156; CHECK-AIX32-NEXT: dmxxinstdmr512 0, 32, 36, 01157; CHECK-AIX32-NEXT: plxvp 36, 8(4), 01158; CHECK-AIX32-NEXT: pmxvf64gernn 0, 36, 2, 0, 01159; CHECK-AIX32-NEXT: dmxxextfdmr512 34, 36, 0, 01160; CHECK-AIX32-NEXT: stxv 5, 48(5)1161; CHECK-AIX32-NEXT: stxv 4, 32(5)1162; CHECK-AIX32-NEXT: stxv 3, 16(5)1163; CHECK-AIX32-NEXT: stxv 2, 0(5)1164; CHECK-AIX32-NEXT: blr1165entry:1166 %0 = load <512 x i1>, ptr %vqp, align 641167 %1 = getelementptr i8, ptr %vpp, i64 81168 %2 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %1)1169 %3 = tail call <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1> %0, <256 x i1> %2, <16 x i8> %vc, i32 0, i32 0)1170 store <512 x i1> %3, ptr %resp, align 641171 ret void1172}1173 1174declare <512 x i1> @llvm.ppc.mma.pmxvf64gernn(<512 x i1>, <256 x i1>, <16 x i8>, i32, i32)1175declare <512 x i1> @llvm.ppc.mma.xvf64gernp(<512 x i1>, <256 x i1>, <16 x i8>)1176