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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \3; RUN: -mcpu=pwr8 -O2 < %s | FileCheck %s4 5define void @test_mtvscr() {6; CHECK-LABEL: test_mtvscr:7; CHECK: # %bb.0: # %test_mtvscr_entry8; CHECK-NEXT: addi 3, 1, -169; CHECK-NEXT: lxvd2x 0, 0, 310; CHECK-NEXT: xxswapd 34, 011; CHECK-NEXT: mtvscr 212; CHECK-NEXT: blr13test_mtvscr_entry:14 %0 = alloca <4 x i32>15 %1 = load <4 x i32>, ptr %016 call void @llvm.ppc.altivec.mtvscr(<4 x i32> %1)17 ret void18}19 20define void @test_mfvscr() {21; CHECK-LABEL: test_mfvscr:22; CHECK: # %bb.0: # %test_mfvscr_entry23; CHECK-NEXT: mfvscr 224; CHECK-NEXT: addi 3, 1, -1625; CHECK-NEXT: xxswapd 0, 3426; CHECK-NEXT: stxvd2x 0, 0, 327; CHECK-NEXT: blr28test_mfvscr_entry:29 %0 = alloca <8 x i16>30 %1 = call <8 x i16> @llvm.ppc.altivec.mfvscr()31 store <8 x i16> %1, ptr %032 ret void33}34 35declare void @llvm.ppc.altivec.mtvscr(<4 x i32>)36 37declare <8 x i16> @llvm.ppc.altivec.mfvscr()38