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1; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=generic < %s -mtriple=ppc64-- | FileCheck %s -check-prefix=GENERIC-CHECK2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s -mtriple=ppc64-- | FileCheck %s -check-prefixes=PWR8-CHECK,CHECK3; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s -mtriple=ppc64le-- | FileCheck %s -check-prefixes=PWR9-CHECK,CHECK4 5 6define i64 @foo(i64 %a) {7entry:8 %mul = mul nsw i64 %a, 69 ret i64 %mul10}11 12; GENERIC-CHECK-LABEL: @foo13; GENERIC-CHECK: mulli r3, r3, 614; GENERIC-CHECK: blr15 16define i64 @test1(i64 %a) {17 %tmp.1 = mul nsw i64 %a, 16 ; <i64> [#uses=1]18 ret i64 %tmp.119}20; CHECK-LABEL: test1:21; CHECK-NOT: mul22; CHECK: sldi r[[REG1:[0-9]+]], r3, 423 24 25define i64 @test2(i64 %a) {26 %tmp.1 = mul nsw i64 %a, 17 ; <i64> [#uses=1]27 ret i64 %tmp.128}29; CHECK-LABEL: test2:30; CHECK-NOT: mul31; CHECK: sldi r[[REG1:[0-9]+]], r3, 432; CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]33 34define i64 @test3(i64 %a) {35 %tmp.1 = mul nsw i64 %a, 15 ; <i64> [#uses=1]36 ret i64 %tmp.137}38; CHECK-LABEL: test3:39; CHECK-NOT: mul40; CHECK: sldi r[[REG1:[0-9]+]], r3, 441; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r342 43; negtive constant44 45define i64 @test4(i64 %a) {46 %tmp.1 = mul nsw i64 %a, -16 ; <i64> [#uses=1]47 ret i64 %tmp.148}49; CHECK-LABEL: test4:50; CHECK-NOT: mul51; CHECK: sldi r[[REG1:[0-9]+]], r3, 452; CHECK-NEXT: neg r[[REG2:[0-9]+]], r[[REG1]]53 54define i64 @test5(i64 %a) {55 %tmp.1 = mul nsw i64 %a, -17 ; <i64> [#uses=1]56 ret i64 %tmp.157}58; CHECK-LABEL: test5:59; PWR9-CHECK: mulli r[[REG1:[0-9]+]], r3, -1760; PWR8-CHECK-NOT: mul61; PWR8-CHECK: sldi r[[REG1:[0-9]+]], r3, 462; PWR8-CHECK-NEXT: add r[[REG2:[0-9]+]], r3, r[[REG1]]63; PWR8-CHECK-NEXT: neg r{{[0-9]+}}, r[[REG2]]64 65define i64 @test6(i64 %a) {66 %tmp.1 = mul nsw i64 %a, -15 ; <i64> [#uses=1]67 ret i64 %tmp.168}69; CHECK-LABEL: test6:70; CHECK-NOT: mul71; CHECK: sldi r[[REG1:[0-9]+]], r3, 472; CHECK-NEXT: sub r[[REG2:[0-9]+]], r3, r[[REG1]]73; CHECK-NOT: neg74 75; boundary case76 77define i64 @test7(i64 %a) {78 %tmp.1 = mul nsw i64 %a, -9223372036854775808 ; <i64> [#uses=1]79 ret i64 %tmp.180}81; CHECK-LABEL: test7:82; CHECK-NOT: mul83; CHECK: sldi r[[REG1:[0-9]+]], r3, 6384 85define i64 @test8(i64 %a) {86 %tmp.1 = mul nsw i64 %a, 9223372036854775807 ; <i64> [#uses=1]87 ret i64 %tmp.188}89; CHECK-LABEL: test8:90; CHECK-NOT: mul91; CHECK: sldi r[[REG1:[0-9]+]], r3, 6392; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r393