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1; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr8 | FileCheck %s --check-prefixes=CHECK,CHECK-P82; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=ppc64le-- -mcpu=pwr9 | FileCheck %s --check-prefixes=CHECK,CHECK-P93 4define <16 x i8> @test1_v16i8(<16 x i8> %a) {5 %tmp.1 = mul nsw <16 x i8> %a, <i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16, i8 16> ; <<16 x i8>> [#uses=1]6 ret <16 x i8> %tmp.17}8; CHECK-LABEL: test1_v16i8:9; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 410; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 411; CHECK-NOT: vmul12; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]13 14define <16 x i8> @test2_v16i8(<16 x i8> %a) {15 %tmp.1 = mul nsw <16 x i8> %a, <i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17, i8 17> ; <<16 x i8>> [#uses=1]16 ret <16 x i8> %tmp.117}18; CHECK-LABEL: test2_v16i8:19; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 420; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 421; CHECK-NOT: vmul22; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]23; CHECK-NEXT: vaddubm v[[REG3:[0-9]+]], v2, v[[REG2]]24 25define <16 x i8> @test3_v16i8(<16 x i8> %a) {26 %tmp.1 = mul nsw <16 x i8> %a, <i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15, i8 15> ; <<16 x i8>> [#uses=1]27 ret <16 x i8> %tmp.128}29; CHECK-LABEL: test3_v16i8:30; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 431; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 432; CHECK-NOT: vmul33; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]34; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v235 36; negtive constant37 38define <16 x i8> @test4_v16i8(<16 x i8> %a) {39 %tmp.1 = mul nsw <16 x i8> %a, <i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16, i8 -16> ; <<16 x i8>> [#uses=1]40 ret <16 x i8> %tmp.141}42; CHECK-LABEL: test4_v16i8:43; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 444; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 445; CHECK-NOT: vmul46; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]47; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],48; CHECK-NEXT: vsububm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]49 50define <16 x i8> @test5_v16i8(<16 x i8> %a) {51 %tmp.1 = mul nsw <16 x i8> %a, <i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17, i8 -17> ; <<16 x i8>> [#uses=1]52 ret <16 x i8> %tmp.153}54; CHECK-LABEL: test5_v16i8:55; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 456; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 457; CHECK-NOT: vmul58; CHECK-NEXT: vslb v[[REG3:[0-9]+]], v2, v[[REG1]]59; CHECK-NEXT: vaddubm v[[REG4:[0-9]+]], v2, v[[REG3]]60; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],61; CHECK-NEXT: vsububm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]62 63define <16 x i8> @test6_v16i8(<16 x i8> %a) {64 %tmp.1 = mul nsw <16 x i8> %a, <i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15, i8 -15> ; <<16 x i8>> [#uses=1]65 ret <16 x i8> %tmp.166}67; CHECK-LABEL: test6_v16i8:68; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 469; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 470; CHECK-NOT: vmul71; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]72; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v2, v[[REG2]]73 74; boundary case75 76define <16 x i8> @test7_v16i8(<16 x i8> %a) {77 %tmp.1 = mul nsw <16 x i8> %a, <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> ; <<16 x i8>> [#uses=1]78 ret <16 x i8> %tmp.179}80; CHECK-LABEL: test7_v16i8:81; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 782; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 783; CHECK-NOT: vmul84; CHECK-NEXT: vslb v[[REG5:[0-9]+]], v2, v[[REG1]]85 86define <16 x i8> @test8_v16i8(<16 x i8> %a) {87 %tmp.1 = mul nsw <16 x i8> %a, <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> ; <<16 x i8>> [#uses=1]88 ret <16 x i8> %tmp.189}90; CHECK-LABEL: test8_v16i8:91; CHECK-P8: vspltisb v[[REG1:[0-9]+]], 792; CHECK-P9: xxspltib v[[REG1:[0-9]+]], 793; CHECK-NOT: vmul94; CHECK-NEXT: vslb v[[REG2:[0-9]+]], v2, v[[REG1]]95; CHECK-NEXT: vsububm v[[REG3:[0-9]+]], v[[REG2]], v296 97define <8 x i16> @test1_v8i16(<8 x i16> %a) {98 %tmp.1 = mul nsw <8 x i16> %a, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16> ; <<8 x i16>> [#uses=1]99 ret <8 x i16> %tmp.1100}101; CHECK-LABEL: test1_v8i16:102; CHECK: vspltish v[[REG1:[0-9]+]], 4103; CHECK-NOT: vmul104; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]105 106define <8 x i16> @test2_v8i16(<8 x i16> %a) {107 %tmp.1 = mul nsw <8 x i16> %a, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> ; <<8 x i16>> [#uses=1]108 ret <8 x i16> %tmp.1109}110; CHECK-LABEL: test2_v8i16:111; CHECK: vspltish v[[REG1:[0-9]+]], 4112; CHECK-NOT: vmul113; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]114; CHECK-NEXT: vadduhm v[[REG3:[0-9]+]], v2, v[[REG2]]115 116define <8 x i16> @test3_v8i16(<8 x i16> %a) {117 %tmp.1 = mul nsw <8 x i16> %a, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> ; <<8 x i16>> [#uses=1]118 ret <8 x i16> %tmp.1119}120; CHECK-LABEL: test3_v8i16:121; CHECK: vspltish v[[REG1:[0-9]+]], 4122; CHECK-NOT: vmul123; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]124; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2125 126; negtive constant127 128define <8 x i16> @test4_v8i16(<8 x i16> %a) {129 %tmp.1 = mul nsw <8 x i16> %a, <i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16> ; <<8 x i16>> [#uses=1]130 ret <8 x i16> %tmp.1131}132; CHECK-LABEL: test4_v8i16:133; CHECK: vspltish v[[REG1:[0-9]+]], 4134; CHECK-NOT: vmul135; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]136; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],137; CHECK-NEXT: vsubuhm v[[REG4:[0-9]+]], v[[REG2]], v[[REG3]]138 139define <8 x i16> @test5_v8i16(<8 x i16> %a) {140 %tmp.1 = mul nsw <8 x i16> %a, <i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17, i16 -17> ; <<8 x i16>> [#uses=1]141 ret <8 x i16> %tmp.1142}143; CHECK-LABEL: test5_v8i16:144; CHECK: vspltish v[[REG1:[0-9]+]], 4145; CHECK-NOT: vmul146; CHECK-NEXT: vslh v[[REG3:[0-9]+]], v2, v[[REG1]]147; CHECK-NEXT: vadduhm v[[REG4:[0-9]+]], v2, v[[REG3]]148; CHECK-NEXT: xxlxor v[[REG2:[0-9]+]],149; CHECK-NEXT: vsubuhm v[[REG5:[0-9]+]], v[[REG2]], v[[REG4]]150 151define <8 x i16> @test6_v8i16(<8 x i16> %a) {152 %tmp.1 = mul nsw <8 x i16> %a, <i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15, i16 -15> ; <<8 x i16>> [#uses=1]153 ret <8 x i16> %tmp.1154}155; CHECK-LABEL: test6_v8i16:156; CHECK: vspltish v[[REG1:[0-9]+]], 4157; CHECK-NOT: vmul158; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]159; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v2, v[[REG2]]160 161; boundary case162 163define <8 x i16> @test7_v8i16(<8 x i16> %a) {164 %tmp.1 = mul nsw <8 x i16> %a, <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768> ; <<8 x i16>> [#uses=1]165 ret <8 x i16> %tmp.1166}167; CHECK-LABEL: test7_v8i16:168; CHECK: vspltish v[[REG1:[0-9]+]], 15169; CHECK-NOT: vmul170; CHECK-NEXT: vslh v[[REG5:[0-9]+]], v2, v[[REG1]]171 172define <8 x i16> @test8_v8i16(<8 x i16> %a) {173 %tmp.1 = mul nsw <8 x i16> %a, <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767> ; <<8 x i16>> [#uses=1]174 ret <8 x i16> %tmp.1175}176; CHECK-LABEL: test8_v8i16:177; CHECK: vspltish v[[REG1:[0-9]+]], 15178; CHECK-NOT: vmul179; CHECK-NEXT: vslh v[[REG2:[0-9]+]], v2, v[[REG1]]180; CHECK-NEXT: vsubuhm v[[REG3:[0-9]+]], v[[REG2]], v2181 182define <4 x i32> @test1_v4i32(<4 x i32> %a) {183 %tmp.1 = mul nsw <4 x i32> %a, <i32 16, i32 16, i32 16, i32 16> ; <<4 x i32>> [#uses=1]184 ret <4 x i32> %tmp.1185}186; CHECK-LABEL: test1_v4i32:187; CHECK: vspltisw v[[REG1:[0-9]+]], 4188; CHECK-NOT: vmul189; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]190 191define <4 x i32> @test2_v4i32(<4 x i32> %a) {192 %tmp.1 = mul nsw <4 x i32> %a, <i32 17, i32 17, i32 17, i32 17> ; <<4 x i32>> [#uses=1]193 ret <4 x i32> %tmp.1194}195; CHECK-LABEL: test2_v4i32:196; CHECK: vspltisw v[[REG1:[0-9]+]], 4197; CHECK-NOT: vmul198; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]199; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]200 201define <4 x i32> @test3_v4i32(<4 x i32> %a) {202 %tmp.1 = mul nsw <4 x i32> %a, <i32 15, i32 15, i32 15, i32 15> ; <<4 x i32>> [#uses=1]203 ret <4 x i32> %tmp.1204}205; CHECK-LABEL: test3_v4i32:206; CHECK: vspltisw v[[REG1:[0-9]+]], 4207; CHECK-NOT: vmul208; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]209; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v[[REG2]], v2210 211; negtive constant212 213define <4 x i32> @test4_v4i32(<4 x i32> %a) {214 %tmp.1 = mul nsw <4 x i32> %a, <i32 -16, i32 -16, i32 -16, i32 -16> ; <<4 x i32>> [#uses=1]215 ret <4 x i32> %tmp.1216}217; CHECK-LABEL: test4_v4i32:218; CHECK: vspltisw v[[REG1:[0-9]+]], 4219; CHECK-NOT: vmul220; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]221; CHECK-P8-NEXT: xxlxor v[[REG3:[0-9]+]],222; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG3]], v[[REG2]]223; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG2]]224 225define <4 x i32> @test5_v4i32(<4 x i32> %a) {226 %tmp.1 = mul nsw <4 x i32> %a, <i32 -17, i32 -17, i32 -17, i32 -17> ; <<4 x i32>> [#uses=1]227 ret <4 x i32> %tmp.1228}229; CHECK-LABEL: test5_v4i32:230; CHECK: vspltisw v[[REG1:[0-9]+]], 4231; CHECK-NOT: vmul232; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]233; CHECK-NEXT: vadduwm v[[REG3:[0-9]+]], v2, v[[REG2]]234; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],235; CHECK-P8-NEXT: vsubuwm v{{[0-9]+}}, v[[REG4]], v[[REG3]]236; CHECK-P9-NEXT: vnegw v{{[0-9]+}}, v[[REG3]]237 238define <4 x i32> @test6_v4i32(<4 x i32> %a) {239 %tmp.1 = mul nsw <4 x i32> %a, <i32 -15, i32 -15, i32 -15, i32 -15> ; <<4 x i32>> [#uses=1]240 ret <4 x i32> %tmp.1241}242; CHECK-LABEL: test6_v4i32:243; CHECK: vspltisw v[[REG1:[0-9]+]], 4244; CHECK-NOT: vmul245; CHECK-NEXT: vslw v[[REG2:[0-9]+]], v2, v[[REG1]]246; CHECK-NEXT: vsubuwm v[[REG3:[0-9]+]], v2, v[[REG2]]247 248; boundary case249 250define <4 x i32> @test7_v4i32(<4 x i32> %a) {251 %tmp.1 = mul nsw <4 x i32> %a, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=1]252 ret <4 x i32> %tmp.1253}254; CHECK-LABEL: test7_v4i32:255; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]256; CHECK-NOT: vmul257; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]258 259define <4 x i32> @test8_v4i32(<4 x i32> %a) {260 %tmp.1 = mul nsw <4 x i32> %a, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]261 ret <4 x i32> %tmp.1262}263; CHECK-LABEL: test8_v4i32:264; CHECK: xxleqv v[[REG1:[0-9]+]], v[[REG2:[0-9]+]], v[[REG2]]265; CHECK-NOT: vmul266; CHECK-NEXT: vslw v[[REG3:[0-9]+]], v2, v[[REG1]]267; CHECK-NEXT: vsubuwm v[[REG4:[0-9]+]], v[[REG3]], v2268 269define <2 x i64> @test1_v2i64(<2 x i64> %a) {270 %tmp.1 = mul nsw <2 x i64> %a, <i64 16, i64 16> ; <<2 x i64>> [#uses=1]271 ret <2 x i64> %tmp.1272}273; CHECK-LABEL: test1_v2i64:274; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}275; CHECK-NOT: vmul276; CHECK-NEXT: vsld v{{[0-9]+}}, v2, v[[REG2]]277 278define <2 x i64> @test2_v2i64(<2 x i64> %a) {279 %tmp.1 = mul nsw <2 x i64> %a, <i64 17, i64 17> ; <<2 x i64>> [#uses=1]280 ret <2 x i64> %tmp.1281}282 283; CHECK-LABEL: test2_v2i64:284; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}285; CHECK-NOT: vmul286; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]287; CHECK-NEXT: vaddudm v{{[0-9]+}}, v2, v[[REG3]]288 289define <2 x i64> @test3_v2i64(<2 x i64> %a) {290 %tmp.1 = mul nsw <2 x i64> %a, <i64 15, i64 15> ; <<2 x i64>> [#uses=1]291 ret <2 x i64> %tmp.1292}293 294; CHECK-LABEL: test3_v2i64:295; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}296; CHECK-NOT: vmul297; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]298; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2299 300; negtive constant301 302define <2 x i64> @test4_v2i64(<2 x i64> %a) {303 %tmp.1 = mul nsw <2 x i64> %a, <i64 -16, i64 -16> ; <<2 x i64>> [#uses=1]304 ret <2 x i64> %tmp.1305}306 307; CHECK-LABEL: test4_v2i64:308; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}309; CHECK-NOT: vmul310; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]311; CHECK-P8-NEXT: xxlxor v[[REG4:[0-9]+]],312; CHECK-P8-NEXT: vsubudm v{{[0-9]+}}, v[[REG4]], v[[REG3]]313; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]314 315define <2 x i64> @test5_v2i64(<2 x i64> %a) {316 %tmp.1 = mul nsw <2 x i64> %a, <i64 -17, i64 -17> ; <<2 x i64>> [#uses=1]317 ret <2 x i64> %tmp.1318}319 320; CHECK-LABEL: test5_v2i64:321; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}322; CHECK-NOT: vmul323; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]324; CHECK-NEXT: vaddudm v[[REG4:[0-9]+]], v2, v[[REG3]]325; CHECK-P8-NEXT: xxlxor v[[REG5:[0-9]+]],326; CHECK-P8-NEXT: vsubudm v[[REG6:[0-9]+]], v[[REG5]], v[[REG4]]327; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]328 329define <2 x i64> @test6_v2i64(<2 x i64> %a) {330 %tmp.1 = mul nsw <2 x i64> %a, <i64 -15, i64 -15> ; <<2 x i64>> [#uses=1]331 ret <2 x i64> %tmp.1332}333 334; CHECK-LABEL: test6_v2i64:335; CHECK: vupklsw v[[REG1:[0-9]+]], v{{[0-9]+}}336; CHECK-NOT: vmul337; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]338; CHECK-NEXT: vsubudm v{{[0-9]+}}, v2, v[[REG3]]339 340 341; boundary case342 343define <2 x i64> @test7_v2i64(<2 x i64> %a) {344 %tmp.1 = mul nsw <2 x i64> %a, <i64 -9223372036854775808, i64 -9223372036854775808> ; <<2 x i64>> [#uses=1]345 ret <2 x i64> %tmp.1346}347 348; CHECK-LABEL: test7_v2i64:349; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]350; CHECK-NOT: vmul351; CHECK-NEXT: vsld v[[REG4:[0-9]+]], v2, v[[REG2]]352 353define <2 x i64> @test8_v2i64(<2 x i64> %a) {354 %tmp.1 = mul nsw <2 x i64> %a, <i64 9223372036854775807, i64 9223372036854775807> ; <<2 x i64>> [#uses=1]355 ret <2 x i64> %tmp.1356}357 358; CHECK-LABEL: test8_v2i64:359; CHECK: xxleqv v[[REG2:[0-9]+]], v[[REG1:[0-9]+]], v[[REG1]]360; CHECK-NOT: vmul361; CHECK-NEXT: vsld v[[REG3:[0-9]+]], v2, v[[REG2]]362; CHECK-NEXT: vsubudm v{{[0-9]+}}, v[[REG3]], v2363