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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5 6; This test case tests multiply high for i32 and i64. When the values are7; sign-extended, mulh[d|w] is emitted. When values are zero-extended,8; mulh[d|w]u is emitted instead.9 10; The primary goal is transforming the pattern:11; (shift (mul (ext $a, <wide_type>), (ext $b, <wide_type>)), <narrow_type>)12; into (mulhs $a, $b) for sign extend, and (mulhu $a, $b) for zero extend,13; provided that the mulh operation is legal for <narrow_type>.14; The shift operation can be either the srl or sra operations.15 16; When no attribute is present on i32, the shift operation is srl.17define i32 @test_mulhw(i32 %a, i32 %b) {18; CHECK-LABEL: test_mulhw:19; CHECK: # %bb.0:20; CHECK-NEXT: mulhw r3, r3, r421; CHECK-NEXT: clrldi r3, r3, 3222; CHECK-NEXT: blr23 %1 = sext i32 %a to i6424 %2 = sext i32 %b to i6425 %mul = mul i64 %1, %226 %shr = lshr i64 %mul, 3227 %tr = trunc i64 %shr to i3228 ret i32 %tr29}30 31define i32 @test_mulhu(i32 %a, i32 %b) {32; CHECK-LABEL: test_mulhu:33; CHECK: # %bb.0:34; CHECK-NEXT: mulhwu r3, r3, r435; CHECK-NEXT: clrldi r3, r3, 3236; CHECK-NEXT: blr37 %1 = zext i32 %a to i6438 %2 = zext i32 %b to i6439 %mul = mul i64 %1, %240 %shr = lshr i64 %mul, 3241 %tr = trunc i64 %shr to i3242 ret i32 %tr43}44 45define i64 @test_mulhd(i64 %a, i64 %b) {46; CHECK-LABEL: test_mulhd:47; CHECK: # %bb.0:48; CHECK-NEXT: mulhd r3, r3, r449; CHECK-NEXT: blr50 %1 = sext i64 %a to i12851 %2 = sext i64 %b to i12852 %mul = mul i128 %1, %253 %shr = lshr i128 %mul, 6454 %tr = trunc i128 %shr to i6455 ret i64 %tr56}57 58define i64 @test_mulhdu(i64 %a, i64 %b) {59; CHECK-LABEL: test_mulhdu:60; CHECK: # %bb.0:61; CHECK-NEXT: mulhdu r3, r3, r462; CHECK-NEXT: blr63 %1 = zext i64 %a to i12864 %2 = zext i64 %b to i12865 %mul = mul i128 %1, %266 %shr = lshr i128 %mul, 6467 %tr = trunc i128 %shr to i6468 ret i64 %tr69}70 71; When the signext attribute is present on i32, the shift operation is sra.72; We are actually transforming (sra (mul sext_in_reg, sext_in_reg)) into mulh.73define signext i32 @test_mulhw_signext(i32 %a, i32 %b) {74; CHECK-LABEL: test_mulhw_signext:75; CHECK: # %bb.0:76; CHECK-NEXT: mulhw r3, r3, r477; CHECK-NEXT: extsw r3, r378; CHECK-NEXT: blr79 %1 = sext i32 %a to i6480 %2 = sext i32 %b to i6481 %mul = mul i64 %1, %282 %shr = lshr i64 %mul, 3283 %tr = trunc i64 %shr to i3284 ret i32 %tr85}86 87define zeroext i32 @test_mulhu_zeroext(i32 %a, i32 %b) {88; CHECK-LABEL: test_mulhu_zeroext:89; CHECK: # %bb.0:90; CHECK-NEXT: mulhwu r3, r3, r491; CHECK-NEXT: clrldi r3, r3, 3292; CHECK-NEXT: blr93 %1 = zext i32 %a to i6494 %2 = zext i32 %b to i6495 %mul = mul i64 %1, %296 %shr = lshr i64 %mul, 3297 %tr = trunc i64 %shr to i3298 ret i32 %tr99}100 101define signext i64 @test_mulhd_signext(i64 %a, i64 %b) {102; CHECK-LABEL: test_mulhd_signext:103; CHECK: # %bb.0:104; CHECK-NEXT: mulhd r3, r3, r4105; CHECK-NEXT: blr106 %1 = sext i64 %a to i128107 %2 = sext i64 %b to i128108 %mul = mul i128 %1, %2109 %shr = lshr i128 %mul, 64110 %tr = trunc i128 %shr to i64111 ret i64 %tr112}113 114define zeroext i64 @test_mulhdu_zeroext(i64 %a, i64 %b) {115; CHECK-LABEL: test_mulhdu_zeroext:116; CHECK: # %bb.0:117; CHECK-NEXT: mulhdu r3, r3, r4118; CHECK-NEXT: blr119 %1 = zext i64 %a to i128120 %2 = zext i64 %b to i128121 %mul = mul i128 %1, %2122 %shr = lshr i128 %mul, 64123 %tr = trunc i128 %shr to i64124 ret i64 %tr125}126