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1; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s2; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s3 4; CHECK-LABEL: fn15define signext i32 @fn1(i32 %baz) {6 %1 = mul nsw i32 %baz, 2087 %2 = zext i32 %1 to i648 %3 = shl i64 %2, 489 %4 = ashr exact i64 %3, 4810; CHECK: RLWINM8 killed {{[^,]+}}, 0, 16, 2711; CHECK: CMPLDI12; CHECK: BCC13 14; CHECK: ANDI8_rec {{[^,]+}}, 65520, implicit-def $cr015; CHECK: COPY killed $cr016; CHECK: BCC17 %5 = icmp eq i64 %4, 018 br i1 %5, label %foo, label %bar19 20foo:21 ret i32 122 23bar:24 ret i32 025}26 27; CHECK-LABEL: fn228define signext i32 @fn2(i64 %a, i64 %b) {29; CHECK: OR8_rec {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr030; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed $cr31; CHECK: BCC 12, killed [[CREG]]32 %1 = or i64 %b, %a33 %2 = icmp sgt i64 %1, -134 br i1 %2, label %foo, label %bar35 36foo:37 ret i32 138 39bar:40 ret i32 041}42 43; CHECK-LABEL: fn344define signext i32 @fn3(i32 %a) {45; CHECK: ANDI_rec killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr046; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr047; CHECK: BCC 76, killed [[CREG]]48 %1 = and i32 %a, 1049 %2 = icmp ne i32 %1, 050 br i1 %2, label %foo, label %bar51 52foo:53 ret i32 154 55bar:56 ret i32 057}58 59; This test case confirms that a record-form instruction is60; generated even if the branch has a static branch hint.61 62; CHECK-LABEL: fn463define i64 @fn4(i64 %a, i64 %b) {64; CHECK: ADD8_rec65; CHECK-NOT: CMP66; CHECK: BCC 7167 68entry:69 %add = add nsw i64 %b, %a70 %cmp = icmp eq i64 %add, 071 br i1 %cmp, label %if.then, label %if.end72 73if.then:74 tail call void @exit(i32 signext 0) #375 unreachable76 77if.end:78 ret i64 %add79}80 81declare void @exit(i32 signext)82 83; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended.84; In this case, we want to use OR_rec instead of OR + CMPLWI.85 86; CHECK-LABEL: fn587define zeroext i32 @fn5(ptr %p1, ptr %p2) {88; CHECK: OR_rec89; CHECK-NOT: CMP90; CHECK: BCC91 %v1 = load i32, ptr %p192 %v2 = load i32, ptr %p293 %1 = or i32 %v1, %v294 %2 = icmp eq i32 %1, 095 br i1 %2, label %foo, label %bar96 97foo:98 ret i32 199 100bar:101 ret i32 0102}103 104; This test confirms record-form instructions are emitted for comparison105; against a non-zero value.106 107; CHECK-LABEL: fn6108define ptr @fn6(ptr readonly %p) {109; CHECK: LBZU110; CHECK: EXTSB_rec111; CHECK-NOT: CMP112; CHECK: BCC113; CHECK: LBZU114; CHECK: EXTSB_rec115; CHECK-NOT: CMP116; CHECK: BCC117 118entry:119 %incdec.ptr = getelementptr inbounds i8, ptr %p, i64 -1120 %0 = load i8, ptr %incdec.ptr121 %cmp = icmp sgt i8 %0, -1122 br i1 %cmp, label %out, label %if.end123 124if.end:125 %incdec.ptr2 = getelementptr inbounds i8, ptr %p, i64 -2126 %1 = load i8, ptr %incdec.ptr2127 %cmp4 = icmp sgt i8 %1, -1128 br i1 %cmp4, label %out, label %cleanup129 130out:131 %p.addr.0 = phi ptr [ %incdec.ptr, %entry ], [ %incdec.ptr2, %if.end ]132 br label %cleanup133 134cleanup:135 %retval.0 = phi ptr [ %p.addr.0, %out ], [ null, %if.end ]136 ret ptr %retval.0137}138