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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s4 5; Check that the brh/brw/brd instructions are generated for the bswap6; intrinsic for register operand on P10 and that the lhbrx/lwbrx/ldbrw7; instructions are generated for memory operand.8 9declare i16 @llvm.bswap.i16(i16)10 11define zeroext i16 @test_nomem16(i16 zeroext %a) {12; CHECK-LABEL: test_nomem16:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: brh r3, r315; CHECK-NEXT: clrldi r3, r3, 4816; CHECK-NEXT: blr17entry:18 %0 = tail call i16 @llvm.bswap.i16(i16 %a)19 ret i16 %020}21 22declare i32 @llvm.bswap.i32(i32)23 24define zeroext i32 @test_nomem32(i32 zeroext %a) {25; CHECK-LABEL: test_nomem32:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: brw r3, r328; CHECK-NEXT: clrldi r3, r3, 3229; CHECK-NEXT: blr30entry:31 %0 = tail call i32 @llvm.bswap.i32(i32 %a)32 ret i32 %033}34 35; Check that brh and clrldi are produced from a call to @llvm.bswap.i3236; followed by a right shift of 16 (and a zero-extend at the end of the DAG).37define zeroext i32 @test_bswap_shift16(i32 zeroext %a) {38; CHECK-LABEL: test_bswap_shift16:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: brh r3, r341; CHECK-NEXT: clrldi r3, r3, 4842; CHECK-NEXT: blr43entry:44 %0 = tail call i32 @llvm.bswap.i32(i32 %a)45 %shr = lshr i32 %0, 1646 ret i32 %shr47}48 49; Check that brh are produced from a call to @llvm.bswap.i3250; followed by a right shift of 16.51declare i64 @call_1()52define void @test_bswap_shift16_2() {53; CHECK-LABEL: test_bswap_shift16_2:54; CHECK: # %bb.0: # %bb55; CHECK-NEXT: mflr r056; CHECK-NEXT: std r0, 16(r1)57; CHECK-NEXT: stdu r1, -32(r1)58; CHECK-NEXT: .cfi_def_cfa_offset 3259; CHECK-NEXT: .cfi_offset lr, 1660; CHECK-NEXT: bl call_1@notoc61; CHECK-NEXT: brh r3, r362; CHECK-NEXT: rldicl r3, r3, 0, 4863; CHECK-NEXT: sth r3, 0(r3)64bb:65 switch i32 undef, label %bb1 [66 i32 78, label %bb267 ]68 69bb1:70 unreachable71 72bb2:73 %i = call i64 @call_1()74 %i3 = trunc i64 %i to i3275 %i4 = call i32 @llvm.bswap.i32(i32 %i3)76 %i5 = lshr i32 %i4, 1677 %i6 = trunc i32 %i5 to i1678 store i16 %i6, ptr undef, align 279 unreachable80}81 82define zeroext i32 @test_bswap_shift18(i32 zeroext %a) {83; CHECK-LABEL: test_bswap_shift18:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: brw r3, r386; CHECK-NEXT: rlwinm r3, r3, 14, 18, 3187; CHECK-NEXT: blr88entry:89 %0 = tail call i32 @llvm.bswap.i32(i32 %a)90 %shr = lshr i32 %0, 1891 ret i32 %shr92}93 94declare i64 @llvm.bswap.i64(i64)95 96define i64 @test_nomem64(i64 %a) {97; CHECK-LABEL: test_nomem64:98; CHECK: # %bb.0: # %entry99; CHECK-NEXT: brd r3, r3100; CHECK-NEXT: blr101entry:102 %0 = tail call i64 @llvm.bswap.i64(i64 %a)103 ret i64 %0104}105 106define i16 @test_mem16(ptr %a) {107; CHECK-LABEL: test_mem16:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: lhbrx r3, 0, r3110; CHECK-NEXT: blr111entry:112 %0 = load i16, ptr %a, align 2113 %1 = tail call i16 @llvm.bswap.i16(i16 %0)114 ret i16 %1115}116 117define i32 @test_mem32(ptr %a) {118; CHECK-LABEL: test_mem32:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: lwbrx r3, 0, r3121; CHECK-NEXT: blr122entry:123 %0 = load i32, ptr %a, align 4124 %1 = tail call i32 @llvm.bswap.i32(i32 %0)125 ret i32 %1126}127 128define i64 @test_mem64(ptr %a) {129; CHECK-LABEL: test_mem64:130; CHECK: # %bb.0: # %entry131; CHECK-NEXT: ldbrx r3, 0, r3132; CHECK-NEXT: blr133entry:134 %0 = load i64, ptr %a, align 8135 %1 = tail call i64 @llvm.bswap.i64(i64 %0)136 ret i64 %1137}138 139