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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \4; RUN: --check-prefixes=CHECK,CHECK-LE5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \6; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \7; RUN: --check-prefixes=CHECK,CHECK-BE8 9; This file does not contain many test cases involving comparisons and logical10; comparisons (cmplwi, cmpldi). This is because alternative code is generated11; when there is a compare (logical or not), followed by a sign or zero extend.12; This codegen will be re-evaluated at a later time on whether or not it should13; be emitted on P10.14 15@globalVal = common dso_local local_unnamed_addr global i8 0, align 116@globalVal2 = common dso_local local_unnamed_addr global i32 0, align 417@globalVal3 = common dso_local local_unnamed_addr global i64 0, align 818@globalVal4 = common dso_local local_unnamed_addr global i16 0, align 219 20define dso_local signext i32 @setbcr1(i8 %a) {21; CHECK-LABEL: setbcr1:22; CHECK: # %bb.0: # %entry23; CHECK-NEXT: clrlwi r3, r3, 2424; CHECK-NEXT: cmpwi r3, 125; CHECK-NEXT: setbcr r3, eq26; CHECK-NEXT: blr27entry:28 %cmp = icmp ne i8 %a, 129 %conv = zext i1 %cmp to i3230 ret i32 %conv31}32 33define dso_local signext i32 @setbcr2(i32 %a) {34; CHECK-LABEL: setbcr2:35; CHECK: # %bb.0: # %entry36; CHECK-NEXT: cmpwi r3, 137; CHECK-NEXT: setbcr r3, eq38; CHECK-NEXT: blr39entry:40 %cmp = icmp ne i32 %a, 141 %conv = zext i1 %cmp to i3242 ret i32 %conv43}44 45define dso_local signext i32 @setbcr3(i64 %a) {46; CHECK-LABEL: setbcr3:47; CHECK: # %bb.0: # %entry48; CHECK-NEXT: cmpdi r3, 149; CHECK-NEXT: setbcr r3, eq50; CHECK-NEXT: blr51entry:52 %cmp = icmp ne i64 %a, 153 %conv = zext i1 %cmp to i3254 ret i32 %conv55}56 57define dso_local signext i32 @setbcr4(i16 %a) {58; CHECK-LABEL: setbcr4:59; CHECK: # %bb.0: # %entry60; CHECK-NEXT: clrlwi r3, r3, 1661; CHECK-NEXT: cmpwi r3, 162; CHECK-NEXT: setbcr r3, eq63; CHECK-NEXT: blr64entry:65 %cmp = icmp ne i16 %a, 166 %conv = zext i1 %cmp to i3267 ret i32 %conv68}69 70define signext i64 @setbcr5(i8 %a) {71; CHECK-LABEL: setbcr5:72; CHECK: # %bb.0: # %entry73; CHECK-NEXT: clrlwi r3, r3, 2474; CHECK-NEXT: cmpwi r3, 175; CHECK-NEXT: setbcr r3, eq76; CHECK-NEXT: blr77entry:78 %cmp = icmp ne i8 %a, 179 %conv = zext i1 %cmp to i6480 ret i64 %conv81}82 83define signext i64 @setbcr6(i32 %a) {84; CHECK-LABEL: setbcr6:85; CHECK: # %bb.0: # %entry86; CHECK-NEXT: cmpwi r3, 187; CHECK-NEXT: setbcr r3, eq88; CHECK-NEXT: blr89entry:90 %cmp = icmp ne i32 %a, 191 %conv = zext i1 %cmp to i6492 ret i64 %conv93}94 95define signext i64 @setbcr7(i64 %a) {96; CHECK-LABEL: setbcr7:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: cmpdi r3, 199; CHECK-NEXT: setbcr r3, eq100; CHECK-NEXT: blr101entry:102 %cmp = icmp ne i64 %a, 1103 %conv = zext i1 %cmp to i64104 ret i64 %conv105}106 107define signext i64 @setbcr8(i16 %a) {108; CHECK-LABEL: setbcr8:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: clrlwi r3, r3, 16111; CHECK-NEXT: cmpwi r3, 1112; CHECK-NEXT: setbcr r3, eq113; CHECK-NEXT: blr114entry:115 %cmp = icmp ne i16 %a, 1116 %conv = zext i1 %cmp to i64117 ret i64 %conv118}119 120define dso_local void @setbcr9(i8 %a) {121; CHECK-LE-LABEL: setbcr9:122; CHECK-LE: # %bb.0: # %entry123; CHECK-LE-NEXT: clrlwi r3, r3, 24124; CHECK-LE-NEXT: cmpwi r3, 1125; CHECK-LE-NEXT: setbcr r3, eq126; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1127; CHECK-LE-NEXT: blr128;129; CHECK-BE-LABEL: setbcr9:130; CHECK-BE: # %bb.0: # %entry131; CHECK-BE-NEXT: clrlwi r3, r3, 24132; CHECK-BE-NEXT: addis r4, r2, globalVal@toc@ha133; CHECK-BE-NEXT: cmpwi r3, 1134; CHECK-BE-NEXT: setbcr r3, eq135; CHECK-BE-NEXT: stb r3, globalVal@toc@l(r4)136; CHECK-BE-NEXT: blr137entry:138 %cmp = icmp ne i8 %a, 1139 %conv1 = zext i1 %cmp to i8140 store i8 %conv1, ptr @globalVal, align 1141 ret void142}143 144define dso_local void @setbcr10(i32 %a) {145; CHECK-LE-LABEL: setbcr10:146; CHECK-LE: # %bb.0: # %entry147; CHECK-LE-NEXT: cmpwi r3, 1148; CHECK-LE-NEXT: setbcr r3, eq149; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1150; CHECK-LE-NEXT: blr151;152; CHECK-BE-LABEL: setbcr10:153; CHECK-BE: # %bb.0: # %entry154; CHECK-BE-NEXT: cmpwi r3, 1155; CHECK-BE-NEXT: addis r4, r2, globalVal2@toc@ha156; CHECK-BE-NEXT: setbcr r3, eq157; CHECK-BE-NEXT: stw r3, globalVal2@toc@l(r4)158; CHECK-BE-NEXT: blr159entry:160 %cmp = icmp ne i32 %a, 1161 %conv1 = zext i1 %cmp to i32162 store i32 %conv1, ptr @globalVal2, align 4163 ret void164}165 166define dso_local void @setbcr11(i64 %a) {167; CHECK-LE-LABEL: setbcr11:168; CHECK-LE: # %bb.0: # %entry169; CHECK-LE-NEXT: cmpdi r3, 1170; CHECK-LE-NEXT: setbcr r3, eq171; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1172; CHECK-LE-NEXT: blr173;174; CHECK-BE-LABEL: setbcr11:175; CHECK-BE: # %bb.0: # %entry176; CHECK-BE-NEXT: cmpdi r3, 1177; CHECK-BE-NEXT: addis r4, r2, globalVal3@toc@ha178; CHECK-BE-NEXT: setbcr r3, eq179; CHECK-BE-NEXT: std r3, globalVal3@toc@l(r4)180; CHECK-BE-NEXT: blr181entry:182 %cmp = icmp ne i64 %a, 1183 %conv1 = zext i1 %cmp to i64184 store i64 %conv1, ptr @globalVal3, align 8185 ret void186}187 188define dso_local void @setbcr12(i16 %a) {189; CHECK-LE-LABEL: setbcr12:190; CHECK-LE: # %bb.0: # %entry191; CHECK-LE-NEXT: clrlwi r3, r3, 16192; CHECK-LE-NEXT: cmpwi r3, 1193; CHECK-LE-NEXT: setbcr r3, eq194; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1195; CHECK-LE-NEXT: blr196;197; CHECK-BE-LABEL: setbcr12:198; CHECK-BE: # %bb.0: # %entry199; CHECK-BE-NEXT: clrlwi r3, r3, 16200; CHECK-BE-NEXT: addis r4, r2, globalVal4@toc@ha201; CHECK-BE-NEXT: cmpwi r3, 1202; CHECK-BE-NEXT: setbcr r3, eq203; CHECK-BE-NEXT: sth r3, globalVal4@toc@l(r4)204; CHECK-BE-NEXT: blr205entry:206 %cmp = icmp ne i16 %a, 1207 %conv1 = zext i1 %cmp to i16208 store i16 %conv1, ptr @globalVal4, align 2209 ret void210}211 212