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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8 9; This test case tests spilling the CR EQ bit on Power10. On Power10, this is10; achieved by setb %reg, %CRREG (eq bit) -> stw %reg, $FI instead of:11; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.12 13; Without fine-grained control over clobbering individual CR bits,14; it is difficult to produce a concise test case that will ensure a specific15; bit of any CR field is spilled. We need to test the spilling of a CR bit16; other than the LT bit. Hence this test case is rather complex.17 18%0 = type { i32, ptr, ptr, [1 x i8], ptr, ptr, ptr, ptr, i64, i32, [20 x i8] }19%1 = type { ptr, ptr, i32 }20%2 = type { [200 x i8], [200 x i8], ptr, ptr, ptr, ptr, ptr, ptr, ptr, i64 }21%3 = type { i64, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i64, i32, i32 }22%4 = type { i32, i64, ptr, ptr, i16, ptr, ptr, i64, i64 }23 24define dso_local double @P10_Spill_CR_EQ(ptr %arg) local_unnamed_addr #0 {25; CHECK-LABEL: P10_Spill_CR_EQ:26; CHECK: # %bb.0: # %bb27; CHECK-NEXT: ld r3, 0(r3)28; CHECK-NEXT: ld r4, 0(0)29; CHECK-NEXT: cmpdi r3, 030; CHECK-NEXT: ld r5, 56(0)31; CHECK-NEXT: cmpdi cr1, r4, 032; CHECK-NEXT: cmpdi cr5, r5, 033; CHECK-NEXT: cmpldi cr6, r3, 034; CHECK-NEXT: beq cr6, .LBB0_335; CHECK-NEXT: # %bb.1: # %bb1036; CHECK-NEXT: lwz r3, 0(r3)37; CHECK-NEXT: bc 12, 4*cr1+eq, .LBB0_438; CHECK-NEXT: .LBB0_2: # %bb1439; CHECK-NEXT: lwz r5, 0(r3)40; CHECK-NEXT: b .LBB0_541; CHECK-NEXT: .LBB0_3:42; CHECK-NEXT: # implicit-def: $r343; CHECK-NEXT: bc 4, 4*cr1+eq, .LBB0_244; CHECK-NEXT: .LBB0_4:45; CHECK-NEXT: # implicit-def: $r546; CHECK-NEXT: .LBB0_5: # %bb1647; CHECK-NEXT: crnot 4*cr1+lt, eq48; CHECK-NEXT: crnot 4*cr5+un, 4*cr5+eq49; CHECK-NEXT: bc 12, 4*cr5+eq, .LBB0_750; CHECK-NEXT: # %bb.6: # %bb1851; CHECK-NEXT: lwz r4, 0(r3)52; CHECK-NEXT: b .LBB0_853; CHECK-NEXT: .LBB0_7:54; CHECK-NEXT: # implicit-def: $r455; CHECK-NEXT: .LBB0_8: # %bb2056; CHECK-NEXT: mfcr r1257; CHECK-NEXT: cmpwi cr3, r4, -158; CHECK-NEXT: cmpwi cr2, r3, -159; CHECK-NEXT: stw r12, 8(r1)60; CHECK-NEXT: cmpwi cr7, r3, 061; CHECK-NEXT: cmpwi cr6, r4, 062; CHECK-NEXT: crand 4*cr5+lt, 4*cr3+gt, 4*cr5+un63; CHECK-NEXT: crand 4*cr5+gt, 4*cr2+gt, 4*cr1+lt64; CHECK-NEXT: # implicit-def: $x365; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_1066; CHECK-NEXT: # %bb.9: # %bb3467; CHECK-NEXT: ld r3, 0(r3)68; CHECK-NEXT: .LBB0_10: # %bb3669; CHECK-NEXT: cmpwi cr2, r5, 070; CHECK-NEXT: # implicit-def: $x471; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_1272; CHECK-NEXT: # %bb.11: # %bb3873; CHECK-NEXT: ld r4, 0(r3)74; CHECK-NEXT: .LBB0_12: # %bb4075; CHECK-NEXT: crand 4*cr6+gt, 4*cr7+lt, 4*cr1+lt76; CHECK-NEXT: crand 4*cr6+lt, 4*cr6+lt, 4*cr5+un77; CHECK-NEXT: crnot 4*cr6+un, 4*cr1+eq78; CHECK-NEXT: # implicit-def: $x679; CHECK-NEXT: bc 4, 4*cr6+lt, .LBB0_1480; CHECK-NEXT: # %bb.13: # %bb4881; CHECK-NEXT: ld r6, 0(r3)82; CHECK-NEXT: .LBB0_14: # %bb5083; CHECK-NEXT: cmpwi cr3, r5, -184; CHECK-NEXT: crand 4*cr7+lt, 4*cr2+lt, 4*cr6+un85; CHECK-NEXT: # implicit-def: $r586; CHECK-NEXT: bc 4, 4*cr6+gt, .LBB0_1687; CHECK-NEXT: # %bb.15: # %bb5288; CHECK-NEXT: lwz r5, 0(r3)89; CHECK-NEXT: .LBB0_16: # %bb5490; CHECK-NEXT: mfocrf r7, 12891; CHECK-NEXT: stw r7, -4(r1)92; CHECK-NEXT: # implicit-def: $r793; CHECK-NEXT: bc 4, 4*cr7+lt, .LBB0_1894; CHECK-NEXT: # %bb.17: # %bb5695; CHECK-NEXT: lwz r7, 0(r3)96; CHECK-NEXT: .LBB0_18: # %bb5897; CHECK-NEXT: lwz r6, 92(r6)98; CHECK-NEXT: cmpwi cr4, r7, 199; CHECK-NEXT: crand 4*cr7+un, 4*cr3+gt, 4*cr6+un100; CHECK-NEXT: cmpwi cr3, r5, 1101; CHECK-NEXT: crand 4*cr7+gt, 4*cr7+eq, 4*cr1+lt102; CHECK-NEXT: # implicit-def: $x5103; CHECK-NEXT: crand 4*cr6+un, 4*cr2+eq, 4*cr6+un104; CHECK-NEXT: crand 4*cr5+un, 4*cr6+eq, 4*cr5+un105; CHECK-NEXT: crand 4*cr7+lt, 4*cr4+lt, 4*cr7+lt106; CHECK-NEXT: crand 4*cr6+gt, 4*cr3+lt, 4*cr6+gt107; CHECK-NEXT: cmpwi r6, 1108; CHECK-NEXT: crand 4*cr6+lt, lt, 4*cr6+lt109; CHECK-NEXT: bc 4, 4*cr6+gt, .LBB0_20110; CHECK-NEXT: # %bb.19: # %bb68111; CHECK-NEXT: ld r5, 0(r3)112; CHECK-NEXT: .LBB0_20: # %bb70113; CHECK-NEXT: ld r6, 0(r3)114; CHECK-NEXT: lwz r9, -4(r1)115; CHECK-NEXT: crandc 4*cr5+gt, 4*cr5+gt, 4*cr7+eq116; CHECK-NEXT: crandc 4*cr7+eq, 4*cr7+un, 4*cr2+eq117; CHECK-NEXT: crandc 4*cr5+lt, 4*cr5+lt, 4*cr6+eq118; CHECK-NEXT: setbc r7, 4*cr6+un119; CHECK-NEXT: setbc r8, 4*cr5+un120; CHECK-NEXT: lwz r12, 8(r1)121; CHECK-NEXT: xxlxor f2, f2, f2122; CHECK-NEXT: isel r3, r3, r5, 4*cr5+gt123; CHECK-NEXT: setbc r5, 4*cr7+gt124; CHECK-NEXT: crnor 4*cr5+gt, 4*cr6+gt, 4*cr5+gt125; CHECK-NEXT: crnor 4*cr6+gt, 4*cr7+lt, 4*cr7+eq126; CHECK-NEXT: crnor 4*cr5+lt, 4*cr6+lt, 4*cr5+lt127; CHECK-NEXT: add r5, r7, r5128; CHECK-NEXT: add r5, r8, r5129; CHECK-NEXT: isel r3, 0, r3, 4*cr5+gt130; CHECK-NEXT: isel r4, 0, r4, 4*cr5+lt131; CHECK-NEXT: isel r6, 0, r6, 4*cr6+gt132; CHECK-NEXT: mtocrf 128, r9133; CHECK-NEXT: mtfprd f0, r5134; CHECK-NEXT: isel r4, 0, r4, 4*cr5+eq135; CHECK-NEXT: mtocrf 32, r12136; CHECK-NEXT: mtocrf 16, r12137; CHECK-NEXT: mtocrf 8, r12138; CHECK-NEXT: iseleq r3, 0, r3139; CHECK-NEXT: isel r6, 0, r6, 4*cr1+eq140; CHECK-NEXT: xscvsxddp f0, f0141; CHECK-NEXT: add r3, r6, r3142; CHECK-NEXT: add r3, r4, r3143; CHECK-NEXT: mtfprd f1, r3144; CHECK-NEXT: xsmuldp f0, f0, f2145; CHECK-NEXT: xscvsxddp f1, f1146; CHECK-NEXT: xsadddp f1, f0, f1147; CHECK-NEXT: blr148bb:149 %tmp = getelementptr inbounds %4, ptr null, i64 undef, i32 7150 %tmp1 = load i64, ptr undef, align 8151 %tmp2 = load i64, ptr null, align 8152 %tmp3 = load i64, ptr %tmp, align 8153 %tmp4 = icmp eq i64 %tmp1, 0154 %tmp5 = icmp eq i64 %tmp2, 0155 %tmp6 = icmp eq i64 %tmp3, 0156 %tmp7 = xor i1 %tmp4, true157 %tmp8 = xor i1 %tmp5, true158 %tmp9 = xor i1 %tmp6, true159 br i1 %tmp4, label %bb12, label %bb10160 161bb10: ; preds = %bb162 %tmp11 = load i32, ptr undef, align 8163 br label %bb12164 165bb12: ; preds = %bb10, %bb166 %tmp13 = phi i32 [ undef, %bb ], [ %tmp11, %bb10 ]167 br i1 %tmp5, label %bb16, label %bb14168 169bb14: ; preds = %bb12170 %tmp15 = load i32, ptr undef, align 8171 br label %bb16172 173bb16: ; preds = %bb14, %bb12174 %tmp17 = phi i32 [ undef, %bb12 ], [ %tmp15, %bb14 ]175 br i1 %tmp6, label %bb20, label %bb18176 177bb18: ; preds = %bb16178 %tmp19 = load i32, ptr undef, align 8179 br label %bb20180 181bb20: ; preds = %bb18, %bb16182 %tmp21 = phi i32 [ undef, %bb16 ], [ %tmp19, %bb18 ]183 %tmp22 = icmp slt i32 %tmp13, 0184 %tmp23 = icmp slt i32 %tmp17, 0185 %tmp24 = icmp slt i32 %tmp21, 0186 %tmp25 = icmp eq i32 %tmp13, 0187 %tmp26 = icmp eq i32 %tmp17, 0188 %tmp27 = icmp eq i32 %tmp21, 0189 %tmp28 = xor i1 %tmp22, true190 %tmp29 = xor i1 %tmp23, true191 %tmp30 = xor i1 %tmp24, true192 %tmp31 = and i1 %tmp28, %tmp7193 %tmp32 = and i1 %tmp29, %tmp8194 %tmp33 = and i1 %tmp30, %tmp9195 br i1 %tmp31, label %bb34, label %bb36196 197bb34: ; preds = %bb20198 %tmp35 = load i64, ptr undef, align 8199 br label %bb36200 201bb36: ; preds = %bb34, %bb20202 %tmp37 = phi i64 [ undef, %bb20 ], [ %tmp35, %bb34 ]203 br i1 %tmp33, label %bb38, label %bb40204 205bb38: ; preds = %bb36206 %tmp39 = load i64, ptr undef, align 8207 br label %bb40208 209bb40: ; preds = %bb38, %bb36210 %tmp41 = phi i64 [ undef, %bb36 ], [ %tmp39, %bb38 ]211 %tmp42 = and i1 %tmp25, %tmp7212 %tmp43 = and i1 %tmp26, %tmp8213 %tmp44 = and i1 %tmp27, %tmp9214 %tmp45 = and i1 %tmp22, %tmp7215 %tmp46 = and i1 %tmp23, %tmp8216 %tmp47 = and i1 %tmp24, %tmp9217 br i1 %tmp47, label %bb48, label %bb50218 219bb48: ; preds = %bb40220 %tmp49 = load ptr, ptr undef, align 8221 br label %bb50222 223bb50: ; preds = %bb48, %bb40224 %tmp51 = phi ptr [ undef, %bb40 ], [ %tmp49, %bb48 ]225 br i1 %tmp45, label %bb52, label %bb54226 227bb52: ; preds = %bb50228 %tmp53 = load i32, ptr undef, align 8229 br label %bb54230 231bb54: ; preds = %bb52, %bb50232 %tmp55 = phi i32 [ undef, %bb50 ], [ %tmp53, %bb52 ]233 br i1 %tmp46, label %bb56, label %bb58234 235bb56: ; preds = %bb54236 %tmp57 = load i32, ptr undef, align 8237 br label %bb58238 239bb58: ; preds = %bb56, %bb54240 %tmp59 = phi i32 [ undef, %bb54 ], [ %tmp57, %bb56 ]241 %tmp60 = getelementptr inbounds %3, ptr %tmp51, i64 0, i32 12242 %tmp61 = load i32, ptr %tmp60, align 8243 %tmp62 = icmp slt i32 %tmp55, 1244 %tmp63 = icmp slt i32 %tmp59, 1245 %tmp64 = icmp slt i32 %tmp61, 1246 %tmp65 = and i1 %tmp62, %tmp45247 %tmp66 = and i1 %tmp63, %tmp46248 %tmp67 = and i1 %tmp64, %tmp47249 br i1 %tmp65, label %bb68, label %bb70250 251bb68: ; preds = %bb58252 %tmp69 = load i64, ptr undef, align 8253 br label %bb70254 255bb70: ; preds = %bb68, %bb58256 %tmp71 = phi i64 [ undef, %bb58 ], [ %tmp69, %bb68 ]257 %tmp72 = load i64, ptr undef, align 8258 %tmp73 = xor i1 %tmp25, true259 %tmp74 = xor i1 %tmp26, true260 %tmp75 = xor i1 %tmp27, true261 %tmp76 = and i1 %tmp31, %tmp73262 %tmp77 = and i1 %tmp32, %tmp74263 %tmp78 = and i1 %tmp33, %tmp75264 %tmp79 = select i1 %tmp76, i64 %tmp37, i64 %tmp71265 %tmp80 = select i1 %tmp77, i64 undef, i64 %tmp72266 %tmp81 = select i1 %tmp78, i64 %tmp41, i64 undef267 %tmp82 = or i1 %tmp65, %tmp76268 %tmp83 = or i1 %tmp66, %tmp77269 %tmp84 = or i1 %tmp67, %tmp78270 %tmp85 = zext i1 %tmp42 to i64271 %tmp86 = add i64 0, %tmp85272 %tmp87 = zext i1 %tmp43 to i64273 %tmp88 = add i64 0, %tmp87274 %tmp89 = zext i1 %tmp44 to i64275 %tmp90 = add i64 0, %tmp89276 %tmp91 = select i1 %tmp82, i64 %tmp79, i64 0277 %tmp92 = add i64 0, %tmp91278 %tmp93 = select i1 %tmp83, i64 %tmp80, i64 0279 %tmp94 = add i64 0, %tmp93280 %tmp95 = select i1 %tmp84, i64 %tmp81, i64 0281 %tmp96 = add i64 0, %tmp95282 %tmp97 = select i1 %tmp42, i64 undef, i64 %tmp92283 %tmp98 = select i1 %tmp43, i64 undef, i64 %tmp94284 %tmp99 = select i1 %tmp44, i64 undef, i64 %tmp96285 %tmp100 = select i1 %tmp4, i64 0, i64 %tmp97286 %tmp101 = select i1 %tmp5, i64 0, i64 %tmp98287 %tmp102 = select i1 %tmp6, i64 0, i64 %tmp99288 %tmp103 = add i64 %tmp88, %tmp86289 %tmp104 = add i64 %tmp90, %tmp103290 %tmp105 = add i64 0, %tmp104291 %tmp106 = add i64 %tmp101, %tmp100292 %tmp107 = add i64 %tmp102, %tmp106293 %tmp108 = add i64 0, %tmp107294 %tmp109 = sitofp i64 %tmp105 to double295 %tmp110 = sitofp i64 %tmp108 to double296 %tmp111 = fmul double %tmp109, 0.000000e+00297 %tmp112 = fadd double %tmp111, %tmp110298 ret double %tmp112299}300