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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \3; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | \4; RUN: FileCheck %s5 6; Function Attrs: norecurse nounwind readnone7define <4 x i32> @test_xxsplti32dx_1(<4 x i32> %a) {8; CHECK-LABEL: test_xxsplti32dx_1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: xxsplti32dx vs34, 0, 56611; CHECK-NEXT: blr12entry:13 %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 566, i32 undef, i32 566>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>14 ret <4 x i32> %vecins115}16 17; Function Attrs: norecurse nounwind readnone18define <4 x i32> @test_xxsplti32dx_2(<4 x i32> %a) {19; CHECK-LABEL: test_xxsplti32dx_2:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: xxsplti32dx vs34, 1, 3322; CHECK-NEXT: blr23entry:24 %vecins1 = shufflevector <4 x i32> <i32 33, i32 undef, i32 33, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>25 ret <4 x i32> %vecins126}27 28; Function Attrs: norecurse nounwind readnone29define <4 x i32> @test_xxsplti32dx_3(<4 x i32> %a) {30; CHECK-LABEL: test_xxsplti32dx_3:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: xxsplti32dx vs34, 0, 1233; CHECK-NEXT: blr34entry:35 %vecins1 = shufflevector <4 x i32> %a, <4 x i32> <i32 undef, i32 12, i32 undef, i32 12>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>36 ret <4 x i32> %vecins137}38 39; Function Attrs: norecurse nounwind readnone40define <4 x i32> @test_xxsplti32dx_4(<4 x i32> %a) {41; CHECK-LABEL: test_xxsplti32dx_4:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: xxsplti32dx vs34, 1, -68344; CHECK-NEXT: blr45entry:46 %vecins1 = shufflevector <4 x i32> <i32 -683, i32 undef, i32 -683, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>47 ret <4 x i32> %vecins148}49 50; Function Attrs: nounwind51define <4 x float> @test_xxsplti32dx_5(<4 x float> %vfa) {52; CHECK-LABEL: test_xxsplti32dx_5:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: xxsplti32dx vs34, 0, 106535321655; CHECK-NEXT: blr56entry:57 %vecins3.i = shufflevector <4 x float> %vfa, <4 x float> <float undef, float 1.000000e+00, float undef, float 1.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>58 ret <4 x float> %vecins3.i59}60 61; Function Attrs: nounwind62define <4 x float> @test_xxsplti32dx_6(<4 x float> %vfa) {63; CHECK-LABEL: test_xxsplti32dx_6:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: xxsplti32dx vs34, 1, 107374182466; CHECK-NEXT: blr67entry:68 %vecins3.i = shufflevector <4 x float> <float 2.000000e+00, float undef, float 2.000000e+00, float undef>, <4 x float> %vfa, <4 x i32> <i32 0, i32 5, i32 2, i32 7>69 ret <4 x float> %vecins3.i70}71 72; Function Attrs: norecurse nounwind readnone73; Test to illustrate when the splat is narrower than 32-bits.74define dso_local <4 x i32> @test_xxsplti32dx_7(<4 x i32> %a) local_unnamed_addr #0 {75; CHECK-LABEL: test_xxsplti32dx_7:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: xxsplti32dx vs34, 1, -141481275778; CHECK-NEXT: blr79entry:80 %vecins1 = shufflevector <4 x i32> <i32 -1414812757, i32 undef, i32 -1414812757, i32 undef>, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 2, i32 7>81 ret <4 x i32> %vecins182}83 84define dso_local <2 x double> @test_xxsplti32dx_8() {85; CHECK-LABEL: test_xxsplti32dx_8:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: xxsplti32dx vs34, 0, 108266016788; CHECK-NEXT: xxsplti32dx vs34, 1, -137438953589; CHECK-NEXT: blr90entry:91 ret <2 x double> <double 0x40881547AE147AE1, double 0x40881547AE147AE1>92}93 94define dso_local <8 x i16> @test_xxsplti32dx_9() {95; CHECK-LABEL: test_xxsplti32dx_9:96; CHECK: # %bb.0: # %entry97; CHECK-NEXT: xxsplti32dx vs34, 0, 2385527798; CHECK-NEXT: xxsplti32dx vs34, 1, 6582799; CHECK-NEXT: blr100entry:101 ret <8 x i16> <i16 291, i16 undef, i16 undef, i16 364, i16 undef, i16 1, i16 173, i16 undef>102}103 104define dso_local <16 x i8> @constSplatBug() {105; CHECK-LABEL: constSplatBug:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: xxlxor vs34, vs34, vs34108; CHECK-NEXT: xxsplti32dx vs34, 0, 1191182336109; CHECK-NEXT: blr110entry:111 ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 71>112}113