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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8 9; These test cases aim to test the vector string isolate builtins on Power10.10 11declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)12declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)13 14define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {15; CHECK-LABEL: test_vclrlb:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: vclrlb v2, v2, r518; CHECK-NEXT: blr19entry:20 %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)21 ret <16 x i8> %tmp22}23 24define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {25; CHECK-LABEL: test_vclrrb:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vclrrb v2, v2, r528; CHECK-NEXT: blr29entry:30 %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)31 ret <16 x i8> %tmp32}33 34declare <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8>)35declare <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>)36declare <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16>)37declare <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16>)38 39declare i32 @llvm.ppc.altivec.vstribr.p(i32, <16 x i8>)40declare i32 @llvm.ppc.altivec.vstribl.p(i32, <16 x i8>)41declare i32 @llvm.ppc.altivec.vstrihr.p(i32, <8 x i16>)42declare i32 @llvm.ppc.altivec.vstrihl.p(i32, <8 x i16>)43 44define <16 x i8> @test_vstribr(<16 x i8> %a) {45; CHECK-LABEL: test_vstribr:46; CHECK: # %bb.0: # %entry47; CHECK-NEXT: vstribr v2, v248; CHECK-NEXT: blr49entry:50 %tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8> %a)51 ret <16 x i8> %tmp52}53 54define <16 x i8> @test_vstribl(<16 x i8> %a) {55; CHECK-LABEL: test_vstribl:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: vstribl v2, v258; CHECK-NEXT: blr59entry:60 %tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>%a)61 ret <16 x i8> %tmp62}63 64define <8 x i16> @test_vstrihr(<8 x i16> %a) {65; CHECK-LABEL: test_vstrihr:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: vstrihr v2, v268; CHECK-NEXT: blr69entry:70 %tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16> %a)71 ret <8 x i16> %tmp72}73 74define <8 x i16> @test_vstrihl(<8 x i16> %a) {75; CHECK-LABEL: test_vstrihl:76; CHECK: # %bb.0: # %entry77; CHECK-NEXT: vstrihl v2, v278; CHECK-NEXT: blr79entry:80 %tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16> %a)81 ret <8 x i16> %tmp82}83 84define i32 @test_vstribr_p(<16 x i8> %a) {85; CHECK-LABEL: test_vstribr_p:86; CHECK: # %bb.0: # %entry87; CHECK-NEXT: vstribr. v2, v288; CHECK-NEXT: setbc r3, 4*cr6+eq89; CHECK-NEXT: blr90entry:91 %tmp = tail call i32 @llvm.ppc.altivec.vstribr.p(i32 1, <16 x i8> %a)92 ret i32 %tmp93}94 95define i32 @test_vstribl_p(<16 x i8> %a) {96; CHECK-LABEL: test_vstribl_p:97; CHECK: # %bb.0: # %entry98; CHECK-NEXT: vstribl. v2, v299; CHECK-NEXT: setbc r3, 4*cr6+eq100; CHECK-NEXT: blr101entry:102 %tmp = tail call i32 @llvm.ppc.altivec.vstribl.p(i32 1, <16 x i8> %a)103 ret i32 %tmp104}105 106define i32 @test_vstrihr_p(<8 x i16> %a) {107; CHECK-LABEL: test_vstrihr_p:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vstrihr. v2, v2110; CHECK-NEXT: setbc r3, 4*cr6+eq111; CHECK-NEXT: blr112entry:113 %tmp = tail call i32 @llvm.ppc.altivec.vstrihr.p(i32 1, <8 x i16> %a)114 ret i32 %tmp115}116 117define i32 @test_vstrihl_p(<8 x i16> %a) {118; CHECK-LABEL: test_vstrihl_p:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vstrihl. v2, v2121; CHECK-NEXT: setbc r3, 4*cr6+eq122; CHECK-NEXT: blr123entry:124 %tmp = tail call i32 @llvm.ppc.altivec.vstrihl.p(i32 1, <8 x i16> %a)125 ret i32 %tmp126}127