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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \9; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s11 12; This test case aims to test the vector mask manipulation operations13; on Power10.14 15declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)16declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)17declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)18declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)19declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)20 21define i32 @test_vextractbm(<16 x i8> %a) {22; CHECK-LABEL: test_vextractbm:23; CHECK: # %bb.0: # %entry24; CHECK-NEXT: vextractbm r3, v225; CHECK-NEXT: blr26entry:27 %ext = tail call i32 @llvm.ppc.altivec.vextractbm(<16 x i8> %a)28 ret i32 %ext29}30 31define i32 @test_vextracthm(<8 x i16> %a) {32; CHECK-LABEL: test_vextracthm:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: vextracthm r3, v235; CHECK-NEXT: blr36entry:37 %ext = tail call i32 @llvm.ppc.altivec.vextracthm(<8 x i16> %a)38 ret i32 %ext39}40 41define i32 @test_vextractwm(<4 x i32> %a) {42; CHECK-LABEL: test_vextractwm:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vextractwm r3, v245; CHECK-NEXT: blr46entry:47 %ext = tail call i32 @llvm.ppc.altivec.vextractwm(<4 x i32> %a)48 ret i32 %ext49}50 51define i32 @test_vextractdm(<2 x i64> %a) {52; CHECK-LABEL: test_vextractdm:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vextractdm r3, v255; CHECK-NEXT: blr56entry:57 %ext = tail call i32 @llvm.ppc.altivec.vextractdm(<2 x i64> %a)58 ret i32 %ext59}60 61define i32 @test_vextractqm(<1 x i128> %a) {62; CHECK-LABEL: test_vextractqm:63; CHECK: # %bb.0: # %entry64; CHECK-NEXT: vextractqm r3, v265; CHECK-NEXT: blr66entry:67 %ext = tail call i32 @llvm.ppc.altivec.vextractqm(<1 x i128> %a)68 ret i32 %ext69}70 71declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>)72declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>)73declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>)74declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>)75declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>)76 77define <16 x i8> @test_vexpandbm(<16 x i8> %a) {78; CHECK-LABEL: test_vexpandbm:79; CHECK: # %bb.0: # %entry80; CHECK-NEXT: vexpandbm v2, v281; CHECK-NEXT: blr82entry:83 %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a)84 ret <16 x i8> %exp85}86 87define <8 x i16> @test_vexpandhm(<8 x i16> %a) {88; CHECK-LABEL: test_vexpandhm:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vexpandhm v2, v291; CHECK-NEXT: blr92entry:93 %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a)94 ret <8 x i16> %exp95}96 97define <4 x i32> @test_vexpandwm(<4 x i32> %a) {98; CHECK-LABEL: test_vexpandwm:99; CHECK: # %bb.0: # %entry100; CHECK-NEXT: vexpandwm v2, v2101; CHECK-NEXT: blr102entry:103 %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a)104 ret <4 x i32> %exp105}106 107define <2 x i64> @test_vexpanddm(<2 x i64> %a) {108; CHECK-LABEL: test_vexpanddm:109; CHECK: # %bb.0: # %entry110; CHECK-NEXT: vexpanddm v2, v2111; CHECK-NEXT: blr112entry:113 %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a)114 ret <2 x i64> %exp115}116 117define <1 x i128> @test_vexpandqm(<1 x i128> %a) {118; CHECK-LABEL: test_vexpandqm:119; CHECK: # %bb.0: # %entry120; CHECK-NEXT: vexpandqm v2, v2121; CHECK-NEXT: blr122entry:123 %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)124 ret <1 x i128> %exp125}126 127declare i64 @llvm.ppc.altivec.vcntmbb(<16 x i8>, i32)128declare i64 @llvm.ppc.altivec.vcntmbh(<8 x i16>, i32)129declare i64 @llvm.ppc.altivec.vcntmbw(<4 x i32>, i32)130declare i64 @llvm.ppc.altivec.vcntmbd(<2 x i64>, i32)131 132define i64 @test_vcntmbb(<16 x i8> %a) {133; CHECK-LABEL: test_vcntmbb:134; CHECK: # %bb.0: # %entry135; CHECK-NEXT: vcntmbb r3, v2, 1136; CHECK-NEXT: blr137entry:138 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbb(<16 x i8> %a, i32 1)139 ret i64 %cnt140}141 142define i64 @test_vcntmbh(<8 x i16> %a) {143; CHECK-LABEL: test_vcntmbh:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: vcntmbh r3, v2, 0146; CHECK-NEXT: blr147entry:148 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbh(<8 x i16> %a, i32 0)149 ret i64 %cnt150}151 152define i64 @test_vcntmbw(<4 x i32> %a) {153; CHECK-LABEL: test_vcntmbw:154; CHECK: # %bb.0: # %entry155; CHECK-NEXT: vcntmbw r3, v2, 1156; CHECK-NEXT: blr157entry:158 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbw(<4 x i32> %a, i32 1)159 ret i64 %cnt160}161 162define i64 @test_vcntmbd(<2 x i64> %a) {163; CHECK-LABEL: test_vcntmbd:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vcntmbd r3, v2, 0166; CHECK-NEXT: blr167entry:168 %cnt = tail call i64 @llvm.ppc.altivec.vcntmbd(<2 x i64> %a, i32 0)169 ret i64 %cnt170}171 172declare <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64)173declare <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64)174declare <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64)175declare <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64)176declare <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64)177 178define <16 x i8> @test_mtvsrbm(i64 %a) {179; CHECK-LABEL: test_mtvsrbm:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: mtvsrbm v2, r3182; CHECK-NEXT: blr183entry:184 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 %a)185 ret <16 x i8> %mv186}187 188define <16 x i8> @test_mtvsrbmi() {189; CHECK-LABEL: test_mtvsrbmi:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: mtvsrbmi v2, 1192; CHECK-NEXT: blr193entry:194 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 1)195 ret <16 x i8> %mv196}197 198define <16 x i8> @test_mtvsrbmi2() {199; CHECK-LABEL: test_mtvsrbmi2:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: mtvsrbmi v2, 255202; CHECK-NEXT: blr203entry:204 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 255)205 ret <16 x i8> %mv206}207 208define <16 x i8> @test_mtvsrbmi3() {209; CHECK-LABEL: test_mtvsrbmi3:210; CHECK: # %bb.0: # %entry211; CHECK-NEXT: mtvsrbmi v2, 65535212; CHECK-NEXT: blr213entry:214 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65535)215 ret <16 x i8> %mv216}217 218define <16 x i8> @test_mtvsrbmi4() {219; CHECK-LABEL: test_mtvsrbmi4:220; CHECK: # %bb.0: # %entry221; CHECK-NEXT: mtvsrbmi v2, 0222; CHECK-NEXT: blr223entry:224 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65536)225 ret <16 x i8> %mv226}227 228define <16 x i8> @test_mtvsrbmi5() {229; CHECK-LABEL: test_mtvsrbmi5:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: mtvsrbmi v2, 10232; CHECK-NEXT: blr233entry:234 %mv = tail call <16 x i8> @llvm.ppc.altivec.mtvsrbm(i64 65546)235 ret <16 x i8> %mv236}237 238define <8 x i16> @test_mtvsrhm(i64 %a) {239; CHECK-LABEL: test_mtvsrhm:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: mtvsrhm v2, r3242; CHECK-NEXT: blr243entry:244 %mv = tail call <8 x i16> @llvm.ppc.altivec.mtvsrhm(i64 %a)245 ret <8 x i16> %mv246}247 248define <4 x i32> @test_mtvsrwm(i64 %a) {249; CHECK-LABEL: test_mtvsrwm:250; CHECK: # %bb.0: # %entry251; CHECK-NEXT: mtvsrwm v2, r3252; CHECK-NEXT: blr253entry:254 %mv = tail call <4 x i32> @llvm.ppc.altivec.mtvsrwm(i64 %a)255 ret <4 x i32> %mv256}257 258define <2 x i64> @test_mtvsrdm(i64 %a) {259; CHECK-LABEL: test_mtvsrdm:260; CHECK: # %bb.0: # %entry261; CHECK-NEXT: mtvsrdm v2, r3262; CHECK-NEXT: blr263entry:264 %mv = tail call <2 x i64> @llvm.ppc.altivec.mtvsrdm(i64 %a)265 ret <2 x i64> %mv266}267 268define <1 x i128> @test_mtvsrqm(i64 %a) {269; CHECK-LABEL: test_mtvsrqm:270; CHECK: # %bb.0: # %entry271; CHECK-NEXT: mtvsrqm v2, r3272; CHECK-NEXT: blr273entry:274 %mv = tail call <1 x i128> @llvm.ppc.altivec.mtvsrqm(i64 %a)275 ret <1 x i128> %mv276}277