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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \9; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \10; RUN: FileCheck %s11 12; This test case aims to test the vector modulo instructions on Power10.13; The vector modulo instructions operate on signed and unsigned words14; and doublewords.15 16; The vector modulo instructions operate on signed and unsigned words,17; doublewords and 128-bit values.18 19 20define <1 x i128> @test_vmodsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {21; CHECK-LABEL: test_vmodsq:22; CHECK: # %bb.0:23; CHECK-NEXT: vmodsq v2, v2, v324; CHECK-NEXT: blr25 %tmp = srem <1 x i128> %x, %y26 ret <1 x i128> %tmp27}28 29define <1 x i128> @test_vmoduq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {30; CHECK-LABEL: test_vmoduq:31; CHECK: # %bb.0:32; CHECK-NEXT: vmoduq v2, v2, v333; CHECK-NEXT: blr34 %tmp = urem <1 x i128> %x, %y35 ret <1 x i128> %tmp36}37 38define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {39; CHECK-LABEL: test_vmodud:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vmodud v2, v2, v342; CHECK-NEXT: blr43entry:44 %rem = urem <2 x i64> %a, %b45 ret <2 x i64> %rem46}47 48define <2 x i64> @test_vmodsd(<2 x i64> %a, <2 x i64> %b) {49; CHECK-LABEL: test_vmodsd:50; CHECK: # %bb.0: # %entry51; CHECK-NEXT: vmodsd v2, v2, v352; CHECK-NEXT: blr53entry:54 %rem = srem <2 x i64> %a, %b55 ret <2 x i64> %rem56}57 58define <4 x i32> @test_vmoduw(<4 x i32> %a, <4 x i32> %b) {59; CHECK-LABEL: test_vmoduw:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vmoduw v2, v2, v362; CHECK-NEXT: blr63entry:64 %rem = urem <4 x i32> %a, %b65 ret <4 x i32> %rem66}67 68define <4 x i32> @test_vmodsw(<4 x i32> %a, <4 x i32> %b) {69; CHECK-LABEL: test_vmodsw:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: vmodsw v2, v2, v372; CHECK-NEXT: blr73entry:74 %rem = srem <4 x i32> %a, %b75 ret <4 x i32> %rem76}77 78define <2 x i64> @test_vmodud_with_div(<2 x i64> %a, <2 x i64> %b) {79; CHECK-LABEL: test_vmodud_with_div:80; CHECK: # %bb.0: # %entry81; CHECK-NEXT: vmodud v4, v2, v382; CHECK-NEXT: vdivud v2, v2, v383; CHECK-NEXT: vaddudm v2, v4, v284; CHECK-NEXT: blr85entry:86 %rem = urem <2 x i64> %a, %b87 %div = udiv <2 x i64> %a, %b88 %add = add <2 x i64> %rem, %div89 ret <2 x i64> %add90}91 92define <2 x i64> @test_vmodsd_with_div(<2 x i64> %a, <2 x i64> %b) {93; CHECK-LABEL: test_vmodsd_with_div:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vmodsd v4, v2, v396; CHECK-NEXT: vdivsd v2, v2, v397; CHECK-NEXT: vaddudm v2, v4, v298; CHECK-NEXT: blr99entry:100 %rem = srem <2 x i64> %a, %b101 %div = sdiv <2 x i64> %a, %b102 %add = add <2 x i64> %rem, %div103 ret <2 x i64> %add104}105 106define <4 x i32> @test_vmoduw_with_div(<4 x i32> %a, <4 x i32> %b) {107; CHECK-LABEL: test_vmoduw_with_div:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vmoduw v4, v2, v3110; CHECK-NEXT: vdivuw v2, v2, v3111; CHECK-NEXT: vadduwm v2, v4, v2112; CHECK-NEXT: blr113entry:114 %rem = urem <4 x i32> %a, %b115 %div = udiv <4 x i32> %a, %b116 %add = add <4 x i32> %rem, %div117 ret <4 x i32> %add118}119 120define <4 x i32> @test_vmodsw_div(<4 x i32> %a, <4 x i32> %b) {121; CHECK-LABEL: test_vmodsw_div:122; CHECK: # %bb.0: # %entry123; CHECK-NEXT: vmodsw v4, v2, v3124; CHECK-NEXT: vdivsw v2, v2, v3125; CHECK-NEXT: vadduwm v2, v4, v2126; CHECK-NEXT: blr127entry:128 %rem = srem <4 x i32> %a, %b129 %div = sdiv <4 x i32> %a, %b130 %add = add <4 x i32> %rem, %div131 ret <4 x i32> %add132}133