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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-LE5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \8; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-BE9 10; This test case aims to test the builtins for vector rotate instructions11; on Power10.12 13 14define <1 x i128> @test_vrlq(<1 x i128> %x, <1 x i128> %y) {15; CHECK-LABEL: test_vrlq:16; CHECK: # %bb.0:17; CHECK-NEXT: vrlq v2, v3, v218; CHECK-NEXT: blr19 %shl.i = shl <1 x i128> %y, %x20 %sub.i = sub <1 x i128> <i128 128>, %x21 %lshr.i = lshr <1 x i128> %y, %sub.i22 %tmp = or <1 x i128> %shl.i, %lshr.i23 ret <1 x i128> %tmp24}25 26define <1 x i128> @test_vrlq_cost_mult8(<1 x i128> %x) {27; CHECK-LE-LABEL: test_vrlq_cost_mult8:28; CHECK-LE: # %bb.0:29; CHECK-LE-NEXT: plxv v3, .LCPI1_0@PCREL(0), 130; CHECK-LE-NEXT: vrlq v2, v3, v231; CHECK-LE-NEXT: blr32;33; CHECK-BE-LABEL: test_vrlq_cost_mult8:34; CHECK-BE: # %bb.0:35; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha36; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l37; CHECK-BE-NEXT: lxv v3, 0(r3)38; CHECK-BE-NEXT: vrlq v2, v3, v239; CHECK-BE-NEXT: blr40 %shl.i = shl <1 x i128> <i128 16>, %x41 %sub.i = sub <1 x i128> <i128 128>, %x42 %lshr.i = lshr <1 x i128> <i128 16>, %sub.i43 %tmp = or <1 x i128> %shl.i, %lshr.i44 ret <1 x i128> %tmp45}46 47define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) {48; CHECK-LE-LABEL: test_vrlq_cost_non_mult8:49; CHECK-LE: # %bb.0:50; CHECK-LE-NEXT: plxv v3, .LCPI2_0@PCREL(0), 151; CHECK-LE-NEXT: vrlq v2, v3, v252; CHECK-LE-NEXT: blr53;54; CHECK-BE-LABEL: test_vrlq_cost_non_mult8:55; CHECK-BE: # %bb.0:56; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha57; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l58; CHECK-BE-NEXT: lxv v3, 0(r3)59; CHECK-BE-NEXT: vrlq v2, v3, v260; CHECK-BE-NEXT: blr61 %shl.i = shl <1 x i128> <i128 4>, %x62 %sub.i = sub <1 x i128> <i128 128>, %x63 %lshr.i = lshr <1 x i128> <i128 4>, %sub.i64 %tmp = or <1 x i128> %shl.i, %lshr.i65 ret <1 x i128> %tmp66}67 68; Function Attrs: nounwind readnone69define <1 x i128> @test_vrlqmi(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {70; CHECK-LABEL: test_vrlqmi:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vrlqmi v3, v2, v473; CHECK-NEXT: vmr v2, v374; CHECK-NEXT: blr75entry:76 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b)77 ret <1 x i128> %tmp78}79 80; Function Attrs: nounwind readnone81define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) {82; CHECK-LE-LABEL: test_vrlqnm:83; CHECK-LE: # %bb.0: # %entry84; CHECK-LE-NEXT: plxv vs0, .LCPI4_0@PCREL(0), 185; CHECK-LE-NEXT: xxperm v3, v4, vs086; CHECK-LE-NEXT: vrlqnm v2, v2, v387; CHECK-LE-NEXT: blr88;89; CHECK-BE-LABEL: test_vrlqnm:90; CHECK-BE: # %bb.0: # %entry91; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha92; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l93; CHECK-BE-NEXT: lxv vs0, 0(r3)94; CHECK-BE-NEXT: xxperm v4, v3, vs095; CHECK-BE-NEXT: vrlqnm v2, v2, v496; CHECK-BE-NEXT: blr97entry:98 %0 = bitcast <1 x i128> %b to <16 x i8>99 %1 = bitcast <1 x i128> %c to <16 x i8>100 %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>101 %d = bitcast <16 x i8> %shuffle.i to <1 x i128>102 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d)103 ret <1 x i128> %tmp104}105 106; Function Attrs: nounwind readnone107declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>)108 109; Function Attrs: nounwind readnone110declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>)111