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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \8; RUN: FileCheck %s9 10; These test cases demonstrate that the vector shift quadword instructions11; introduced within Power10 are correctly exploited.12 13define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {14; CHECK-LABEL: test_vec_vslq:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: xxswapd v3, v317; CHECK-NEXT: vslq v2, v2, v318; CHECK-NEXT: blr19entry:20 %rem = urem <1 x i128> %b, <i128 128>21 %shl = shl <1 x i128> %a, %rem22 ret <1 x i128> %shl23}24 25define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {26; CHECK-LABEL: test_vec_vsrq:27; CHECK: # %bb.0: # %entry28; CHECK-NEXT: xxswapd v3, v329; CHECK-NEXT: vsrq v2, v2, v330; CHECK-NEXT: blr31entry:32 %rem = urem <1 x i128> %b, <i128 128>33 %shr = lshr <1 x i128> %a, %rem34 ret <1 x i128> %shr35}36 37define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {38; CHECK-LABEL: test_vec_vsraq:39; CHECK: # %bb.0: # %entry40; CHECK-NEXT: xxswapd v3, v341; CHECK-NEXT: vsraq v2, v2, v342; CHECK-NEXT: blr43entry:44 %rem = urem <1 x i128> %b, <i128 128>45 %shr = ashr <1 x i128> %a, %rem46 ret <1 x i128> %shr47}48 49define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {50; CHECK-LABEL: test_vec_vslq2:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: xxswapd v3, v353; CHECK-NEXT: vslq v2, v2, v354; CHECK-NEXT: blr55entry:56 %shl = shl <1 x i128> %a, %b57 ret <1 x i128> %shl58}59 60define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {61; CHECK-LABEL: test_vec_vsrq2:62; CHECK: # %bb.0: # %entry63; CHECK-NEXT: xxswapd v3, v364; CHECK-NEXT: vsrq v2, v2, v365; CHECK-NEXT: blr66entry:67 %shr = lshr <1 x i128> %a, %b68 ret <1 x i128> %shr69}70 71define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {72; CHECK-LABEL: test_vec_vsraq2:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: xxswapd v3, v375; CHECK-NEXT: vsraq v2, v2, v376; CHECK-NEXT: blr77entry:78 %shr = ashr <1 x i128> %a, %b79 ret <1 x i128> %shr80}81