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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \7; RUN: FileCheck %s8 9; This test case aims to test vector sign extend builtins.10 11declare <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64>) nounwind readnone12 13define <1 x i128> @test_vextsd2q(<2 x i64> %x) nounwind readnone {14; CHECK-LABEL: test_vextsd2q:15; CHECK: # %bb.0:16; CHECK-NEXT: vextsd2q v2, v217; CHECK-NEXT: blr18 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64> %x)19 ret <1 x i128> %tmp20}21