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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \4; RUN: FileCheck %s5 6; This test case aims to test vector sign extend builtins.7 8declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>) nounwind readnone9declare <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8>) nounwind readnone10declare <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16>) nounwind readnone11declare <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16>) nounwind readnone12declare <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32>) nounwind readnone13 14define <4 x i32> @test_vextsb2w(<16 x i8> %x) nounwind readnone {15; CHECK-LABEL: test_vextsb2w:16; CHECK: # %bb.0:17; CHECK-NEXT: vextsb2w v2, v218; CHECK-NEXT: blr19 %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> %x)20 ret <4 x i32> %tmp21}22 23define <2 x i64> @test_vextsb2d(<16 x i8> %x) nounwind readnone {24; CHECK-LABEL: test_vextsb2d:25; CHECK: # %bb.0:26; CHECK-NEXT: vextsb2d v2, v227; CHECK-NEXT: blr28 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8> %x)29 ret <2 x i64> %tmp30}31 32define <4 x i32> @test_vextsh2w(<8 x i16> %x) nounwind readnone {33; CHECK-LABEL: test_vextsh2w:34; CHECK: # %bb.0:35; CHECK-NEXT: vextsh2w v2, v236; CHECK-NEXT: blr37 %tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16> %x)38 ret <4 x i32> %tmp39}40 41define <2 x i64> @test_vextsh2d(<8 x i16> %x) nounwind readnone {42; CHECK-LABEL: test_vextsh2d:43; CHECK: # %bb.0:44; CHECK-NEXT: vextsh2d v2, v245; CHECK-NEXT: blr46 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16> %x)47 ret <2 x i64> %tmp48}49 50define <2 x i64> @test_vextsw2d(<4 x i32> %x) nounwind readnone {51; CHECK-LABEL: test_vextsw2d:52; CHECK: # %bb.0:53; CHECK-NEXT: vextsw2d v2, v254; CHECK-NEXT: blr55 %tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32> %x)56 ret <2 x i64> %tmp57}58