2536 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-OPT %s4; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,CHECK-O0 %s6; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-OPT8; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-BE,CHECK-BE-O010 11; The following testcases take one halfword element from the second vector and12; inserts it at various locations in the first vector13define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) {14; CHECK-LABEL: shuffle_vector_halfword_0_8:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: vsldoi 3, 3, 3, 817; CHECK-NEXT: vinserth 2, 3, 1418; CHECK-NEXT: blr19;20; CHECK-BE-LABEL: shuffle_vector_halfword_0_8:21; CHECK-BE: # %bb.0: # %entry22; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1023; CHECK-BE-NEXT: vinserth 2, 3, 024; CHECK-BE-NEXT: blr25entry:26 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>27 ret <8 x i16> %vecins28}29 30define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) {31; CHECK-LABEL: shuffle_vector_halfword_1_15:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: vsldoi 3, 3, 3, 1034; CHECK-NEXT: vinserth 2, 3, 1235; CHECK-NEXT: blr36;37; CHECK-BE-LABEL: shuffle_vector_halfword_1_15:38; CHECK-BE: # %bb.0: # %entry39; CHECK-BE-NEXT: vsldoi 3, 3, 3, 840; CHECK-BE-NEXT: vinserth 2, 3, 241; CHECK-BE-NEXT: blr42entry:43 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>44 ret <8 x i16> %vecins45}46 47define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) {48; CHECK-LABEL: shuffle_vector_halfword_2_9:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: vsldoi 3, 3, 3, 651; CHECK-NEXT: vinserth 2, 3, 1052; CHECK-NEXT: blr53;54; CHECK-BE-LABEL: shuffle_vector_halfword_2_9:55; CHECK-BE: # %bb.0: # %entry56; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1257; CHECK-BE-NEXT: vinserth 2, 3, 458; CHECK-BE-NEXT: blr59entry:60 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7>61 ret <8 x i16> %vecins62}63 64define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) {65; CHECK-LABEL: shuffle_vector_halfword_3_13:66; CHECK: # %bb.0: # %entry67; CHECK-NEXT: vsldoi 3, 3, 3, 1468; CHECK-NEXT: vinserth 2, 3, 869; CHECK-NEXT: blr70;71; CHECK-BE-LABEL: shuffle_vector_halfword_3_13:72; CHECK-BE: # %bb.0: # %entry73; CHECK-BE-NEXT: vsldoi 3, 3, 3, 474; CHECK-BE-NEXT: vinserth 2, 3, 675; CHECK-BE-NEXT: blr76entry:77 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7>78 ret <8 x i16> %vecins79}80 81define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) {82; CHECK-LABEL: shuffle_vector_halfword_4_10:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: vsldoi 3, 3, 3, 485; CHECK-NEXT: vinserth 2, 3, 686; CHECK-NEXT: blr87;88; CHECK-BE-LABEL: shuffle_vector_halfword_4_10:89; CHECK-BE: # %bb.0: # %entry90; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1491; CHECK-BE-NEXT: vinserth 2, 3, 892; CHECK-BE-NEXT: blr93entry:94 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7>95 ret <8 x i16> %vecins96}97 98define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) {99; CHECK-LABEL: shuffle_vector_halfword_5_14:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: vsldoi 3, 3, 3, 12102; CHECK-NEXT: vinserth 2, 3, 4103; CHECK-NEXT: blr104;105; CHECK-BE-LABEL: shuffle_vector_halfword_5_14:106; CHECK-BE: # %bb.0: # %entry107; CHECK-BE-NEXT: vsldoi 3, 3, 3, 6108; CHECK-BE-NEXT: vinserth 2, 3, 10109; CHECK-BE-NEXT: blr110entry:111 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7>112 ret <8 x i16> %vecins113}114 115define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) {116; CHECK-LABEL: shuffle_vector_halfword_6_11:117; CHECK: # %bb.0: # %entry118; CHECK-NEXT: vsldoi 3, 3, 3, 2119; CHECK-NEXT: vinserth 2, 3, 2120; CHECK-NEXT: blr121;122; CHECK-BE-LABEL: shuffle_vector_halfword_6_11:123; CHECK-BE: # %bb.0: # %entry124; CHECK-BE-NEXT: vinserth 2, 3, 12125; CHECK-BE-NEXT: blr126entry:127 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7>128 ret <8 x i16> %vecins129}130 131define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) {132; CHECK-LABEL: shuffle_vector_halfword_7_12:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vinserth 2, 3, 0135; CHECK-NEXT: blr136;137; CHECK-BE-LABEL: shuffle_vector_halfword_7_12:138; CHECK-BE: # %bb.0: # %entry139; CHECK-BE-NEXT: vsldoi 3, 3, 3, 2140; CHECK-BE-NEXT: vinserth 2, 3, 14141; CHECK-BE-NEXT: blr142entry:143 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12>144 ret <8 x i16> %vecins145}146 147define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) {148; CHECK-OPT-LABEL: shuffle_vector_halfword_8_1:149; CHECK-OPT: # %bb.0: # %entry150; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 6151; CHECK-OPT-NEXT: vinserth 3, 2, 14152; CHECK-OPT-NEXT: vmr 2, 3153; CHECK-OPT-NEXT: blr154;155; CHECK-O0-LABEL: shuffle_vector_halfword_8_1:156; CHECK-O0: # %bb.0: # %entry157; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill158; CHECK-O0-NEXT: vmr 3, 2159; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload160; CHECK-O0-NEXT: vsldoi 3, 3, 3, 6161; CHECK-O0-NEXT: vinserth 2, 3, 14162; CHECK-O0-NEXT: blr163;164; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_8_1:165; CHECK-BE-OPT: # %bb.0: # %entry166; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 12167; CHECK-BE-OPT-NEXT: vinserth 3, 2, 0168; CHECK-BE-OPT-NEXT: vmr 2, 3169; CHECK-BE-OPT-NEXT: blr170;171; CHECK-BE-O0-LABEL: shuffle_vector_halfword_8_1:172; CHECK-BE-O0: # %bb.0: # %entry173; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill174; CHECK-BE-O0-NEXT: vmr 3, 2175; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload176; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 12177; CHECK-BE-O0-NEXT: vinserth 2, 3, 0178; CHECK-BE-O0-NEXT: blr179entry:180 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>181 ret <8 x i16> %vecins182}183 184; The following testcases take one halfword element from the first vector and185; inserts it at various locations in the second vector186define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) {187; CHECK-OPT-LABEL: shuffle_vector_halfword_9_7:188; CHECK-OPT: # %bb.0: # %entry189; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 10190; CHECK-OPT-NEXT: vinserth 3, 2, 12191; CHECK-OPT-NEXT: vmr 2, 3192; CHECK-OPT-NEXT: blr193;194; CHECK-O0-LABEL: shuffle_vector_halfword_9_7:195; CHECK-O0: # %bb.0: # %entry196; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill197; CHECK-O0-NEXT: vmr 3, 2198; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload199; CHECK-O0-NEXT: vsldoi 3, 3, 3, 10200; CHECK-O0-NEXT: vinserth 2, 3, 12201; CHECK-O0-NEXT: blr202;203; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_9_7:204; CHECK-BE-OPT: # %bb.0: # %entry205; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 8206; CHECK-BE-OPT-NEXT: vinserth 3, 2, 2207; CHECK-BE-OPT-NEXT: vmr 2, 3208; CHECK-BE-OPT-NEXT: blr209;210; CHECK-BE-O0-LABEL: shuffle_vector_halfword_9_7:211; CHECK-BE-O0: # %bb.0: # %entry212; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill213; CHECK-BE-O0-NEXT: vmr 3, 2214; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload215; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 8216; CHECK-BE-O0-NEXT: vinserth 2, 3, 2217; CHECK-BE-O0-NEXT: blr218entry:219 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>220 ret <8 x i16> %vecins221}222 223define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) {224; CHECK-OPT-LABEL: shuffle_vector_halfword_10_4:225; CHECK-OPT: # %bb.0: # %entry226; CHECK-OPT-NEXT: vinserth 3, 2, 10227; CHECK-OPT-NEXT: vmr 2, 3228; CHECK-OPT-NEXT: blr229;230; CHECK-O0-LABEL: shuffle_vector_halfword_10_4:231; CHECK-O0: # %bb.0: # %entry232; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill233; CHECK-O0-NEXT: vmr 3, 2234; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload235; CHECK-O0-NEXT: vinserth 2, 3, 10236; CHECK-O0-NEXT: blr237;238; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_10_4:239; CHECK-BE-OPT: # %bb.0: # %entry240; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 2241; CHECK-BE-OPT-NEXT: vinserth 3, 2, 4242; CHECK-BE-OPT-NEXT: vmr 2, 3243; CHECK-BE-OPT-NEXT: blr244;245; CHECK-BE-O0-LABEL: shuffle_vector_halfword_10_4:246; CHECK-BE-O0: # %bb.0: # %entry247; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill248; CHECK-BE-O0-NEXT: vmr 3, 2249; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload250; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 2251; CHECK-BE-O0-NEXT: vinserth 2, 3, 4252; CHECK-BE-O0-NEXT: blr253entry:254 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15>255 ret <8 x i16> %vecins256}257 258define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) {259; CHECK-OPT-LABEL: shuffle_vector_halfword_11_2:260; CHECK-OPT: # %bb.0: # %entry261; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 4262; CHECK-OPT-NEXT: vinserth 3, 2, 8263; CHECK-OPT-NEXT: vmr 2, 3264; CHECK-OPT-NEXT: blr265;266; CHECK-O0-LABEL: shuffle_vector_halfword_11_2:267; CHECK-O0: # %bb.0: # %entry268; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill269; CHECK-O0-NEXT: vmr 3, 2270; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload271; CHECK-O0-NEXT: vsldoi 3, 3, 3, 4272; CHECK-O0-NEXT: vinserth 2, 3, 8273; CHECK-O0-NEXT: blr274;275; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_11_2:276; CHECK-BE-OPT: # %bb.0: # %entry277; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 14278; CHECK-BE-OPT-NEXT: vinserth 3, 2, 6279; CHECK-BE-OPT-NEXT: vmr 2, 3280; CHECK-BE-OPT-NEXT: blr281;282; CHECK-BE-O0-LABEL: shuffle_vector_halfword_11_2:283; CHECK-BE-O0: # %bb.0: # %entry284; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill285; CHECK-BE-O0-NEXT: vmr 3, 2286; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload287; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 14288; CHECK-BE-O0-NEXT: vinserth 2, 3, 6289; CHECK-BE-O0-NEXT: blr290entry:291 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15>292 ret <8 x i16> %vecins293}294 295define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) {296; CHECK-OPT-LABEL: shuffle_vector_halfword_12_6:297; CHECK-OPT: # %bb.0: # %entry298; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 12299; CHECK-OPT-NEXT: vinserth 3, 2, 6300; CHECK-OPT-NEXT: vmr 2, 3301; CHECK-OPT-NEXT: blr302;303; CHECK-O0-LABEL: shuffle_vector_halfword_12_6:304; CHECK-O0: # %bb.0: # %entry305; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill306; CHECK-O0-NEXT: vmr 3, 2307; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload308; CHECK-O0-NEXT: vsldoi 3, 3, 3, 12309; CHECK-O0-NEXT: vinserth 2, 3, 6310; CHECK-O0-NEXT: blr311;312; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_12_6:313; CHECK-BE-OPT: # %bb.0: # %entry314; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 6315; CHECK-BE-OPT-NEXT: vinserth 3, 2, 8316; CHECK-BE-OPT-NEXT: vmr 2, 3317; CHECK-BE-OPT-NEXT: blr318;319; CHECK-BE-O0-LABEL: shuffle_vector_halfword_12_6:320; CHECK-BE-O0: # %bb.0: # %entry321; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill322; CHECK-BE-O0-NEXT: vmr 3, 2323; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload324; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 6325; CHECK-BE-O0-NEXT: vinserth 2, 3, 8326; CHECK-BE-O0-NEXT: blr327entry:328 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15>329 ret <8 x i16> %vecins330}331 332define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) {333; CHECK-OPT-LABEL: shuffle_vector_halfword_13_3:334; CHECK-OPT: # %bb.0: # %entry335; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 2336; CHECK-OPT-NEXT: vinserth 3, 2, 4337; CHECK-OPT-NEXT: vmr 2, 3338; CHECK-OPT-NEXT: blr339;340; CHECK-O0-LABEL: shuffle_vector_halfword_13_3:341; CHECK-O0: # %bb.0: # %entry342; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill343; CHECK-O0-NEXT: vmr 3, 2344; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload345; CHECK-O0-NEXT: vsldoi 3, 3, 3, 2346; CHECK-O0-NEXT: vinserth 2, 3, 4347; CHECK-O0-NEXT: blr348;349; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_13_3:350; CHECK-BE-OPT: # %bb.0: # %entry351; CHECK-BE-OPT-NEXT: vinserth 3, 2, 10352; CHECK-BE-OPT-NEXT: vmr 2, 3353; CHECK-BE-OPT-NEXT: blr354;355; CHECK-BE-O0-LABEL: shuffle_vector_halfword_13_3:356; CHECK-BE-O0: # %bb.0: # %entry357; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill358; CHECK-BE-O0-NEXT: vmr 3, 2359; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload360; CHECK-BE-O0-NEXT: vinserth 2, 3, 10361; CHECK-BE-O0-NEXT: blr362entry:363 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15>364 ret <8 x i16> %vecins365}366 367define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) {368; CHECK-OPT-LABEL: shuffle_vector_halfword_14_5:369; CHECK-OPT: # %bb.0: # %entry370; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 14371; CHECK-OPT-NEXT: vinserth 3, 2, 2372; CHECK-OPT-NEXT: vmr 2, 3373; CHECK-OPT-NEXT: blr374;375; CHECK-O0-LABEL: shuffle_vector_halfword_14_5:376; CHECK-O0: # %bb.0: # %entry377; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill378; CHECK-O0-NEXT: vmr 3, 2379; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload380; CHECK-O0-NEXT: vsldoi 3, 3, 3, 14381; CHECK-O0-NEXT: vinserth 2, 3, 2382; CHECK-O0-NEXT: blr383;384; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_14_5:385; CHECK-BE-OPT: # %bb.0: # %entry386; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 4387; CHECK-BE-OPT-NEXT: vinserth 3, 2, 12388; CHECK-BE-OPT-NEXT: vmr 2, 3389; CHECK-BE-OPT-NEXT: blr390;391; CHECK-BE-O0-LABEL: shuffle_vector_halfword_14_5:392; CHECK-BE-O0: # %bb.0: # %entry393; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill394; CHECK-BE-O0-NEXT: vmr 3, 2395; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload396; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 4397; CHECK-BE-O0-NEXT: vinserth 2, 3, 12398; CHECK-BE-O0-NEXT: blr399entry:400 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15>401 ret <8 x i16> %vecins402}403 404define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) {405; CHECK-OPT-LABEL: shuffle_vector_halfword_15_0:406; CHECK-OPT: # %bb.0: # %entry407; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 8408; CHECK-OPT-NEXT: vinserth 3, 2, 0409; CHECK-OPT-NEXT: vmr 2, 3410; CHECK-OPT-NEXT: blr411;412; CHECK-O0-LABEL: shuffle_vector_halfword_15_0:413; CHECK-O0: # %bb.0: # %entry414; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill415; CHECK-O0-NEXT: vmr 3, 2416; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload417; CHECK-O0-NEXT: vsldoi 3, 3, 3, 8418; CHECK-O0-NEXT: vinserth 2, 3, 0419; CHECK-O0-NEXT: blr420;421; CHECK-BE-OPT-LABEL: shuffle_vector_halfword_15_0:422; CHECK-BE-OPT: # %bb.0: # %entry423; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 10424; CHECK-BE-OPT-NEXT: vinserth 3, 2, 14425; CHECK-BE-OPT-NEXT: vmr 2, 3426; CHECK-BE-OPT-NEXT: blr427;428; CHECK-BE-O0-LABEL: shuffle_vector_halfword_15_0:429; CHECK-BE-O0: # %bb.0: # %entry430; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill431; CHECK-BE-O0-NEXT: vmr 3, 2432; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload433; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 10434; CHECK-BE-O0-NEXT: vinserth 2, 3, 14435; CHECK-BE-O0-NEXT: blr436entry:437 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>438 ret <8 x i16> %vecins439}440 441; The following testcases use the same vector in both arguments of the442; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one443; we're attempting to insert, then we can use the vector insert instruction444define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) {445; CHECK-LABEL: shuffle_vector_halfword_0_4:446; CHECK: # %bb.0: # %entry447; CHECK-NEXT: vinserth 2, 2, 14448; CHECK-NEXT: blr449;450; CHECK-BE-LABEL: shuffle_vector_halfword_0_4:451; CHECK-BE: # %bb.0: # %entry452; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha453; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l454; CHECK-BE-NEXT: lxv 0, 0(3)455; CHECK-BE-NEXT: xxperm 34, 34, 0456; CHECK-BE-NEXT: blr457entry:458 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>459 ret <8 x i16> %vecins460}461 462define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) {463; CHECK-LABEL: shuffle_vector_halfword_1_3:464; CHECK: # %bb.0: # %entry465; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha466; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l467; CHECK-NEXT: lxv 0, 0(3)468; CHECK-NEXT: xxperm 34, 34, 0469; CHECK-NEXT: blr470;471; CHECK-BE-LABEL: shuffle_vector_halfword_1_3:472; CHECK-BE: # %bb.0: # %entry473; CHECK-BE-NEXT: vinserth 2, 2, 2474; CHECK-BE-NEXT: blr475entry:476 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>477 ret <8 x i16> %vecins478}479 480define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) {481; CHECK-LABEL: shuffle_vector_halfword_2_3:482; CHECK: # %bb.0: # %entry483; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha484; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l485; CHECK-NEXT: lxv 0, 0(3)486; CHECK-NEXT: xxperm 34, 34, 0487; CHECK-NEXT: blr488;489; CHECK-BE-LABEL: shuffle_vector_halfword_2_3:490; CHECK-BE: # %bb.0: # %entry491; CHECK-BE-NEXT: vinserth 2, 2, 4492; CHECK-BE-NEXT: blr493entry:494 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7>495 ret <8 x i16> %vecins496}497 498define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) {499; CHECK-LABEL: shuffle_vector_halfword_3_4:500; CHECK: # %bb.0: # %entry501; CHECK-NEXT: vinserth 2, 2, 8502; CHECK-NEXT: blr503;504; CHECK-BE-LABEL: shuffle_vector_halfword_3_4:505; CHECK-BE: # %bb.0: # %entry506; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha507; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l508; CHECK-BE-NEXT: lxv 0, 0(3)509; CHECK-BE-NEXT: xxperm 34, 34, 0510; CHECK-BE-NEXT: blr511entry:512 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7>513 ret <8 x i16> %vecins514}515 516define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) {517; CHECK-LABEL: shuffle_vector_halfword_4_3:518; CHECK: # %bb.0: # %entry519; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha520; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l521; CHECK-NEXT: lxv 0, 0(3)522; CHECK-NEXT: xxperm 34, 34, 0523; CHECK-NEXT: blr524;525; CHECK-BE-LABEL: shuffle_vector_halfword_4_3:526; CHECK-BE: # %bb.0: # %entry527; CHECK-BE-NEXT: vinserth 2, 2, 8528; CHECK-BE-NEXT: blr529entry:530 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7>531 ret <8 x i16> %vecins532}533 534define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) {535; CHECK-LABEL: shuffle_vector_halfword_5_3:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha538; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l539; CHECK-NEXT: lxv 0, 0(3)540; CHECK-NEXT: xxperm 34, 34, 0541; CHECK-NEXT: blr542;543; CHECK-BE-LABEL: shuffle_vector_halfword_5_3:544; CHECK-BE: # %bb.0: # %entry545; CHECK-BE-NEXT: vinserth 2, 2, 10546; CHECK-BE-NEXT: blr547entry:548 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7>549 ret <8 x i16> %vecins550}551 552define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) {553; CHECK-LABEL: shuffle_vector_halfword_6_4:554; CHECK: # %bb.0: # %entry555; CHECK-NEXT: vinserth 2, 2, 2556; CHECK-NEXT: blr557;558; CHECK-BE-LABEL: shuffle_vector_halfword_6_4:559; CHECK-BE: # %bb.0: # %entry560; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha561; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l562; CHECK-BE-NEXT: lxv 0, 0(3)563; CHECK-BE-NEXT: xxperm 34, 34, 0564; CHECK-BE-NEXT: blr565entry:566 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7>567 ret <8 x i16> %vecins568}569 570define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) {571; CHECK-LABEL: shuffle_vector_halfword_7_4:572; CHECK: # %bb.0: # %entry573; CHECK-NEXT: vinserth 2, 2, 0574; CHECK-NEXT: blr575;576; CHECK-BE-LABEL: shuffle_vector_halfword_7_4:577; CHECK-BE: # %bb.0: # %entry578; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha579; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l580; CHECK-BE-NEXT: lxv 0, 0(3)581; CHECK-BE-NEXT: xxperm 34, 34, 0582; CHECK-BE-NEXT: blr583entry:584 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4>585 ret <8 x i16> %vecins586}587 588; The following testcases take one byte element from the second vector and589; inserts it at various locations in the first vector590define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) {591; CHECK-LABEL: shuffle_vector_byte_0_16:592; CHECK: # %bb.0: # %entry593; CHECK-NEXT: vsldoi 3, 3, 3, 8594; CHECK-NEXT: vinsertb 2, 3, 15595; CHECK-NEXT: blr596;597; CHECK-BE-LABEL: shuffle_vector_byte_0_16:598; CHECK-BE: # %bb.0: # %entry599; CHECK-BE-NEXT: vsldoi 3, 3, 3, 9600; CHECK-BE-NEXT: vinsertb 2, 3, 0601; CHECK-BE-NEXT: blr602entry:603 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>604 ret <16 x i8> %vecins605}606 607define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) {608; CHECK-LABEL: shuffle_vector_byte_1_25:609; CHECK: # %bb.0: # %entry610; CHECK-NEXT: vsldoi 3, 3, 3, 15611; CHECK-NEXT: vinsertb 2, 3, 14612; CHECK-NEXT: blr613;614; CHECK-BE-LABEL: shuffle_vector_byte_1_25:615; CHECK-BE: # %bb.0: # %entry616; CHECK-BE-NEXT: vsldoi 3, 3, 3, 2617; CHECK-BE-NEXT: vinsertb 2, 3, 1618; CHECK-BE-NEXT: blr619entry:620 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>621 ret <16 x i8> %vecins622}623 624define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) {625; CHECK-LABEL: shuffle_vector_byte_2_18:626; CHECK: # %bb.0: # %entry627; CHECK-NEXT: vsldoi 3, 3, 3, 6628; CHECK-NEXT: vinsertb 2, 3, 13629; CHECK-NEXT: blr630;631; CHECK-BE-LABEL: shuffle_vector_byte_2_18:632; CHECK-BE: # %bb.0: # %entry633; CHECK-BE-NEXT: vsldoi 3, 3, 3, 11634; CHECK-BE-NEXT: vinsertb 2, 3, 2635; CHECK-BE-NEXT: blr636entry:637 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>638 ret <16 x i8> %vecins639}640 641define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) {642; CHECK-LABEL: shuffle_vector_byte_3_27:643; CHECK: # %bb.0: # %entry644; CHECK-NEXT: vsldoi 3, 3, 3, 13645; CHECK-NEXT: vinsertb 2, 3, 12646; CHECK-NEXT: blr647;648; CHECK-BE-LABEL: shuffle_vector_byte_3_27:649; CHECK-BE: # %bb.0: # %entry650; CHECK-BE-NEXT: vsldoi 3, 3, 3, 4651; CHECK-BE-NEXT: vinsertb 2, 3, 3652; CHECK-BE-NEXT: blr653entry:654 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>655 ret <16 x i8> %vecins656}657 658define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) {659; CHECK-LABEL: shuffle_vector_byte_4_20:660; CHECK: # %bb.0: # %entry661; CHECK-NEXT: vsldoi 3, 3, 3, 4662; CHECK-NEXT: vinsertb 2, 3, 11663; CHECK-NEXT: blr664;665; CHECK-BE-LABEL: shuffle_vector_byte_4_20:666; CHECK-BE: # %bb.0: # %entry667; CHECK-BE-NEXT: vsldoi 3, 3, 3, 13668; CHECK-BE-NEXT: vinsertb 2, 3, 4669; CHECK-BE-NEXT: blr670entry:671 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>672 ret <16 x i8> %vecins673}674 675define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) {676; CHECK-LABEL: shuffle_vector_byte_5_29:677; CHECK: # %bb.0: # %entry678; CHECK-NEXT: vsldoi 3, 3, 3, 11679; CHECK-NEXT: vinsertb 2, 3, 10680; CHECK-NEXT: blr681;682; CHECK-BE-LABEL: shuffle_vector_byte_5_29:683; CHECK-BE: # %bb.0: # %entry684; CHECK-BE-NEXT: vsldoi 3, 3, 3, 6685; CHECK-BE-NEXT: vinsertb 2, 3, 5686; CHECK-BE-NEXT: blr687entry:688 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>689 ret <16 x i8> %vecins690}691 692define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) {693; CHECK-LABEL: shuffle_vector_byte_6_22:694; CHECK: # %bb.0: # %entry695; CHECK-NEXT: vsldoi 3, 3, 3, 2696; CHECK-NEXT: vinsertb 2, 3, 9697; CHECK-NEXT: blr698;699; CHECK-BE-LABEL: shuffle_vector_byte_6_22:700; CHECK-BE: # %bb.0: # %entry701; CHECK-BE-NEXT: vsldoi 3, 3, 3, 15702; CHECK-BE-NEXT: vinsertb 2, 3, 6703; CHECK-BE-NEXT: blr704entry:705 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>706 ret <16 x i8> %vecins707}708 709define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) {710; CHECK-LABEL: shuffle_vector_byte_7_31:711; CHECK: # %bb.0: # %entry712; CHECK-NEXT: vsldoi 3, 3, 3, 9713; CHECK-NEXT: vinsertb 2, 3, 8714; CHECK-NEXT: blr715;716; CHECK-BE-LABEL: shuffle_vector_byte_7_31:717; CHECK-BE: # %bb.0: # %entry718; CHECK-BE-NEXT: vsldoi 3, 3, 3, 8719; CHECK-BE-NEXT: vinsertb 2, 3, 7720; CHECK-BE-NEXT: blr721entry:722 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>723 ret <16 x i8> %vecins724}725 726define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) {727; CHECK-LABEL: shuffle_vector_byte_8_24:728; CHECK: # %bb.0: # %entry729; CHECK-NEXT: vinsertb 2, 3, 7730; CHECK-NEXT: blr731;732; CHECK-BE-LABEL: shuffle_vector_byte_8_24:733; CHECK-BE: # %bb.0: # %entry734; CHECK-BE-NEXT: vsldoi 3, 3, 3, 1735; CHECK-BE-NEXT: vinsertb 2, 3, 8736; CHECK-BE-NEXT: blr737entry:738 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>739 ret <16 x i8> %vecins740}741 742define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) {743; CHECK-LABEL: shuffle_vector_byte_9_17:744; CHECK: # %bb.0: # %entry745; CHECK-NEXT: vsldoi 3, 3, 3, 7746; CHECK-NEXT: vinsertb 2, 3, 6747; CHECK-NEXT: blr748;749; CHECK-BE-LABEL: shuffle_vector_byte_9_17:750; CHECK-BE: # %bb.0: # %entry751; CHECK-BE-NEXT: vsldoi 3, 3, 3, 10752; CHECK-BE-NEXT: vinsertb 2, 3, 9753; CHECK-BE-NEXT: blr754entry:755 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>756 ret <16 x i8> %vecins757}758 759define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) {760; CHECK-LABEL: shuffle_vector_byte_10_26:761; CHECK: # %bb.0: # %entry762; CHECK-NEXT: vsldoi 3, 3, 3, 14763; CHECK-NEXT: vinsertb 2, 3, 5764; CHECK-NEXT: blr765;766; CHECK-BE-LABEL: shuffle_vector_byte_10_26:767; CHECK-BE: # %bb.0: # %entry768; CHECK-BE-NEXT: vsldoi 3, 3, 3, 3769; CHECK-BE-NEXT: vinsertb 2, 3, 10770; CHECK-BE-NEXT: blr771entry:772 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15>773 ret <16 x i8> %vecins774}775 776define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) {777; CHECK-LABEL: shuffle_vector_byte_11_19:778; CHECK: # %bb.0: # %entry779; CHECK-NEXT: vsldoi 3, 3, 3, 5780; CHECK-NEXT: vinsertb 2, 3, 4781; CHECK-NEXT: blr782;783; CHECK-BE-LABEL: shuffle_vector_byte_11_19:784; CHECK-BE: # %bb.0: # %entry785; CHECK-BE-NEXT: vsldoi 3, 3, 3, 12786; CHECK-BE-NEXT: vinsertb 2, 3, 11787; CHECK-BE-NEXT: blr788entry:789 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15>790 ret <16 x i8> %vecins791}792 793define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) {794; CHECK-LABEL: shuffle_vector_byte_12_28:795; CHECK: # %bb.0: # %entry796; CHECK-NEXT: vsldoi 3, 3, 3, 12797; CHECK-NEXT: vinsertb 2, 3, 3798; CHECK-NEXT: blr799;800; CHECK-BE-LABEL: shuffle_vector_byte_12_28:801; CHECK-BE: # %bb.0: # %entry802; CHECK-BE-NEXT: vsldoi 3, 3, 3, 5803; CHECK-BE-NEXT: vinsertb 2, 3, 12804; CHECK-BE-NEXT: blr805entry:806 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15>807 ret <16 x i8> %vecins808}809 810define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) {811; CHECK-LABEL: shuffle_vector_byte_13_21:812; CHECK: # %bb.0: # %entry813; CHECK-NEXT: vsldoi 3, 3, 3, 3814; CHECK-NEXT: vinsertb 2, 3, 2815; CHECK-NEXT: blr816;817; CHECK-BE-LABEL: shuffle_vector_byte_13_21:818; CHECK-BE: # %bb.0: # %entry819; CHECK-BE-NEXT: vsldoi 3, 3, 3, 14820; CHECK-BE-NEXT: vinsertb 2, 3, 13821; CHECK-BE-NEXT: blr822entry:823 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15>824 ret <16 x i8> %vecins825}826 827define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) {828; CHECK-LABEL: shuffle_vector_byte_14_30:829; CHECK: # %bb.0: # %entry830; CHECK-NEXT: vsldoi 3, 3, 3, 10831; CHECK-NEXT: vinsertb 2, 3, 1832; CHECK-NEXT: blr833;834; CHECK-BE-LABEL: shuffle_vector_byte_14_30:835; CHECK-BE: # %bb.0: # %entry836; CHECK-BE-NEXT: vsldoi 3, 3, 3, 7837; CHECK-BE-NEXT: vinsertb 2, 3, 14838; CHECK-BE-NEXT: blr839entry:840 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15>841 ret <16 x i8> %vecins842}843 844define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) {845; CHECK-LABEL: shuffle_vector_byte_15_23:846; CHECK: # %bb.0: # %entry847; CHECK-NEXT: vsldoi 3, 3, 3, 1848; CHECK-NEXT: vinsertb 2, 3, 0849; CHECK-NEXT: blr850;851; CHECK-BE-LABEL: shuffle_vector_byte_15_23:852; CHECK-BE: # %bb.0: # %entry853; CHECK-BE-NEXT: vinsertb 2, 3, 15854; CHECK-BE-NEXT: blr855entry:856 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23>857 ret <16 x i8> %vecins858}859 860; The following testcases take one byte element from the first vector and861; inserts it at various locations in the second vector862define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) {863; CHECK-OPT-LABEL: shuffle_vector_byte_16_8:864; CHECK-OPT: # %bb.0: # %entry865; CHECK-OPT-NEXT: vinsertb 3, 2, 15866; CHECK-OPT-NEXT: vmr 2, 3867; CHECK-OPT-NEXT: blr868;869; CHECK-O0-LABEL: shuffle_vector_byte_16_8:870; CHECK-O0: # %bb.0: # %entry871; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill872; CHECK-O0-NEXT: vmr 3, 2873; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload874; CHECK-O0-NEXT: vinsertb 2, 3, 15875; CHECK-O0-NEXT: blr876;877; CHECK-BE-OPT-LABEL: shuffle_vector_byte_16_8:878; CHECK-BE-OPT: # %bb.0: # %entry879; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 1880; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 0881; CHECK-BE-OPT-NEXT: vmr 2, 3882; CHECK-BE-OPT-NEXT: blr883;884; CHECK-BE-O0-LABEL: shuffle_vector_byte_16_8:885; CHECK-BE-O0: # %bb.0: # %entry886; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill887; CHECK-BE-O0-NEXT: vmr 3, 2888; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload889; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 1890; CHECK-BE-O0-NEXT: vinsertb 2, 3, 0891; CHECK-BE-O0-NEXT: blr892entry:893 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>894 ret <16 x i8> %vecins895}896 897define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) {898; CHECK-OPT-LABEL: shuffle_vector_byte_17_1:899; CHECK-OPT: # %bb.0: # %entry900; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 7901; CHECK-OPT-NEXT: vinsertb 3, 2, 14902; CHECK-OPT-NEXT: vmr 2, 3903; CHECK-OPT-NEXT: blr904;905; CHECK-O0-LABEL: shuffle_vector_byte_17_1:906; CHECK-O0: # %bb.0: # %entry907; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill908; CHECK-O0-NEXT: vmr 3, 2909; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload910; CHECK-O0-NEXT: vsldoi 3, 3, 3, 7911; CHECK-O0-NEXT: vinsertb 2, 3, 14912; CHECK-O0-NEXT: blr913;914; CHECK-BE-OPT-LABEL: shuffle_vector_byte_17_1:915; CHECK-BE-OPT: # %bb.0: # %entry916; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 10917; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 1918; CHECK-BE-OPT-NEXT: vmr 2, 3919; CHECK-BE-OPT-NEXT: blr920;921; CHECK-BE-O0-LABEL: shuffle_vector_byte_17_1:922; CHECK-BE-O0: # %bb.0: # %entry923; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill924; CHECK-BE-O0-NEXT: vmr 3, 2925; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload926; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 10927; CHECK-BE-O0-NEXT: vinsertb 2, 3, 1928; CHECK-BE-O0-NEXT: blr929entry:930 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>931 ret <16 x i8> %vecins932}933 934define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) {935; CHECK-OPT-LABEL: shuffle_vector_byte_18_10:936; CHECK-OPT: # %bb.0: # %entry937; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 14938; CHECK-OPT-NEXT: vinsertb 3, 2, 13939; CHECK-OPT-NEXT: vmr 2, 3940; CHECK-OPT-NEXT: blr941;942; CHECK-O0-LABEL: shuffle_vector_byte_18_10:943; CHECK-O0: # %bb.0: # %entry944; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill945; CHECK-O0-NEXT: vmr 3, 2946; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload947; CHECK-O0-NEXT: vsldoi 3, 3, 3, 14948; CHECK-O0-NEXT: vinsertb 2, 3, 13949; CHECK-O0-NEXT: blr950;951; CHECK-BE-OPT-LABEL: shuffle_vector_byte_18_10:952; CHECK-BE-OPT: # %bb.0: # %entry953; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 3954; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 2955; CHECK-BE-OPT-NEXT: vmr 2, 3956; CHECK-BE-OPT-NEXT: blr957;958; CHECK-BE-O0-LABEL: shuffle_vector_byte_18_10:959; CHECK-BE-O0: # %bb.0: # %entry960; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill961; CHECK-BE-O0-NEXT: vmr 3, 2962; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload963; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 3964; CHECK-BE-O0-NEXT: vinsertb 2, 3, 2965; CHECK-BE-O0-NEXT: blr966entry:967 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>968 ret <16 x i8> %vecins969}970 971define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) {972; CHECK-OPT-LABEL: shuffle_vector_byte_19_3:973; CHECK-OPT: # %bb.0: # %entry974; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 5975; CHECK-OPT-NEXT: vinsertb 3, 2, 12976; CHECK-OPT-NEXT: vmr 2, 3977; CHECK-OPT-NEXT: blr978;979; CHECK-O0-LABEL: shuffle_vector_byte_19_3:980; CHECK-O0: # %bb.0: # %entry981; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill982; CHECK-O0-NEXT: vmr 3, 2983; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload984; CHECK-O0-NEXT: vsldoi 3, 3, 3, 5985; CHECK-O0-NEXT: vinsertb 2, 3, 12986; CHECK-O0-NEXT: blr987;988; CHECK-BE-OPT-LABEL: shuffle_vector_byte_19_3:989; CHECK-BE-OPT: # %bb.0: # %entry990; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 12991; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 3992; CHECK-BE-OPT-NEXT: vmr 2, 3993; CHECK-BE-OPT-NEXT: blr994;995; CHECK-BE-O0-LABEL: shuffle_vector_byte_19_3:996; CHECK-BE-O0: # %bb.0: # %entry997; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill998; CHECK-BE-O0-NEXT: vmr 3, 2999; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1000; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 121001; CHECK-BE-O0-NEXT: vinsertb 2, 3, 31002; CHECK-BE-O0-NEXT: blr1003entry:1004 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1005 ret <16 x i8> %vecins1006}1007 1008define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) {1009; CHECK-OPT-LABEL: shuffle_vector_byte_20_12:1010; CHECK-OPT: # %bb.0: # %entry1011; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 121012; CHECK-OPT-NEXT: vinsertb 3, 2, 111013; CHECK-OPT-NEXT: vmr 2, 31014; CHECK-OPT-NEXT: blr1015;1016; CHECK-O0-LABEL: shuffle_vector_byte_20_12:1017; CHECK-O0: # %bb.0: # %entry1018; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1019; CHECK-O0-NEXT: vmr 3, 21020; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1021; CHECK-O0-NEXT: vsldoi 3, 3, 3, 121022; CHECK-O0-NEXT: vinsertb 2, 3, 111023; CHECK-O0-NEXT: blr1024;1025; CHECK-BE-OPT-LABEL: shuffle_vector_byte_20_12:1026; CHECK-BE-OPT: # %bb.0: # %entry1027; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 51028; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 41029; CHECK-BE-OPT-NEXT: vmr 2, 31030; CHECK-BE-OPT-NEXT: blr1031;1032; CHECK-BE-O0-LABEL: shuffle_vector_byte_20_12:1033; CHECK-BE-O0: # %bb.0: # %entry1034; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1035; CHECK-BE-O0-NEXT: vmr 3, 21036; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1037; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 51038; CHECK-BE-O0-NEXT: vinsertb 2, 3, 41039; CHECK-BE-O0-NEXT: blr1040entry:1041 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1042 ret <16 x i8> %vecins1043}1044 1045define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) {1046; CHECK-OPT-LABEL: shuffle_vector_byte_21_5:1047; CHECK-OPT: # %bb.0: # %entry1048; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 31049; CHECK-OPT-NEXT: vinsertb 3, 2, 101050; CHECK-OPT-NEXT: vmr 2, 31051; CHECK-OPT-NEXT: blr1052;1053; CHECK-O0-LABEL: shuffle_vector_byte_21_5:1054; CHECK-O0: # %bb.0: # %entry1055; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1056; CHECK-O0-NEXT: vmr 3, 21057; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1058; CHECK-O0-NEXT: vsldoi 3, 3, 3, 31059; CHECK-O0-NEXT: vinsertb 2, 3, 101060; CHECK-O0-NEXT: blr1061;1062; CHECK-BE-OPT-LABEL: shuffle_vector_byte_21_5:1063; CHECK-BE-OPT: # %bb.0: # %entry1064; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 141065; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 51066; CHECK-BE-OPT-NEXT: vmr 2, 31067; CHECK-BE-OPT-NEXT: blr1068;1069; CHECK-BE-O0-LABEL: shuffle_vector_byte_21_5:1070; CHECK-BE-O0: # %bb.0: # %entry1071; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1072; CHECK-BE-O0-NEXT: vmr 3, 21073; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1074; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 141075; CHECK-BE-O0-NEXT: vinsertb 2, 3, 51076; CHECK-BE-O0-NEXT: blr1077entry:1078 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1079 ret <16 x i8> %vecins1080}1081 1082define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) {1083; CHECK-OPT-LABEL: shuffle_vector_byte_22_14:1084; CHECK-OPT: # %bb.0: # %entry1085; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 101086; CHECK-OPT-NEXT: vinsertb 3, 2, 91087; CHECK-OPT-NEXT: vmr 2, 31088; CHECK-OPT-NEXT: blr1089;1090; CHECK-O0-LABEL: shuffle_vector_byte_22_14:1091; CHECK-O0: # %bb.0: # %entry1092; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1093; CHECK-O0-NEXT: vmr 3, 21094; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1095; CHECK-O0-NEXT: vsldoi 3, 3, 3, 101096; CHECK-O0-NEXT: vinsertb 2, 3, 91097; CHECK-O0-NEXT: blr1098;1099; CHECK-BE-OPT-LABEL: shuffle_vector_byte_22_14:1100; CHECK-BE-OPT: # %bb.0: # %entry1101; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 71102; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 61103; CHECK-BE-OPT-NEXT: vmr 2, 31104; CHECK-BE-OPT-NEXT: blr1105;1106; CHECK-BE-O0-LABEL: shuffle_vector_byte_22_14:1107; CHECK-BE-O0: # %bb.0: # %entry1108; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1109; CHECK-BE-O0-NEXT: vmr 3, 21110; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1111; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 71112; CHECK-BE-O0-NEXT: vinsertb 2, 3, 61113; CHECK-BE-O0-NEXT: blr1114entry:1115 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1116 ret <16 x i8> %vecins1117}1118 1119define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) {1120; CHECK-OPT-LABEL: shuffle_vector_byte_23_7:1121; CHECK-OPT: # %bb.0: # %entry1122; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 11123; CHECK-OPT-NEXT: vinsertb 3, 2, 81124; CHECK-OPT-NEXT: vmr 2, 31125; CHECK-OPT-NEXT: blr1126;1127; CHECK-O0-LABEL: shuffle_vector_byte_23_7:1128; CHECK-O0: # %bb.0: # %entry1129; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1130; CHECK-O0-NEXT: vmr 3, 21131; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1132; CHECK-O0-NEXT: vsldoi 3, 3, 3, 11133; CHECK-O0-NEXT: vinsertb 2, 3, 81134; CHECK-O0-NEXT: blr1135;1136; CHECK-BE-OPT-LABEL: shuffle_vector_byte_23_7:1137; CHECK-BE-OPT: # %bb.0: # %entry1138; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 71139; CHECK-BE-OPT-NEXT: vmr 2, 31140; CHECK-BE-OPT-NEXT: blr1141;1142; CHECK-BE-O0-LABEL: shuffle_vector_byte_23_7:1143; CHECK-BE-O0: # %bb.0: # %entry1144; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1145; CHECK-BE-O0-NEXT: vmr 3, 21146; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1147; CHECK-BE-O0-NEXT: vinsertb 2, 3, 71148; CHECK-BE-O0-NEXT: blr1149entry:1150 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1151 ret <16 x i8> %vecins1152}1153 1154define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) {1155; CHECK-OPT-LABEL: shuffle_vector_byte_24_0:1156; CHECK-OPT: # %bb.0: # %entry1157; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 81158; CHECK-OPT-NEXT: vinsertb 3, 2, 71159; CHECK-OPT-NEXT: vmr 2, 31160; CHECK-OPT-NEXT: blr1161;1162; CHECK-O0-LABEL: shuffle_vector_byte_24_0:1163; CHECK-O0: # %bb.0: # %entry1164; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1165; CHECK-O0-NEXT: vmr 3, 21166; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1167; CHECK-O0-NEXT: vsldoi 3, 3, 3, 81168; CHECK-O0-NEXT: vinsertb 2, 3, 71169; CHECK-O0-NEXT: blr1170;1171; CHECK-BE-OPT-LABEL: shuffle_vector_byte_24_0:1172; CHECK-BE-OPT: # %bb.0: # %entry1173; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 91174; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 81175; CHECK-BE-OPT-NEXT: vmr 2, 31176; CHECK-BE-OPT-NEXT: blr1177;1178; CHECK-BE-O0-LABEL: shuffle_vector_byte_24_0:1179; CHECK-BE-O0: # %bb.0: # %entry1180; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1181; CHECK-BE-O0-NEXT: vmr 3, 21182; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1183; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 91184; CHECK-BE-O0-NEXT: vinsertb 2, 3, 81185; CHECK-BE-O0-NEXT: blr1186entry:1187 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1188 ret <16 x i8> %vecins1189}1190 1191define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) {1192; CHECK-OPT-LABEL: shuffle_vector_byte_25_9:1193; CHECK-OPT: # %bb.0: # %entry1194; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 151195; CHECK-OPT-NEXT: vinsertb 3, 2, 61196; CHECK-OPT-NEXT: vmr 2, 31197; CHECK-OPT-NEXT: blr1198;1199; CHECK-O0-LABEL: shuffle_vector_byte_25_9:1200; CHECK-O0: # %bb.0: # %entry1201; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1202; CHECK-O0-NEXT: vmr 3, 21203; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1204; CHECK-O0-NEXT: vsldoi 3, 3, 3, 151205; CHECK-O0-NEXT: vinsertb 2, 3, 61206; CHECK-O0-NEXT: blr1207;1208; CHECK-BE-OPT-LABEL: shuffle_vector_byte_25_9:1209; CHECK-BE-OPT: # %bb.0: # %entry1210; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 21211; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 91212; CHECK-BE-OPT-NEXT: vmr 2, 31213; CHECK-BE-OPT-NEXT: blr1214;1215; CHECK-BE-O0-LABEL: shuffle_vector_byte_25_9:1216; CHECK-BE-O0: # %bb.0: # %entry1217; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1218; CHECK-BE-O0-NEXT: vmr 3, 21219; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1220; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 21221; CHECK-BE-O0-NEXT: vinsertb 2, 3, 91222; CHECK-BE-O0-NEXT: blr1223entry:1224 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>1225 ret <16 x i8> %vecins1226}1227 1228define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) {1229; CHECK-OPT-LABEL: shuffle_vector_byte_26_2:1230; CHECK-OPT: # %bb.0: # %entry1231; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 61232; CHECK-OPT-NEXT: vinsertb 3, 2, 51233; CHECK-OPT-NEXT: vmr 2, 31234; CHECK-OPT-NEXT: blr1235;1236; CHECK-O0-LABEL: shuffle_vector_byte_26_2:1237; CHECK-O0: # %bb.0: # %entry1238; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1239; CHECK-O0-NEXT: vmr 3, 21240; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1241; CHECK-O0-NEXT: vsldoi 3, 3, 3, 61242; CHECK-O0-NEXT: vinsertb 2, 3, 51243; CHECK-O0-NEXT: blr1244;1245; CHECK-BE-OPT-LABEL: shuffle_vector_byte_26_2:1246; CHECK-BE-OPT: # %bb.0: # %entry1247; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 111248; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 101249; CHECK-BE-OPT-NEXT: vmr 2, 31250; CHECK-BE-OPT-NEXT: blr1251;1252; CHECK-BE-O0-LABEL: shuffle_vector_byte_26_2:1253; CHECK-BE-O0: # %bb.0: # %entry1254; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1255; CHECK-BE-O0-NEXT: vmr 3, 21256; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1257; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 111258; CHECK-BE-O0-NEXT: vinsertb 2, 3, 101259; CHECK-BE-O0-NEXT: blr1260entry:1261 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31>1262 ret <16 x i8> %vecins1263}1264 1265define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) {1266; CHECK-OPT-LABEL: shuffle_vector_byte_27_11:1267; CHECK-OPT: # %bb.0: # %entry1268; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 131269; CHECK-OPT-NEXT: vinsertb 3, 2, 41270; CHECK-OPT-NEXT: vmr 2, 31271; CHECK-OPT-NEXT: blr1272;1273; CHECK-O0-LABEL: shuffle_vector_byte_27_11:1274; CHECK-O0: # %bb.0: # %entry1275; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1276; CHECK-O0-NEXT: vmr 3, 21277; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1278; CHECK-O0-NEXT: vsldoi 3, 3, 3, 131279; CHECK-O0-NEXT: vinsertb 2, 3, 41280; CHECK-O0-NEXT: blr1281;1282; CHECK-BE-OPT-LABEL: shuffle_vector_byte_27_11:1283; CHECK-BE-OPT: # %bb.0: # %entry1284; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 41285; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 111286; CHECK-BE-OPT-NEXT: vmr 2, 31287; CHECK-BE-OPT-NEXT: blr1288;1289; CHECK-BE-O0-LABEL: shuffle_vector_byte_27_11:1290; CHECK-BE-O0: # %bb.0: # %entry1291; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1292; CHECK-BE-O0-NEXT: vmr 3, 21293; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1294; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 41295; CHECK-BE-O0-NEXT: vinsertb 2, 3, 111296; CHECK-BE-O0-NEXT: blr1297entry:1298 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31>1299 ret <16 x i8> %vecins1300}1301 1302define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) {1303; CHECK-OPT-LABEL: shuffle_vector_byte_28_4:1304; CHECK-OPT: # %bb.0: # %entry1305; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 41306; CHECK-OPT-NEXT: vinsertb 3, 2, 31307; CHECK-OPT-NEXT: vmr 2, 31308; CHECK-OPT-NEXT: blr1309;1310; CHECK-O0-LABEL: shuffle_vector_byte_28_4:1311; CHECK-O0: # %bb.0: # %entry1312; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1313; CHECK-O0-NEXT: vmr 3, 21314; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1315; CHECK-O0-NEXT: vsldoi 3, 3, 3, 41316; CHECK-O0-NEXT: vinsertb 2, 3, 31317; CHECK-O0-NEXT: blr1318;1319; CHECK-BE-OPT-LABEL: shuffle_vector_byte_28_4:1320; CHECK-BE-OPT: # %bb.0: # %entry1321; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 131322; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 121323; CHECK-BE-OPT-NEXT: vmr 2, 31324; CHECK-BE-OPT-NEXT: blr1325;1326; CHECK-BE-O0-LABEL: shuffle_vector_byte_28_4:1327; CHECK-BE-O0: # %bb.0: # %entry1328; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1329; CHECK-BE-O0-NEXT: vmr 3, 21330; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1331; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 131332; CHECK-BE-O0-NEXT: vinsertb 2, 3, 121333; CHECK-BE-O0-NEXT: blr1334entry:1335 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31>1336 ret <16 x i8> %vecins1337}1338 1339define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) {1340; CHECK-OPT-LABEL: shuffle_vector_byte_29_13:1341; CHECK-OPT: # %bb.0: # %entry1342; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 111343; CHECK-OPT-NEXT: vinsertb 3, 2, 21344; CHECK-OPT-NEXT: vmr 2, 31345; CHECK-OPT-NEXT: blr1346;1347; CHECK-O0-LABEL: shuffle_vector_byte_29_13:1348; CHECK-O0: # %bb.0: # %entry1349; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1350; CHECK-O0-NEXT: vmr 3, 21351; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1352; CHECK-O0-NEXT: vsldoi 3, 3, 3, 111353; CHECK-O0-NEXT: vinsertb 2, 3, 21354; CHECK-O0-NEXT: blr1355;1356; CHECK-BE-OPT-LABEL: shuffle_vector_byte_29_13:1357; CHECK-BE-OPT: # %bb.0: # %entry1358; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 61359; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 131360; CHECK-BE-OPT-NEXT: vmr 2, 31361; CHECK-BE-OPT-NEXT: blr1362;1363; CHECK-BE-O0-LABEL: shuffle_vector_byte_29_13:1364; CHECK-BE-O0: # %bb.0: # %entry1365; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1366; CHECK-BE-O0-NEXT: vmr 3, 21367; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1368; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 61369; CHECK-BE-O0-NEXT: vinsertb 2, 3, 131370; CHECK-BE-O0-NEXT: blr1371entry:1372 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31>1373 ret <16 x i8> %vecins1374}1375 1376define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) {1377; CHECK-OPT-LABEL: shuffle_vector_byte_30_6:1378; CHECK-OPT: # %bb.0: # %entry1379; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 21380; CHECK-OPT-NEXT: vinsertb 3, 2, 11381; CHECK-OPT-NEXT: vmr 2, 31382; CHECK-OPT-NEXT: blr1383;1384; CHECK-O0-LABEL: shuffle_vector_byte_30_6:1385; CHECK-O0: # %bb.0: # %entry1386; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1387; CHECK-O0-NEXT: vmr 3, 21388; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1389; CHECK-O0-NEXT: vsldoi 3, 3, 3, 21390; CHECK-O0-NEXT: vinsertb 2, 3, 11391; CHECK-O0-NEXT: blr1392;1393; CHECK-BE-OPT-LABEL: shuffle_vector_byte_30_6:1394; CHECK-BE-OPT: # %bb.0: # %entry1395; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 151396; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 141397; CHECK-BE-OPT-NEXT: vmr 2, 31398; CHECK-BE-OPT-NEXT: blr1399;1400; CHECK-BE-O0-LABEL: shuffle_vector_byte_30_6:1401; CHECK-BE-O0: # %bb.0: # %entry1402; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1403; CHECK-BE-O0-NEXT: vmr 3, 21404; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1405; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 151406; CHECK-BE-O0-NEXT: vinsertb 2, 3, 141407; CHECK-BE-O0-NEXT: blr1408entry:1409 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31>1410 ret <16 x i8> %vecins1411}1412 1413define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) {1414; CHECK-OPT-LABEL: shuffle_vector_byte_31_15:1415; CHECK-OPT: # %bb.0: # %entry1416; CHECK-OPT-NEXT: vsldoi 2, 2, 2, 91417; CHECK-OPT-NEXT: vinsertb 3, 2, 01418; CHECK-OPT-NEXT: vmr 2, 31419; CHECK-OPT-NEXT: blr1420;1421; CHECK-O0-LABEL: shuffle_vector_byte_31_15:1422; CHECK-O0: # %bb.0: # %entry1423; CHECK-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1424; CHECK-O0-NEXT: vmr 3, 21425; CHECK-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1426; CHECK-O0-NEXT: vsldoi 3, 3, 3, 91427; CHECK-O0-NEXT: vinsertb 2, 3, 01428; CHECK-O0-NEXT: blr1429;1430; CHECK-BE-OPT-LABEL: shuffle_vector_byte_31_15:1431; CHECK-BE-OPT: # %bb.0: # %entry1432; CHECK-BE-OPT-NEXT: vsldoi 2, 2, 2, 81433; CHECK-BE-OPT-NEXT: vinsertb 3, 2, 151434; CHECK-BE-OPT-NEXT: vmr 2, 31435; CHECK-BE-OPT-NEXT: blr1436;1437; CHECK-BE-O0-LABEL: shuffle_vector_byte_31_15:1438; CHECK-BE-O0: # %bb.0: # %entry1439; CHECK-BE-O0-NEXT: stxv 35, -16(1) # 16-byte Folded Spill1440; CHECK-BE-O0-NEXT: vmr 3, 21441; CHECK-BE-O0-NEXT: lxv 34, -16(1) # 16-byte Folded Reload1442; CHECK-BE-O0-NEXT: vsldoi 3, 3, 3, 81443; CHECK-BE-O0-NEXT: vinsertb 2, 3, 151444; CHECK-BE-O0-NEXT: blr1445entry:1446 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15>1447 ret <16 x i8> %vecins1448}1449 1450; The following testcases use the same vector in both arguments of the1451; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one1452; we're attempting to insert, then we can use the vector insert instruction1453define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) {1454; CHECK-LABEL: shuffle_vector_byte_0_7:1455; CHECK: # %bb.0: # %entry1456; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha1457; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l1458; CHECK-NEXT: lxv 0, 0(3)1459; CHECK-NEXT: xxperm 34, 34, 01460; CHECK-NEXT: blr1461;1462; CHECK-BE-LABEL: shuffle_vector_byte_0_7:1463; CHECK-BE: # %bb.0: # %entry1464; CHECK-BE-NEXT: vinsertb 2, 2, 01465; CHECK-BE-NEXT: blr1466entry:1467 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1468 ret <16 x i8> %vecins1469}1470 1471define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) {1472; CHECK-LABEL: shuffle_vector_byte_1_8:1473; CHECK: # %bb.0: # %entry1474; CHECK-NEXT: vinsertb 2, 2, 141475; CHECK-NEXT: blr1476;1477; CHECK-BE-LABEL: shuffle_vector_byte_1_8:1478; CHECK-BE: # %bb.0: # %entry1479; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha1480; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l1481; CHECK-BE-NEXT: lxv 0, 0(3)1482; CHECK-BE-NEXT: xxperm 34, 34, 01483; CHECK-BE-NEXT: blr1484entry:1485 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1486 ret <16 x i8> %vecins1487}1488 1489define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) {1490; CHECK-LABEL: shuffle_vector_byte_2_8:1491; CHECK: # %bb.0: # %entry1492; CHECK-NEXT: vinsertb 2, 2, 131493; CHECK-NEXT: blr1494;1495; CHECK-BE-LABEL: shuffle_vector_byte_2_8:1496; CHECK-BE: # %bb.0: # %entry1497; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha1498; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l1499; CHECK-BE-NEXT: lxv 0, 0(3)1500; CHECK-BE-NEXT: xxperm 34, 34, 01501; CHECK-BE-NEXT: blr1502entry:1503 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1504 ret <16 x i8> %vecins1505}1506 1507define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) {1508; CHECK-LABEL: shuffle_vector_byte_3_7:1509; CHECK: # %bb.0: # %entry1510; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha1511; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l1512; CHECK-NEXT: lxv 0, 0(3)1513; CHECK-NEXT: xxperm 34, 34, 01514; CHECK-NEXT: blr1515;1516; CHECK-BE-LABEL: shuffle_vector_byte_3_7:1517; CHECK-BE: # %bb.0: # %entry1518; CHECK-BE-NEXT: vinsertb 2, 2, 31519; CHECK-BE-NEXT: blr1520entry:1521 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1522 ret <16 x i8> %vecins1523}1524 1525define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) {1526; CHECK-LABEL: shuffle_vector_byte_4_7:1527; CHECK: # %bb.0: # %entry1528; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha1529; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l1530; CHECK-NEXT: lxv 0, 0(3)1531; CHECK-NEXT: xxperm 34, 34, 01532; CHECK-NEXT: blr1533;1534; CHECK-BE-LABEL: shuffle_vector_byte_4_7:1535; CHECK-BE: # %bb.0: # %entry1536; CHECK-BE-NEXT: vinsertb 2, 2, 41537; CHECK-BE-NEXT: blr1538entry:1539 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1540 ret <16 x i8> %vecins1541}1542 1543define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) {1544; CHECK-LABEL: shuffle_vector_byte_5_8:1545; CHECK: # %bb.0: # %entry1546; CHECK-NEXT: vinsertb 2, 2, 101547; CHECK-NEXT: blr1548;1549; CHECK-BE-LABEL: shuffle_vector_byte_5_8:1550; CHECK-BE: # %bb.0: # %entry1551; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha1552; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l1553; CHECK-BE-NEXT: lxv 0, 0(3)1554; CHECK-BE-NEXT: xxperm 34, 34, 01555; CHECK-BE-NEXT: blr1556entry:1557 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1558 ret <16 x i8> %vecins1559}1560 1561define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) {1562; CHECK-LABEL: shuffle_vector_byte_6_8:1563; CHECK: # %bb.0: # %entry1564; CHECK-NEXT: vinsertb 2, 2, 91565; CHECK-NEXT: blr1566;1567; CHECK-BE-LABEL: shuffle_vector_byte_6_8:1568; CHECK-BE: # %bb.0: # %entry1569; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha1570; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l1571; CHECK-BE-NEXT: lxv 0, 0(3)1572; CHECK-BE-NEXT: xxperm 34, 34, 01573; CHECK-BE-NEXT: blr1574entry:1575 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1576 ret <16 x i8> %vecins1577}1578 1579define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) {1580; CHECK-LABEL: shuffle_vector_byte_7_8:1581; CHECK: # %bb.0: # %entry1582; CHECK-NEXT: vinsertb 2, 2, 81583; CHECK-NEXT: blr1584;1585; CHECK-BE-LABEL: shuffle_vector_byte_7_8:1586; CHECK-BE: # %bb.0: # %entry1587; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha1588; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l1589; CHECK-BE-NEXT: lxv 0, 0(3)1590; CHECK-BE-NEXT: xxperm 34, 34, 01591; CHECK-BE-NEXT: blr1592entry:1593 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1594 ret <16 x i8> %vecins1595}1596 1597define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) {1598; CHECK-LABEL: shuffle_vector_byte_8_7:1599; CHECK: # %bb.0: # %entry1600; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha1601; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l1602; CHECK-NEXT: lxv 0, 0(3)1603; CHECK-NEXT: xxperm 34, 34, 01604; CHECK-NEXT: blr1605;1606; CHECK-BE-LABEL: shuffle_vector_byte_8_7:1607; CHECK-BE: # %bb.0: # %entry1608; CHECK-BE-NEXT: vinsertb 2, 2, 81609; CHECK-BE-NEXT: blr1610entry:1611 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1612 ret <16 x i8> %vecins1613}1614 1615define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) {1616; CHECK-LABEL: shuffle_vector_byte_9_7:1617; CHECK: # %bb.0: # %entry1618; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha1619; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l1620; CHECK-NEXT: lxv 0, 0(3)1621; CHECK-NEXT: xxperm 34, 34, 01622; CHECK-NEXT: blr1623;1624; CHECK-BE-LABEL: shuffle_vector_byte_9_7:1625; CHECK-BE: # %bb.0: # %entry1626; CHECK-BE-NEXT: vinsertb 2, 2, 91627; CHECK-BE-NEXT: blr1628entry:1629 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1630 ret <16 x i8> %vecins1631}1632 1633define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) {1634; CHECK-LABEL: shuffle_vector_byte_10_7:1635; CHECK: # %bb.0: # %entry1636; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha1637; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l1638; CHECK-NEXT: lxv 0, 0(3)1639; CHECK-NEXT: xxperm 34, 34, 01640; CHECK-NEXT: blr1641;1642; CHECK-BE-LABEL: shuffle_vector_byte_10_7:1643; CHECK-BE: # %bb.0: # %entry1644; CHECK-BE-NEXT: vinsertb 2, 2, 101645; CHECK-BE-NEXT: blr1646entry:1647 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15>1648 ret <16 x i8> %vecins1649}1650 1651define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) {1652; CHECK-LABEL: shuffle_vector_byte_11_8:1653; CHECK: # %bb.0: # %entry1654; CHECK-NEXT: vinsertb 2, 2, 41655; CHECK-NEXT: blr1656;1657; CHECK-BE-LABEL: shuffle_vector_byte_11_8:1658; CHECK-BE: # %bb.0: # %entry1659; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha1660; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l1661; CHECK-BE-NEXT: lxv 0, 0(3)1662; CHECK-BE-NEXT: xxperm 34, 34, 01663; CHECK-BE-NEXT: blr1664entry:1665 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15>1666 ret <16 x i8> %vecins1667}1668 1669define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) {1670; CHECK-LABEL: shuffle_vector_byte_12_8:1671; CHECK: # %bb.0: # %entry1672; CHECK-NEXT: vinsertb 2, 2, 31673; CHECK-NEXT: blr1674;1675; CHECK-BE-LABEL: shuffle_vector_byte_12_8:1676; CHECK-BE: # %bb.0: # %entry1677; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha1678; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l1679; CHECK-BE-NEXT: lxv 0, 0(3)1680; CHECK-BE-NEXT: xxperm 34, 34, 01681; CHECK-BE-NEXT: blr1682entry:1683 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15>1684 ret <16 x i8> %vecins1685}1686 1687define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) {1688; CHECK-LABEL: shuffle_vector_byte_13_7:1689; CHECK: # %bb.0: # %entry1690; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha1691; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l1692; CHECK-NEXT: lxv 0, 0(3)1693; CHECK-NEXT: xxperm 34, 34, 01694; CHECK-NEXT: blr1695;1696; CHECK-BE-LABEL: shuffle_vector_byte_13_7:1697; CHECK-BE: # %bb.0: # %entry1698; CHECK-BE-NEXT: vinsertb 2, 2, 131699; CHECK-BE-NEXT: blr1700entry:1701 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15>1702 ret <16 x i8> %vecins1703}1704 1705define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) {1706; CHECK-LABEL: shuffle_vector_byte_14_7:1707; CHECK: # %bb.0: # %entry1708; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha1709; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l1710; CHECK-NEXT: lxv 0, 0(3)1711; CHECK-NEXT: xxperm 34, 34, 01712; CHECK-NEXT: blr1713;1714; CHECK-BE-LABEL: shuffle_vector_byte_14_7:1715; CHECK-BE: # %bb.0: # %entry1716; CHECK-BE-NEXT: vinsertb 2, 2, 141717; CHECK-BE-NEXT: blr1718entry:1719 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15>1720 ret <16 x i8> %vecins1721}1722 1723define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) {1724; CHECK-LABEL: shuffle_vector_byte_15_8:1725; CHECK: # %bb.0: # %entry1726; CHECK-NEXT: vinsertb 2, 2, 01727; CHECK-NEXT: blr1728;1729; CHECK-BE-LABEL: shuffle_vector_byte_15_8:1730; CHECK-BE: # %bb.0: # %entry1731; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha1732; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l1733; CHECK-BE-NEXT: lxv 0, 0(3)1734; CHECK-BE-NEXT: xxperm 34, 34, 01735; CHECK-BE-NEXT: blr1736entry:1737 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8>1738 ret <16 x i8> %vecins1739}1740 1741; The following tests try to insert one halfword element into the vector. We1742; should always be using the 'vinserth' instruction.1743define <8 x i16> @insert_halfword_0(<8 x i16> %a, i16 %b) {1744; CHECK-OPT-LABEL: insert_halfword_0:1745; CHECK-OPT: # %bb.0: # %entry1746; CHECK-OPT-NEXT: mtvsrwz 35, 51747; CHECK-OPT-NEXT: vinserth 2, 3, 141748; CHECK-OPT-NEXT: blr1749;1750; CHECK-O0-LABEL: insert_halfword_0:1751; CHECK-O0: # %bb.0: # %entry1752; CHECK-O0-NEXT: mr 3, 51753; CHECK-O0-NEXT: mtfprwz 0, 31754; CHECK-O0-NEXT: xscpsgndp 35, 0, 01755; CHECK-O0-NEXT: vinserth 2, 3, 141756; CHECK-O0-NEXT: blr1757;1758; CHECK-BE-OPT-LABEL: insert_halfword_0:1759; CHECK-BE-OPT: # %bb.0: # %entry1760; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51761; CHECK-BE-OPT-NEXT: vinserth 2, 3, 01762; CHECK-BE-OPT-NEXT: blr1763;1764; CHECK-BE-O0-LABEL: insert_halfword_0:1765; CHECK-BE-O0: # %bb.0: # %entry1766; CHECK-BE-O0-NEXT: mr 3, 51767; CHECK-BE-O0-NEXT: mtfprwz 0, 31768; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01769; CHECK-BE-O0-NEXT: vinserth 2, 3, 01770; CHECK-BE-O0-NEXT: blr1771entry:1772 %vecins = insertelement <8 x i16> %a, i16 %b, i32 01773 ret <8 x i16> %vecins1774}1775 1776define <8 x i16> @insert_halfword_1(<8 x i16> %a, i16 %b) {1777; CHECK-OPT-LABEL: insert_halfword_1:1778; CHECK-OPT: # %bb.0: # %entry1779; CHECK-OPT-NEXT: mtvsrwz 35, 51780; CHECK-OPT-NEXT: vinserth 2, 3, 121781; CHECK-OPT-NEXT: blr1782;1783; CHECK-O0-LABEL: insert_halfword_1:1784; CHECK-O0: # %bb.0: # %entry1785; CHECK-O0-NEXT: mr 3, 51786; CHECK-O0-NEXT: mtfprwz 0, 31787; CHECK-O0-NEXT: xscpsgndp 35, 0, 01788; CHECK-O0-NEXT: vinserth 2, 3, 121789; CHECK-O0-NEXT: blr1790;1791; CHECK-BE-OPT-LABEL: insert_halfword_1:1792; CHECK-BE-OPT: # %bb.0: # %entry1793; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51794; CHECK-BE-OPT-NEXT: vinserth 2, 3, 21795; CHECK-BE-OPT-NEXT: blr1796;1797; CHECK-BE-O0-LABEL: insert_halfword_1:1798; CHECK-BE-O0: # %bb.0: # %entry1799; CHECK-BE-O0-NEXT: mr 3, 51800; CHECK-BE-O0-NEXT: mtfprwz 0, 31801; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01802; CHECK-BE-O0-NEXT: vinserth 2, 3, 21803; CHECK-BE-O0-NEXT: blr1804entry:1805 %vecins = insertelement <8 x i16> %a, i16 %b, i32 11806 ret <8 x i16> %vecins1807}1808 1809define <8 x i16> @insert_halfword_2(<8 x i16> %a, i16 %b) {1810; CHECK-OPT-LABEL: insert_halfword_2:1811; CHECK-OPT: # %bb.0: # %entry1812; CHECK-OPT-NEXT: mtvsrwz 35, 51813; CHECK-OPT-NEXT: vinserth 2, 3, 101814; CHECK-OPT-NEXT: blr1815;1816; CHECK-O0-LABEL: insert_halfword_2:1817; CHECK-O0: # %bb.0: # %entry1818; CHECK-O0-NEXT: mr 3, 51819; CHECK-O0-NEXT: mtfprwz 0, 31820; CHECK-O0-NEXT: xscpsgndp 35, 0, 01821; CHECK-O0-NEXT: vinserth 2, 3, 101822; CHECK-O0-NEXT: blr1823;1824; CHECK-BE-OPT-LABEL: insert_halfword_2:1825; CHECK-BE-OPT: # %bb.0: # %entry1826; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51827; CHECK-BE-OPT-NEXT: vinserth 2, 3, 41828; CHECK-BE-OPT-NEXT: blr1829;1830; CHECK-BE-O0-LABEL: insert_halfword_2:1831; CHECK-BE-O0: # %bb.0: # %entry1832; CHECK-BE-O0-NEXT: mr 3, 51833; CHECK-BE-O0-NEXT: mtfprwz 0, 31834; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01835; CHECK-BE-O0-NEXT: vinserth 2, 3, 41836; CHECK-BE-O0-NEXT: blr1837entry:1838 %vecins = insertelement <8 x i16> %a, i16 %b, i32 21839 ret <8 x i16> %vecins1840}1841 1842define <8 x i16> @insert_halfword_3(<8 x i16> %a, i16 %b) {1843; CHECK-OPT-LABEL: insert_halfword_3:1844; CHECK-OPT: # %bb.0: # %entry1845; CHECK-OPT-NEXT: mtvsrwz 35, 51846; CHECK-OPT-NEXT: vinserth 2, 3, 81847; CHECK-OPT-NEXT: blr1848;1849; CHECK-O0-LABEL: insert_halfword_3:1850; CHECK-O0: # %bb.0: # %entry1851; CHECK-O0-NEXT: mr 3, 51852; CHECK-O0-NEXT: mtfprwz 0, 31853; CHECK-O0-NEXT: xscpsgndp 35, 0, 01854; CHECK-O0-NEXT: vinserth 2, 3, 81855; CHECK-O0-NEXT: blr1856;1857; CHECK-BE-OPT-LABEL: insert_halfword_3:1858; CHECK-BE-OPT: # %bb.0: # %entry1859; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51860; CHECK-BE-OPT-NEXT: vinserth 2, 3, 61861; CHECK-BE-OPT-NEXT: blr1862;1863; CHECK-BE-O0-LABEL: insert_halfword_3:1864; CHECK-BE-O0: # %bb.0: # %entry1865; CHECK-BE-O0-NEXT: mr 3, 51866; CHECK-BE-O0-NEXT: mtfprwz 0, 31867; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01868; CHECK-BE-O0-NEXT: vinserth 2, 3, 61869; CHECK-BE-O0-NEXT: blr1870entry:1871 %vecins = insertelement <8 x i16> %a, i16 %b, i32 31872 ret <8 x i16> %vecins1873}1874 1875define <8 x i16> @insert_halfword_4(<8 x i16> %a, i16 %b) {1876; CHECK-OPT-LABEL: insert_halfword_4:1877; CHECK-OPT: # %bb.0: # %entry1878; CHECK-OPT-NEXT: mtvsrwz 35, 51879; CHECK-OPT-NEXT: vinserth 2, 3, 61880; CHECK-OPT-NEXT: blr1881;1882; CHECK-O0-LABEL: insert_halfword_4:1883; CHECK-O0: # %bb.0: # %entry1884; CHECK-O0-NEXT: mr 3, 51885; CHECK-O0-NEXT: mtfprwz 0, 31886; CHECK-O0-NEXT: xscpsgndp 35, 0, 01887; CHECK-O0-NEXT: vinserth 2, 3, 61888; CHECK-O0-NEXT: blr1889;1890; CHECK-BE-OPT-LABEL: insert_halfword_4:1891; CHECK-BE-OPT: # %bb.0: # %entry1892; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51893; CHECK-BE-OPT-NEXT: vinserth 2, 3, 81894; CHECK-BE-OPT-NEXT: blr1895;1896; CHECK-BE-O0-LABEL: insert_halfword_4:1897; CHECK-BE-O0: # %bb.0: # %entry1898; CHECK-BE-O0-NEXT: mr 3, 51899; CHECK-BE-O0-NEXT: mtfprwz 0, 31900; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01901; CHECK-BE-O0-NEXT: vinserth 2, 3, 81902; CHECK-BE-O0-NEXT: blr1903entry:1904 %vecins = insertelement <8 x i16> %a, i16 %b, i32 41905 ret <8 x i16> %vecins1906}1907 1908define <8 x i16> @insert_halfword_5(<8 x i16> %a, i16 %b) {1909; CHECK-OPT-LABEL: insert_halfword_5:1910; CHECK-OPT: # %bb.0: # %entry1911; CHECK-OPT-NEXT: mtvsrwz 35, 51912; CHECK-OPT-NEXT: vinserth 2, 3, 41913; CHECK-OPT-NEXT: blr1914;1915; CHECK-O0-LABEL: insert_halfword_5:1916; CHECK-O0: # %bb.0: # %entry1917; CHECK-O0-NEXT: mr 3, 51918; CHECK-O0-NEXT: mtfprwz 0, 31919; CHECK-O0-NEXT: xscpsgndp 35, 0, 01920; CHECK-O0-NEXT: vinserth 2, 3, 41921; CHECK-O0-NEXT: blr1922;1923; CHECK-BE-OPT-LABEL: insert_halfword_5:1924; CHECK-BE-OPT: # %bb.0: # %entry1925; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51926; CHECK-BE-OPT-NEXT: vinserth 2, 3, 101927; CHECK-BE-OPT-NEXT: blr1928;1929; CHECK-BE-O0-LABEL: insert_halfword_5:1930; CHECK-BE-O0: # %bb.0: # %entry1931; CHECK-BE-O0-NEXT: mr 3, 51932; CHECK-BE-O0-NEXT: mtfprwz 0, 31933; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01934; CHECK-BE-O0-NEXT: vinserth 2, 3, 101935; CHECK-BE-O0-NEXT: blr1936entry:1937 %vecins = insertelement <8 x i16> %a, i16 %b, i32 51938 ret <8 x i16> %vecins1939}1940 1941define <8 x i16> @insert_halfword_6(<8 x i16> %a, i16 %b) {1942; CHECK-OPT-LABEL: insert_halfword_6:1943; CHECK-OPT: # %bb.0: # %entry1944; CHECK-OPT-NEXT: mtvsrwz 35, 51945; CHECK-OPT-NEXT: vinserth 2, 3, 21946; CHECK-OPT-NEXT: blr1947;1948; CHECK-O0-LABEL: insert_halfword_6:1949; CHECK-O0: # %bb.0: # %entry1950; CHECK-O0-NEXT: mr 3, 51951; CHECK-O0-NEXT: mtfprwz 0, 31952; CHECK-O0-NEXT: xscpsgndp 35, 0, 01953; CHECK-O0-NEXT: vinserth 2, 3, 21954; CHECK-O0-NEXT: blr1955;1956; CHECK-BE-OPT-LABEL: insert_halfword_6:1957; CHECK-BE-OPT: # %bb.0: # %entry1958; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51959; CHECK-BE-OPT-NEXT: vinserth 2, 3, 121960; CHECK-BE-OPT-NEXT: blr1961;1962; CHECK-BE-O0-LABEL: insert_halfword_6:1963; CHECK-BE-O0: # %bb.0: # %entry1964; CHECK-BE-O0-NEXT: mr 3, 51965; CHECK-BE-O0-NEXT: mtfprwz 0, 31966; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 01967; CHECK-BE-O0-NEXT: vinserth 2, 3, 121968; CHECK-BE-O0-NEXT: blr1969entry:1970 %vecins = insertelement <8 x i16> %a, i16 %b, i32 61971 ret <8 x i16> %vecins1972}1973 1974define <8 x i16> @insert_halfword_7(<8 x i16> %a, i16 %b) {1975; CHECK-OPT-LABEL: insert_halfword_7:1976; CHECK-OPT: # %bb.0: # %entry1977; CHECK-OPT-NEXT: mtvsrwz 35, 51978; CHECK-OPT-NEXT: vinserth 2, 3, 01979; CHECK-OPT-NEXT: blr1980;1981; CHECK-O0-LABEL: insert_halfword_7:1982; CHECK-O0: # %bb.0: # %entry1983; CHECK-O0-NEXT: mr 3, 51984; CHECK-O0-NEXT: mtfprwz 0, 31985; CHECK-O0-NEXT: xscpsgndp 35, 0, 01986; CHECK-O0-NEXT: vinserth 2, 3, 01987; CHECK-O0-NEXT: blr1988;1989; CHECK-BE-OPT-LABEL: insert_halfword_7:1990; CHECK-BE-OPT: # %bb.0: # %entry1991; CHECK-BE-OPT-NEXT: mtvsrwz 35, 51992; CHECK-BE-OPT-NEXT: vinserth 2, 3, 141993; CHECK-BE-OPT-NEXT: blr1994;1995; CHECK-BE-O0-LABEL: insert_halfword_7:1996; CHECK-BE-O0: # %bb.0: # %entry1997; CHECK-BE-O0-NEXT: mr 3, 51998; CHECK-BE-O0-NEXT: mtfprwz 0, 31999; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02000; CHECK-BE-O0-NEXT: vinserth 2, 3, 142001; CHECK-BE-O0-NEXT: blr2002entry:2003 %vecins = insertelement <8 x i16> %a, i16 %b, i32 72004 ret <8 x i16> %vecins2005}2006 2007; The following tests try to insert one byte element into the vector. We2008; should always be using the 'vinsertb' instruction.2009define <16 x i8> @insert_byte_0(<16 x i8> %a, i8 %b) {2010; CHECK-OPT-LABEL: insert_byte_0:2011; CHECK-OPT: # %bb.0: # %entry2012; CHECK-OPT-NEXT: mtvsrwz 35, 52013; CHECK-OPT-NEXT: vinsertb 2, 3, 152014; CHECK-OPT-NEXT: blr2015;2016; CHECK-O0-LABEL: insert_byte_0:2017; CHECK-O0: # %bb.0: # %entry2018; CHECK-O0-NEXT: mr 3, 52019; CHECK-O0-NEXT: mtfprwz 0, 32020; CHECK-O0-NEXT: xscpsgndp 35, 0, 02021; CHECK-O0-NEXT: vinsertb 2, 3, 152022; CHECK-O0-NEXT: blr2023;2024; CHECK-BE-OPT-LABEL: insert_byte_0:2025; CHECK-BE-OPT: # %bb.0: # %entry2026; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52027; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 02028; CHECK-BE-OPT-NEXT: blr2029;2030; CHECK-BE-O0-LABEL: insert_byte_0:2031; CHECK-BE-O0: # %bb.0: # %entry2032; CHECK-BE-O0-NEXT: mr 3, 52033; CHECK-BE-O0-NEXT: mtfprwz 0, 32034; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02035; CHECK-BE-O0-NEXT: vinsertb 2, 3, 02036; CHECK-BE-O0-NEXT: blr2037entry:2038 %vecins = insertelement <16 x i8> %a, i8 %b, i32 02039 ret <16 x i8> %vecins2040}2041 2042define <16 x i8> @insert_byte_1(<16 x i8> %a, i8 %b) {2043; CHECK-OPT-LABEL: insert_byte_1:2044; CHECK-OPT: # %bb.0: # %entry2045; CHECK-OPT-NEXT: mtvsrwz 35, 52046; CHECK-OPT-NEXT: vinsertb 2, 3, 142047; CHECK-OPT-NEXT: blr2048;2049; CHECK-O0-LABEL: insert_byte_1:2050; CHECK-O0: # %bb.0: # %entry2051; CHECK-O0-NEXT: mr 3, 52052; CHECK-O0-NEXT: mtfprwz 0, 32053; CHECK-O0-NEXT: xscpsgndp 35, 0, 02054; CHECK-O0-NEXT: vinsertb 2, 3, 142055; CHECK-O0-NEXT: blr2056;2057; CHECK-BE-OPT-LABEL: insert_byte_1:2058; CHECK-BE-OPT: # %bb.0: # %entry2059; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52060; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 12061; CHECK-BE-OPT-NEXT: blr2062;2063; CHECK-BE-O0-LABEL: insert_byte_1:2064; CHECK-BE-O0: # %bb.0: # %entry2065; CHECK-BE-O0-NEXT: mr 3, 52066; CHECK-BE-O0-NEXT: mtfprwz 0, 32067; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02068; CHECK-BE-O0-NEXT: vinsertb 2, 3, 12069; CHECK-BE-O0-NEXT: blr2070entry:2071 %vecins = insertelement <16 x i8> %a, i8 %b, i32 12072 ret <16 x i8> %vecins2073}2074 2075define <16 x i8> @insert_byte_2(<16 x i8> %a, i8 %b) {2076; CHECK-OPT-LABEL: insert_byte_2:2077; CHECK-OPT: # %bb.0: # %entry2078; CHECK-OPT-NEXT: mtvsrwz 35, 52079; CHECK-OPT-NEXT: vinsertb 2, 3, 132080; CHECK-OPT-NEXT: blr2081;2082; CHECK-O0-LABEL: insert_byte_2:2083; CHECK-O0: # %bb.0: # %entry2084; CHECK-O0-NEXT: mr 3, 52085; CHECK-O0-NEXT: mtfprwz 0, 32086; CHECK-O0-NEXT: xscpsgndp 35, 0, 02087; CHECK-O0-NEXT: vinsertb 2, 3, 132088; CHECK-O0-NEXT: blr2089;2090; CHECK-BE-OPT-LABEL: insert_byte_2:2091; CHECK-BE-OPT: # %bb.0: # %entry2092; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52093; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 22094; CHECK-BE-OPT-NEXT: blr2095;2096; CHECK-BE-O0-LABEL: insert_byte_2:2097; CHECK-BE-O0: # %bb.0: # %entry2098; CHECK-BE-O0-NEXT: mr 3, 52099; CHECK-BE-O0-NEXT: mtfprwz 0, 32100; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02101; CHECK-BE-O0-NEXT: vinsertb 2, 3, 22102; CHECK-BE-O0-NEXT: blr2103entry:2104 %vecins = insertelement <16 x i8> %a, i8 %b, i32 22105 ret <16 x i8> %vecins2106}2107 2108define <16 x i8> @insert_byte_3(<16 x i8> %a, i8 %b) {2109; CHECK-OPT-LABEL: insert_byte_3:2110; CHECK-OPT: # %bb.0: # %entry2111; CHECK-OPT-NEXT: mtvsrwz 35, 52112; CHECK-OPT-NEXT: vinsertb 2, 3, 122113; CHECK-OPT-NEXT: blr2114;2115; CHECK-O0-LABEL: insert_byte_3:2116; CHECK-O0: # %bb.0: # %entry2117; CHECK-O0-NEXT: mr 3, 52118; CHECK-O0-NEXT: mtfprwz 0, 32119; CHECK-O0-NEXT: xscpsgndp 35, 0, 02120; CHECK-O0-NEXT: vinsertb 2, 3, 122121; CHECK-O0-NEXT: blr2122;2123; CHECK-BE-OPT-LABEL: insert_byte_3:2124; CHECK-BE-OPT: # %bb.0: # %entry2125; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52126; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 32127; CHECK-BE-OPT-NEXT: blr2128;2129; CHECK-BE-O0-LABEL: insert_byte_3:2130; CHECK-BE-O0: # %bb.0: # %entry2131; CHECK-BE-O0-NEXT: mr 3, 52132; CHECK-BE-O0-NEXT: mtfprwz 0, 32133; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02134; CHECK-BE-O0-NEXT: vinsertb 2, 3, 32135; CHECK-BE-O0-NEXT: blr2136entry:2137 %vecins = insertelement <16 x i8> %a, i8 %b, i32 32138 ret <16 x i8> %vecins2139}2140 2141define <16 x i8> @insert_byte_4(<16 x i8> %a, i8 %b) {2142; CHECK-OPT-LABEL: insert_byte_4:2143; CHECK-OPT: # %bb.0: # %entry2144; CHECK-OPT-NEXT: mtvsrwz 35, 52145; CHECK-OPT-NEXT: vinsertb 2, 3, 112146; CHECK-OPT-NEXT: blr2147;2148; CHECK-O0-LABEL: insert_byte_4:2149; CHECK-O0: # %bb.0: # %entry2150; CHECK-O0-NEXT: mr 3, 52151; CHECK-O0-NEXT: mtfprwz 0, 32152; CHECK-O0-NEXT: xscpsgndp 35, 0, 02153; CHECK-O0-NEXT: vinsertb 2, 3, 112154; CHECK-O0-NEXT: blr2155;2156; CHECK-BE-OPT-LABEL: insert_byte_4:2157; CHECK-BE-OPT: # %bb.0: # %entry2158; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52159; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 42160; CHECK-BE-OPT-NEXT: blr2161;2162; CHECK-BE-O0-LABEL: insert_byte_4:2163; CHECK-BE-O0: # %bb.0: # %entry2164; CHECK-BE-O0-NEXT: mr 3, 52165; CHECK-BE-O0-NEXT: mtfprwz 0, 32166; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02167; CHECK-BE-O0-NEXT: vinsertb 2, 3, 42168; CHECK-BE-O0-NEXT: blr2169entry:2170 %vecins = insertelement <16 x i8> %a, i8 %b, i32 42171 ret <16 x i8> %vecins2172}2173 2174define <16 x i8> @insert_byte_5(<16 x i8> %a, i8 %b) {2175; CHECK-OPT-LABEL: insert_byte_5:2176; CHECK-OPT: # %bb.0: # %entry2177; CHECK-OPT-NEXT: mtvsrwz 35, 52178; CHECK-OPT-NEXT: vinsertb 2, 3, 102179; CHECK-OPT-NEXT: blr2180;2181; CHECK-O0-LABEL: insert_byte_5:2182; CHECK-O0: # %bb.0: # %entry2183; CHECK-O0-NEXT: mr 3, 52184; CHECK-O0-NEXT: mtfprwz 0, 32185; CHECK-O0-NEXT: xscpsgndp 35, 0, 02186; CHECK-O0-NEXT: vinsertb 2, 3, 102187; CHECK-O0-NEXT: blr2188;2189; CHECK-BE-OPT-LABEL: insert_byte_5:2190; CHECK-BE-OPT: # %bb.0: # %entry2191; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52192; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 52193; CHECK-BE-OPT-NEXT: blr2194;2195; CHECK-BE-O0-LABEL: insert_byte_5:2196; CHECK-BE-O0: # %bb.0: # %entry2197; CHECK-BE-O0-NEXT: mr 3, 52198; CHECK-BE-O0-NEXT: mtfprwz 0, 32199; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02200; CHECK-BE-O0-NEXT: vinsertb 2, 3, 52201; CHECK-BE-O0-NEXT: blr2202entry:2203 %vecins = insertelement <16 x i8> %a, i8 %b, i32 52204 ret <16 x i8> %vecins2205}2206 2207define <16 x i8> @insert_byte_6(<16 x i8> %a, i8 %b) {2208; CHECK-OPT-LABEL: insert_byte_6:2209; CHECK-OPT: # %bb.0: # %entry2210; CHECK-OPT-NEXT: mtvsrwz 35, 52211; CHECK-OPT-NEXT: vinsertb 2, 3, 92212; CHECK-OPT-NEXT: blr2213;2214; CHECK-O0-LABEL: insert_byte_6:2215; CHECK-O0: # %bb.0: # %entry2216; CHECK-O0-NEXT: mr 3, 52217; CHECK-O0-NEXT: mtfprwz 0, 32218; CHECK-O0-NEXT: xscpsgndp 35, 0, 02219; CHECK-O0-NEXT: vinsertb 2, 3, 92220; CHECK-O0-NEXT: blr2221;2222; CHECK-BE-OPT-LABEL: insert_byte_6:2223; CHECK-BE-OPT: # %bb.0: # %entry2224; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52225; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 62226; CHECK-BE-OPT-NEXT: blr2227;2228; CHECK-BE-O0-LABEL: insert_byte_6:2229; CHECK-BE-O0: # %bb.0: # %entry2230; CHECK-BE-O0-NEXT: mr 3, 52231; CHECK-BE-O0-NEXT: mtfprwz 0, 32232; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02233; CHECK-BE-O0-NEXT: vinsertb 2, 3, 62234; CHECK-BE-O0-NEXT: blr2235entry:2236 %vecins = insertelement <16 x i8> %a, i8 %b, i32 62237 ret <16 x i8> %vecins2238}2239 2240define <16 x i8> @insert_byte_7(<16 x i8> %a, i8 %b) {2241; CHECK-OPT-LABEL: insert_byte_7:2242; CHECK-OPT: # %bb.0: # %entry2243; CHECK-OPT-NEXT: mtvsrwz 35, 52244; CHECK-OPT-NEXT: vinsertb 2, 3, 82245; CHECK-OPT-NEXT: blr2246;2247; CHECK-O0-LABEL: insert_byte_7:2248; CHECK-O0: # %bb.0: # %entry2249; CHECK-O0-NEXT: mr 3, 52250; CHECK-O0-NEXT: mtfprwz 0, 32251; CHECK-O0-NEXT: xscpsgndp 35, 0, 02252; CHECK-O0-NEXT: vinsertb 2, 3, 82253; CHECK-O0-NEXT: blr2254;2255; CHECK-BE-OPT-LABEL: insert_byte_7:2256; CHECK-BE-OPT: # %bb.0: # %entry2257; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52258; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 72259; CHECK-BE-OPT-NEXT: blr2260;2261; CHECK-BE-O0-LABEL: insert_byte_7:2262; CHECK-BE-O0: # %bb.0: # %entry2263; CHECK-BE-O0-NEXT: mr 3, 52264; CHECK-BE-O0-NEXT: mtfprwz 0, 32265; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02266; CHECK-BE-O0-NEXT: vinsertb 2, 3, 72267; CHECK-BE-O0-NEXT: blr2268entry:2269 %vecins = insertelement <16 x i8> %a, i8 %b, i32 72270 ret <16 x i8> %vecins2271}2272 2273define <16 x i8> @insert_byte_8(<16 x i8> %a, i8 %b) {2274; CHECK-OPT-LABEL: insert_byte_8:2275; CHECK-OPT: # %bb.0: # %entry2276; CHECK-OPT-NEXT: mtvsrwz 35, 52277; CHECK-OPT-NEXT: vinsertb 2, 3, 72278; CHECK-OPT-NEXT: blr2279;2280; CHECK-O0-LABEL: insert_byte_8:2281; CHECK-O0: # %bb.0: # %entry2282; CHECK-O0-NEXT: mr 3, 52283; CHECK-O0-NEXT: mtfprwz 0, 32284; CHECK-O0-NEXT: xscpsgndp 35, 0, 02285; CHECK-O0-NEXT: vinsertb 2, 3, 72286; CHECK-O0-NEXT: blr2287;2288; CHECK-BE-OPT-LABEL: insert_byte_8:2289; CHECK-BE-OPT: # %bb.0: # %entry2290; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52291; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 82292; CHECK-BE-OPT-NEXT: blr2293;2294; CHECK-BE-O0-LABEL: insert_byte_8:2295; CHECK-BE-O0: # %bb.0: # %entry2296; CHECK-BE-O0-NEXT: mr 3, 52297; CHECK-BE-O0-NEXT: mtfprwz 0, 32298; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02299; CHECK-BE-O0-NEXT: vinsertb 2, 3, 82300; CHECK-BE-O0-NEXT: blr2301entry:2302 %vecins = insertelement <16 x i8> %a, i8 %b, i32 82303 ret <16 x i8> %vecins2304}2305 2306define <16 x i8> @insert_byte_9(<16 x i8> %a, i8 %b) {2307; CHECK-OPT-LABEL: insert_byte_9:2308; CHECK-OPT: # %bb.0: # %entry2309; CHECK-OPT-NEXT: mtvsrwz 35, 52310; CHECK-OPT-NEXT: vinsertb 2, 3, 62311; CHECK-OPT-NEXT: blr2312;2313; CHECK-O0-LABEL: insert_byte_9:2314; CHECK-O0: # %bb.0: # %entry2315; CHECK-O0-NEXT: mr 3, 52316; CHECK-O0-NEXT: mtfprwz 0, 32317; CHECK-O0-NEXT: xscpsgndp 35, 0, 02318; CHECK-O0-NEXT: vinsertb 2, 3, 62319; CHECK-O0-NEXT: blr2320;2321; CHECK-BE-OPT-LABEL: insert_byte_9:2322; CHECK-BE-OPT: # %bb.0: # %entry2323; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52324; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 92325; CHECK-BE-OPT-NEXT: blr2326;2327; CHECK-BE-O0-LABEL: insert_byte_9:2328; CHECK-BE-O0: # %bb.0: # %entry2329; CHECK-BE-O0-NEXT: mr 3, 52330; CHECK-BE-O0-NEXT: mtfprwz 0, 32331; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02332; CHECK-BE-O0-NEXT: vinsertb 2, 3, 92333; CHECK-BE-O0-NEXT: blr2334entry:2335 %vecins = insertelement <16 x i8> %a, i8 %b, i32 92336 ret <16 x i8> %vecins2337}2338 2339define <16 x i8> @insert_byte_10(<16 x i8> %a, i8 %b) {2340; CHECK-OPT-LABEL: insert_byte_10:2341; CHECK-OPT: # %bb.0: # %entry2342; CHECK-OPT-NEXT: mtvsrwz 35, 52343; CHECK-OPT-NEXT: vinsertb 2, 3, 52344; CHECK-OPT-NEXT: blr2345;2346; CHECK-O0-LABEL: insert_byte_10:2347; CHECK-O0: # %bb.0: # %entry2348; CHECK-O0-NEXT: mr 3, 52349; CHECK-O0-NEXT: mtfprwz 0, 32350; CHECK-O0-NEXT: xscpsgndp 35, 0, 02351; CHECK-O0-NEXT: vinsertb 2, 3, 52352; CHECK-O0-NEXT: blr2353;2354; CHECK-BE-OPT-LABEL: insert_byte_10:2355; CHECK-BE-OPT: # %bb.0: # %entry2356; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52357; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 102358; CHECK-BE-OPT-NEXT: blr2359;2360; CHECK-BE-O0-LABEL: insert_byte_10:2361; CHECK-BE-O0: # %bb.0: # %entry2362; CHECK-BE-O0-NEXT: mr 3, 52363; CHECK-BE-O0-NEXT: mtfprwz 0, 32364; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02365; CHECK-BE-O0-NEXT: vinsertb 2, 3, 102366; CHECK-BE-O0-NEXT: blr2367entry:2368 %vecins = insertelement <16 x i8> %a, i8 %b, i32 102369 ret <16 x i8> %vecins2370}2371 2372define <16 x i8> @insert_byte_11(<16 x i8> %a, i8 %b) {2373; CHECK-OPT-LABEL: insert_byte_11:2374; CHECK-OPT: # %bb.0: # %entry2375; CHECK-OPT-NEXT: mtvsrwz 35, 52376; CHECK-OPT-NEXT: vinsertb 2, 3, 42377; CHECK-OPT-NEXT: blr2378;2379; CHECK-O0-LABEL: insert_byte_11:2380; CHECK-O0: # %bb.0: # %entry2381; CHECK-O0-NEXT: mr 3, 52382; CHECK-O0-NEXT: mtfprwz 0, 32383; CHECK-O0-NEXT: xscpsgndp 35, 0, 02384; CHECK-O0-NEXT: vinsertb 2, 3, 42385; CHECK-O0-NEXT: blr2386;2387; CHECK-BE-OPT-LABEL: insert_byte_11:2388; CHECK-BE-OPT: # %bb.0: # %entry2389; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52390; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 112391; CHECK-BE-OPT-NEXT: blr2392;2393; CHECK-BE-O0-LABEL: insert_byte_11:2394; CHECK-BE-O0: # %bb.0: # %entry2395; CHECK-BE-O0-NEXT: mr 3, 52396; CHECK-BE-O0-NEXT: mtfprwz 0, 32397; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02398; CHECK-BE-O0-NEXT: vinsertb 2, 3, 112399; CHECK-BE-O0-NEXT: blr2400entry:2401 %vecins = insertelement <16 x i8> %a, i8 %b, i32 112402 ret <16 x i8> %vecins2403}2404 2405define <16 x i8> @insert_byte_12(<16 x i8> %a, i8 %b) {2406; CHECK-OPT-LABEL: insert_byte_12:2407; CHECK-OPT: # %bb.0: # %entry2408; CHECK-OPT-NEXT: mtvsrwz 35, 52409; CHECK-OPT-NEXT: vinsertb 2, 3, 32410; CHECK-OPT-NEXT: blr2411;2412; CHECK-O0-LABEL: insert_byte_12:2413; CHECK-O0: # %bb.0: # %entry2414; CHECK-O0-NEXT: mr 3, 52415; CHECK-O0-NEXT: mtfprwz 0, 32416; CHECK-O0-NEXT: xscpsgndp 35, 0, 02417; CHECK-O0-NEXT: vinsertb 2, 3, 32418; CHECK-O0-NEXT: blr2419;2420; CHECK-BE-OPT-LABEL: insert_byte_12:2421; CHECK-BE-OPT: # %bb.0: # %entry2422; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52423; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 122424; CHECK-BE-OPT-NEXT: blr2425;2426; CHECK-BE-O0-LABEL: insert_byte_12:2427; CHECK-BE-O0: # %bb.0: # %entry2428; CHECK-BE-O0-NEXT: mr 3, 52429; CHECK-BE-O0-NEXT: mtfprwz 0, 32430; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02431; CHECK-BE-O0-NEXT: vinsertb 2, 3, 122432; CHECK-BE-O0-NEXT: blr2433entry:2434 %vecins = insertelement <16 x i8> %a, i8 %b, i32 122435 ret <16 x i8> %vecins2436}2437 2438define <16 x i8> @insert_byte_13(<16 x i8> %a, i8 %b) {2439; CHECK-OPT-LABEL: insert_byte_13:2440; CHECK-OPT: # %bb.0: # %entry2441; CHECK-OPT-NEXT: mtvsrwz 35, 52442; CHECK-OPT-NEXT: vinsertb 2, 3, 22443; CHECK-OPT-NEXT: blr2444;2445; CHECK-O0-LABEL: insert_byte_13:2446; CHECK-O0: # %bb.0: # %entry2447; CHECK-O0-NEXT: mr 3, 52448; CHECK-O0-NEXT: mtfprwz 0, 32449; CHECK-O0-NEXT: xscpsgndp 35, 0, 02450; CHECK-O0-NEXT: vinsertb 2, 3, 22451; CHECK-O0-NEXT: blr2452;2453; CHECK-BE-OPT-LABEL: insert_byte_13:2454; CHECK-BE-OPT: # %bb.0: # %entry2455; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52456; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 132457; CHECK-BE-OPT-NEXT: blr2458;2459; CHECK-BE-O0-LABEL: insert_byte_13:2460; CHECK-BE-O0: # %bb.0: # %entry2461; CHECK-BE-O0-NEXT: mr 3, 52462; CHECK-BE-O0-NEXT: mtfprwz 0, 32463; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02464; CHECK-BE-O0-NEXT: vinsertb 2, 3, 132465; CHECK-BE-O0-NEXT: blr2466entry:2467 %vecins = insertelement <16 x i8> %a, i8 %b, i32 132468 ret <16 x i8> %vecins2469}2470 2471define <16 x i8> @insert_byte_14(<16 x i8> %a, i8 %b) {2472; CHECK-OPT-LABEL: insert_byte_14:2473; CHECK-OPT: # %bb.0: # %entry2474; CHECK-OPT-NEXT: mtvsrwz 35, 52475; CHECK-OPT-NEXT: vinsertb 2, 3, 12476; CHECK-OPT-NEXT: blr2477;2478; CHECK-O0-LABEL: insert_byte_14:2479; CHECK-O0: # %bb.0: # %entry2480; CHECK-O0-NEXT: mr 3, 52481; CHECK-O0-NEXT: mtfprwz 0, 32482; CHECK-O0-NEXT: xscpsgndp 35, 0, 02483; CHECK-O0-NEXT: vinsertb 2, 3, 12484; CHECK-O0-NEXT: blr2485;2486; CHECK-BE-OPT-LABEL: insert_byte_14:2487; CHECK-BE-OPT: # %bb.0: # %entry2488; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52489; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 142490; CHECK-BE-OPT-NEXT: blr2491;2492; CHECK-BE-O0-LABEL: insert_byte_14:2493; CHECK-BE-O0: # %bb.0: # %entry2494; CHECK-BE-O0-NEXT: mr 3, 52495; CHECK-BE-O0-NEXT: mtfprwz 0, 32496; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02497; CHECK-BE-O0-NEXT: vinsertb 2, 3, 142498; CHECK-BE-O0-NEXT: blr2499entry:2500 %vecins = insertelement <16 x i8> %a, i8 %b, i32 142501 ret <16 x i8> %vecins2502}2503 2504define <16 x i8> @insert_byte_15(<16 x i8> %a, i8 %b) {2505; CHECK-OPT-LABEL: insert_byte_15:2506; CHECK-OPT: # %bb.0: # %entry2507; CHECK-OPT-NEXT: mtvsrwz 35, 52508; CHECK-OPT-NEXT: vinsertb 2, 3, 02509; CHECK-OPT-NEXT: blr2510;2511; CHECK-O0-LABEL: insert_byte_15:2512; CHECK-O0: # %bb.0: # %entry2513; CHECK-O0-NEXT: mr 3, 52514; CHECK-O0-NEXT: mtfprwz 0, 32515; CHECK-O0-NEXT: xscpsgndp 35, 0, 02516; CHECK-O0-NEXT: vinsertb 2, 3, 02517; CHECK-O0-NEXT: blr2518;2519; CHECK-BE-OPT-LABEL: insert_byte_15:2520; CHECK-BE-OPT: # %bb.0: # %entry2521; CHECK-BE-OPT-NEXT: mtvsrwz 35, 52522; CHECK-BE-OPT-NEXT: vinsertb 2, 3, 152523; CHECK-BE-OPT-NEXT: blr2524;2525; CHECK-BE-O0-LABEL: insert_byte_15:2526; CHECK-BE-O0: # %bb.0: # %entry2527; CHECK-BE-O0-NEXT: mr 3, 52528; CHECK-BE-O0-NEXT: mtfprwz 0, 32529; CHECK-BE-O0-NEXT: xscpsgndp 35, 0, 02530; CHECK-BE-O0-NEXT: vinsertb 2, 3, 152531; CHECK-BE-O0-NEXT: blr2532entry:2533 %vecins = insertelement <16 x i8> %a, i8 %b, i32 152534 ret <16 x i8> %vecins2535}2536