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1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \2; RUN: -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \4; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE5 6define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {7entry:8; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_9; CHECK: xxswapd 0, 3510; CHECK: xxinsertw 34, 0, 1211; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_12; CHECK-BE: xxsldwi 0, 35, 35, 313; CHECK-BE: xxinsertw 34, 0, 014 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>15 ret <4 x float> %vecins16}17 18define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {19entry:20; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_21; CHECK: xxsldwi 0, 35, 35, 122; CHECK: xxinsertw 34, 0, 1223; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_24; CHECK-BE-NOT: xxsldwi25; CHECK-BE: xxinsertw 34, 35, 026 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>27 ret <4 x float> %vecins28}29 30define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {31entry:32; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_33; CHECK-NOT: xxsldwi34; CHECK: xxinsertw 34, 35, 1235; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_36; CHECK-BE: xxsldwi 0, 35, 35, 137; CHECK-BE: xxinsertw 34, 0, 038 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>39 ret <4 x float> %vecins40}41 42define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {43entry:44; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_45; CHECK: xxsldwi 0, 35, 35, 346; CHECK: xxinsertw 34, 0, 1247; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_48; CHECK-BE: xxswapd 0, 3549; CHECK-BE: xxinsertw 34, 0, 050 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>51 ret <4 x float> %vecins52}53 54define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {55entry:56; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_57; CHECK: xxswapd 0, 3558; CHECK: xxinsertw 34, 0, 859; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_60; CHECK-BE: xxsldwi 0, 35, 35, 361; CHECK-BE: xxinsertw 34, 0, 462 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>63 ret <4 x float> %vecins64}65 66define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {67entry:68; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_69; CHECK: xxsldwi 0, 35, 35, 170; CHECK: xxinsertw 34, 0, 871; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_72; CHECK-BE-NOT: xxsldwi73; CHECK-BE: xxinsertw 34, 35, 474 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>75 ret <4 x float> %vecins76}77 78define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {79entry:80; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_81; CHECK-NOT: xxsldwi82; CHECK: xxinsertw 34, 35, 883; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_84; CHECK-BE: xxsldwi 0, 35, 35, 185; CHECK-BE: xxinsertw 34, 0, 486 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>87 ret <4 x float> %vecins88}89 90define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {91entry:92; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_93; CHECK: xxsldwi 0, 35, 35, 394; CHECK: xxinsertw 34, 0, 895; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_96; CHECK-BE: xxswapd 0, 3597; CHECK-BE: xxinsertw 34, 0, 498 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>99 ret <4 x float> %vecins100}101 102define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {103entry:104; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_105; CHECK: xxswapd 0, 35106; CHECK: xxinsertw 34, 0, 4107; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_108; CHECK-BE: xxsldwi 0, 35, 35, 3109; CHECK-BE: xxinsertw 34, 0, 8110 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>111 ret <4 x float> %vecins112}113 114define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {115entry:116; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_117; CHECK: xxsldwi 0, 35, 35, 1118; CHECK: xxinsertw 34, 0, 4119; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_120; CHECK-BE-NOT: xxsldwi121; CHECK-BE: xxinsertw 34, 35, 8122 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>123 ret <4 x float> %vecins124}125 126define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {127entry:128; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_129; CHECK-NOT: xxsldwi130; CHECK: xxinsertw 34, 35, 4131; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_132; CHECK-BE: xxsldwi 0, 35, 35, 1133; CHECK-BE: xxinsertw 34, 0, 8134 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>135 ret <4 x float> %vecins136}137 138define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {139entry:140; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_141; CHECK: xxsldwi 0, 35, 35, 3142; CHECK: xxinsertw 34, 0, 4143; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_144; CHECK-BE: xxswapd 0, 35145; CHECK-BE: xxinsertw 34, 0, 8146 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>147 ret <4 x float> %vecins148}149 150define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {151entry:152; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_153; CHECK: xxswapd 0, 35154; CHECK: xxinsertw 34, 0, 0155; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_156; CHECK-BE: xxsldwi 0, 35, 35, 3157; CHECK-BE: xxinsertw 34, 0, 12158 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>159 ret <4 x float> %vecins160}161 162define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {163entry:164; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_165; CHECK: xxsldwi 0, 35, 35, 1166; CHECK: xxinsertw 34, 0, 0167; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_168; CHECK-BE-NOT: xxsldwi169; CHECK-BE: xxinsertw 34, 35, 12170 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>171 ret <4 x float> %vecins172}173 174define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {175entry:176; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_177; CHECK-NOT: xxsldwi178; CHECK: xxinsertw 34, 35, 0179; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_180; CHECK-BE: xxsldwi 0, 35, 35, 1181; CHECK-BE: xxinsertw 34, 0, 12182 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>183 ret <4 x float> %vecins184}185 186define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {187entry:188; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_189; CHECK: xxsldwi 0, 35, 35, 3190; CHECK: xxinsertw 34, 0, 0191; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_192; CHECK-BE: xxswapd 0, 35193; CHECK-BE: xxinsertw 34, 0, 12194 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>195 ret <4 x float> %vecins196}197 198define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {199entry:200; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_201; CHECK: xxswapd 0, 35202; CHECK: xxinsertw 34, 0, 12203; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_204; CHECK-BE: xxsldwi 0, 35, 35, 3205; CHECK-BE: xxinsertw 34, 0, 0206 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>207 ret <4 x i32> %vecins208}209 210define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {211entry:212; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_213; CHECK: xxsldwi 0, 35, 35, 1214; CHECK: xxinsertw 34, 0, 12215; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_216; CHECK-BE-NOT: xxsldwi217; CHECK-BE: xxinsertw 34, 35, 0218 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 1, i32 2, i32 3>219 ret <4 x i32> %vecins220}221 222define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {223entry:224; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_225; CHECK-NOT: xxsldwi226; CHECK: xxinsertw 34, 35, 12227; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_228; CHECK-BE: xxsldwi 0, 35, 35, 1229; CHECK-BE: xxinsertw 34, 0, 0230 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 6, i32 1, i32 2, i32 3>231 ret <4 x i32> %vecins232}233 234define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {235entry:236; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_237; CHECK: xxsldwi 0, 35, 35, 3238; CHECK: xxinsertw 34, 0, 12239; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_240; CHECK-BE: xxswapd 0, 35241; CHECK-BE: xxinsertw 34, 0, 0242 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 7, i32 1, i32 2, i32 3>243 ret <4 x i32> %vecins244}245 246define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {247entry:248; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_249; CHECK: xxswapd 0, 35250; CHECK: xxinsertw 34, 0, 8251; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_252; CHECK-BE: xxsldwi 0, 35, 35, 3253; CHECK-BE: xxinsertw 34, 0, 4254 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 3>255 ret <4 x i32> %vecins256}257 258define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {259entry:260; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_261; CHECK: xxsldwi 0, 35, 35, 1262; CHECK: xxinsertw 34, 0, 8263; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_264; CHECK-BE-NOT: xxsldwi265; CHECK-BE: xxinsertw 34, 35, 4266 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>267 ret <4 x i32> %vecins268}269 270define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {271entry:272; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_273; CHECK-NOT: xxsldwi274; CHECK: xxinsertw 34, 35, 8275; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_276; CHECK-BE: xxsldwi 0, 35, 35, 1277; CHECK-BE: xxinsertw 34, 0, 4278 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 6, i32 2, i32 3>279 ret <4 x i32> %vecins280}281 282define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {283entry:284; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_285; CHECK: xxsldwi 0, 35, 35, 3286; CHECK: xxinsertw 34, 0, 8287; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_288; CHECK-BE: xxswapd 0, 35289; CHECK-BE: xxinsertw 34, 0, 4290 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>291 ret <4 x i32> %vecins292}293 294define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {295entry:296; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_297; CHECK: xxswapd 0, 35298; CHECK: xxinsertw 34, 0, 4299; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_300; CHECK-BE: xxsldwi 0, 35, 35, 3301; CHECK-BE: xxinsertw 34, 0, 8302 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 3>303 ret <4 x i32> %vecins304}305 306define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {307entry:308; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_309; CHECK: xxsldwi 0, 35, 35, 1310; CHECK: xxinsertw 34, 0, 4311; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_312; CHECK-BE-NOT: xxsldwi313; CHECK-BE: xxinsertw 34, 35, 8314 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>315 ret <4 x i32> %vecins316}317 318define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {319entry:320; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_321; CHECK-NOT: xxsldwi322; CHECK: xxinsertw 34, 35, 4323; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_324; CHECK-BE: xxsldwi 0, 35, 35, 1325; CHECK-BE: xxinsertw 34, 0, 8326 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>327 ret <4 x i32> %vecins328}329 330define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {331entry:332; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_333; CHECK: xxsldwi 0, 35, 35, 3334; CHECK: xxinsertw 34, 0, 4335; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_336; CHECK-BE: xxswapd 0, 35337; CHECK-BE: xxinsertw 34, 0, 8338 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 7, i32 3>339 ret <4 x i32> %vecins340}341 342define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {343entry:344; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_345; CHECK: xxswapd 0, 35346; CHECK: xxinsertw 34, 0, 0347; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_348; CHECK-BE: xxsldwi 0, 35, 35, 3349; CHECK-BE: xxinsertw 34, 0, 12350 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 4>351 ret <4 x i32> %vecins352}353 354define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {355entry:356; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_357; CHECK: xxsldwi 0, 35, 35, 1358; CHECK: xxinsertw 34, 0, 0359; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_360; CHECK-BE-NOT: xxsldwi361; CHECK-BE: xxinsertw 34, 35, 12362 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 5>363 ret <4 x i32> %vecins364}365 366define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {367entry:368; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_369; CHECK-NOT: xxsldwi370; CHECK: xxinsertw 34, 35, 0371; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_372; CHECK-BE: xxsldwi 0, 35, 35, 1373; CHECK-BE: xxinsertw 34, 0, 12374 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 6>375 ret <4 x i32> %vecins376}377 378define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_(<4 x i32> %a, <4 x i32> %b) {379entry:380; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_381; CHECK: xxsldwi 0, 35, 35, 3382; CHECK: xxinsertw 34, 0, 0383; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_384; CHECK-BE: xxswapd 0, 35385; CHECK-BE: xxinsertw 34, 0, 12386 %vecins = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>387 ret <4 x i32> %vecins388}389 390define float @_Z13testUiToFpExtILj0EEfDv4_j(<4 x i32> %a) {391entry:392; CHECK-LABEL: _Z13testUiToFpExtILj0EEfDv4_j393; CHECK: xxextractuw 0, 34, 12394; CHECK: xscvuxdsp 1, 0395; CHECK-BE-LABEL: _Z13testUiToFpExtILj0EEfDv4_j396; CHECK-BE: xxextractuw 0, 34, 0397; CHECK-BE: xscvuxdsp 1, 0398 %vecext = extractelement <4 x i32> %a, i32 0399 %conv = uitofp i32 %vecext to float400 ret float %conv401}402 403define float @_Z13testUiToFpExtILj1EEfDv4_j(<4 x i32> %a) {404entry:405; CHECK-LABEL: _Z13testUiToFpExtILj1EEfDv4_j406; CHECK: xxextractuw 0, 34, 8407; CHECK: xscvuxdsp 1, 0408; CHECK-BE-LABEL: _Z13testUiToFpExtILj1EEfDv4_j409; CHECK-BE: xxextractuw 0, 34, 4410; CHECK-BE: xscvuxdsp 1, 0411 %vecext = extractelement <4 x i32> %a, i32 1412 %conv = uitofp i32 %vecext to float413 ret float %conv414}415 416define float @_Z13testUiToFpExtILj2EEfDv4_j(<4 x i32> %a) {417entry:418; CHECK-LABEL: _Z13testUiToFpExtILj2EEfDv4_j419; CHECK: xxextractuw 0, 34, 4420; CHECK: xscvuxdsp 1, 0421; CHECK-BE-LABEL: _Z13testUiToFpExtILj2EEfDv4_j422; CHECK-BE: xxextractuw 0, 34, 8423; CHECK-BE: xscvuxdsp 1, 0424 %vecext = extractelement <4 x i32> %a, i32 2425 %conv = uitofp i32 %vecext to float426 ret float %conv427}428 429define float @_Z13testUiToFpExtILj3EEfDv4_j(<4 x i32> %a) {430entry:431; CHECK-LABEL: _Z13testUiToFpExtILj3EEfDv4_j432; CHECK: xxextractuw 0, 34, 0433; CHECK: xscvuxdsp 1, 0434; CHECK-BE-LABEL: _Z13testUiToFpExtILj3EEfDv4_j435; CHECK-BE: xxextractuw 0, 34, 12436; CHECK-BE: xscvuxdsp 1, 0437 %vecext = extractelement <4 x i32> %a, i32 3438 %conv = uitofp i32 %vecext to float439 ret float %conv440}441 442; Verify we generate optimal code for unsigned vector int elem extract followed443; by conversion to double444 445define double @conv2dlbTestui0(<4 x i32> %a) {446entry:447; CHECK-LABEL: conv2dlbTestui0448; CHECK: xxextractuw [[SW:[0-9]+]], 34, 12449; CHECK: xscvuxddp 1, [[SW]]450; CHECK-BE-LABEL: conv2dlbTestui0451; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 0452; CHECK-BE: xscvuxddp 1, [[CP]]453 %0 = extractelement <4 x i32> %a, i32 0454 %1 = uitofp i32 %0 to double455 ret double %1456}457 458define double @conv2dlbTestui1(<4 x i32> %a) {459entry:460; CHECK-LABEL: conv2dlbTestui1461; CHECK: xxextractuw [[SW:[0-9]+]], 34, 8462; CHECK: xscvuxddp 1, [[SW]]463; CHECK-BE-LABEL: conv2dlbTestui1464; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 4465; CHECK-BE: xscvuxddp 1, [[CP]]466 %0 = extractelement <4 x i32> %a, i32 1467 %1 = uitofp i32 %0 to double468 ret double %1469}470 471define double @conv2dlbTestui2(<4 x i32> %a) {472entry:473; CHECK-LABEL: conv2dlbTestui2474; CHECK: xxextractuw [[SW:[0-9]+]], 34, 4475; CHECK: xscvuxddp 1, [[SW]]476; CHECK-BE-LABEL: conv2dlbTestui2477; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 8478; CHECK-BE: xscvuxddp 1, [[CP]]479 %0 = extractelement <4 x i32> %a, i32 2480 %1 = uitofp i32 %0 to double481 ret double %1482}483 484define double @conv2dlbTestui3(<4 x i32> %a) {485entry:486; CHECK-LABEL: conv2dlbTestui3487; CHECK: xxextractuw [[SW:[0-9]+]], 34, 0488; CHECK: xscvuxddp 1, [[SW]]489; CHECK-BE-LABEL: conv2dlbTestui3490; CHECK-BE: xxextractuw [[CP:[0-9]+]], 34, 12491; CHECK-BE: xscvuxddp 1, [[CP]]492 %0 = extractelement <4 x i32> %a, i32 3493 %1 = uitofp i32 %0 to double494 ret double %1495}496 497; verify we don't crash for variable elem extract498define double @conv2dlbTestuiVar(<4 x i32> %a, i32 zeroext %elem) {499entry:500 %vecext = extractelement <4 x i32> %a, i32 %elem501 %conv = uitofp i32 %vecext to double502 ret double %conv503}504 505define <4 x float> @_Z10testInsEltILj0EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {506entry:507; CHECK-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_508; CHECK: xscvdpspn 0, 1509; CHECK: xxinsertw 34, 0, 12510; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_ffET0_S1_T1_511; CHECK-BE: xscvdpspn 0, 1512; CHECK-BE: xxinsertw 34, 0, 0513 %vecins = insertelement <4 x float> %a, float %b, i32 0514 ret <4 x float> %vecins515}516 517define <4 x float> @_Z10testInsEltILj1EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {518entry:519; CHECK-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_520; CHECK: xscvdpspn 0, 1521; CHECK: xxinsertw 34, 0, 8522; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_ffET0_S1_T1_523; CHECK-BE: xscvdpspn 0, 1524; CHECK-BE: xxinsertw 34, 0, 4525 %vecins = insertelement <4 x float> %a, float %b, i32 1526 ret <4 x float> %vecins527}528 529define <4 x float> @_Z10testInsEltILj2EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {530entry:531; CHECK-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_532; CHECK: xscvdpspn 0, 1533; CHECK: xxinsertw 34, 0, 4534; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_ffET0_S1_T1_535; CHECK-BE: xscvdpspn 0, 1536; CHECK-BE: xxinsertw 34, 0, 8537 %vecins = insertelement <4 x float> %a, float %b, i32 2538 ret <4 x float> %vecins539}540 541define <4 x float> @_Z10testInsEltILj3EDv4_ffET0_S1_T1_(<4 x float> %a, float %b) {542entry:543; CHECK-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_544; CHECK: xscvdpspn 0, 1545; CHECK: xxinsertw 34, 0, 0546; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_ffET0_S1_T1_547; CHECK-BE: xscvdpspn 0, 1548; CHECK-BE: xxinsertw 34, 0, 12549 %vecins = insertelement <4 x float> %a, float %b, i32 3550 ret <4 x float> %vecins551}552 553define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {554entry:555; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_556; CHECK: mtfprwz 0, 5557; CHECK: xxinsertw 34, 0, 12558; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_559; CHECK-BE: mtfprwz 0, 5560; CHECK-BE: xxinsertw 34, 0, 0561 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0562 ret <4 x i32> %vecins563}564 565define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {566entry:567; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_568; CHECK: mtfprwz 0, 5569; CHECK: xxinsertw 34, 0, 8570; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_571; CHECK-BE: mtfprwz 0, 5572; CHECK-BE: xxinsertw 34, 0, 4573 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1574 ret <4 x i32> %vecins575}576 577define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {578entry:579; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_580; CHECK: mtfprwz 0, 5581; CHECK: xxinsertw 34, 0, 4582; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_583; CHECK-BE: mtfprwz 0, 5584; CHECK-BE: xxinsertw 34, 0, 8585 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2586 ret <4 x i32> %vecins587}588 589define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {590entry:591; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_592; CHECK: mtfprwz 0, 5593; CHECK: xxinsertw 34, 0, 0594; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_595; CHECK-BE: mtfprwz 0, 5596; CHECK-BE: xxinsertw 34, 0, 12597 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3598 ret <4 x i32> %vecins599}600 601define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {602entry:603; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_604; CHECK: xxswapd 0, 35605; CHECK: xxinsertw 34, 0, 12606; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_607; CHECK-BE: xxsldwi 0, 35, 35, 3608; CHECK-BE: xxinsertw 34, 0, 0609 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>610 ret <4 x float> %vecins611}612 613define <4 x float> @_Z7testInsILj0ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {614entry:615; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_616; CHECK: xxsldwi 0, 35, 35, 1617; CHECK: xxinsertw 34, 0, 12618; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_fET1_S1_S1_619; CHECK-BE-NOT: xxsldwi620; CHECK-BE: xxinsertw 34, 35, 0621 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>622 ret <4 x float> %vecins623}624 625define <4 x float> @_Z7testInsILj0ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {626entry:627; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_628; CHECK-NOT: xxsldwi629; CHECK: xxinsertw 34, 35, 12630; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_fET1_S1_S1_631; CHECK-BE: xxsldwi 0, 35, 35, 1632; CHECK-BE: xxinsertw 34, 0, 0633 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>634 ret <4 x float> %vecins635}636 637define <4 x float> @_Z7testInsILj0ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {638entry:639; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_640; CHECK: xxsldwi 0, 35, 35, 3641; CHECK: xxinsertw 34, 0, 12642; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_fET1_S1_S1_643; CHECK-BE: xxswapd 0, 35644; CHECK-BE: xxinsertw 34, 0, 0645 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>646 ret <4 x float> %vecins647}648 649define <4 x float> @_Z7testInsILj1ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {650entry:651; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_652; CHECK: xxswapd 0, 35653; CHECK: xxinsertw 34, 0, 8654; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_fET1_S1_S1_655; CHECK-BE: xxsldwi 0, 35, 35, 3656; CHECK-BE: xxinsertw 34, 0, 4657 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>658 ret <4 x float> %vecins659}660 661define <4 x float> @_Z7testInsILj1ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {662entry:663; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_664; CHECK: xxsldwi 0, 35, 35, 1665; CHECK: xxinsertw 34, 0, 8666; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_fET1_S1_S1_667; CHECK-BE-NOT: xxsldwi668; CHECK-BE: xxinsertw 34, 35, 4669 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>670 ret <4 x float> %vecins671}672 673define <4 x float> @_Z7testInsILj1ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {674entry:675; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_676; CHECK-NOT: xxsldwi677; CHECK: xxinsertw 34, 35, 8678; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_fET1_S1_S1_679; CHECK-BE: xxsldwi 0, 35, 35, 1680; CHECK-BE: xxinsertw 34, 0, 4681 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>682 ret <4 x float> %vecins683}684 685define <4 x float> @_Z7testInsILj1ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {686entry:687; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_688; CHECK: xxsldwi 0, 35, 35, 3689; CHECK: xxinsertw 34, 0, 8690; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_fET1_S1_S1_691; CHECK-BE: xxswapd 0, 35692; CHECK-BE: xxinsertw 34, 0, 4693 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>694 ret <4 x float> %vecins695}696 697define <4 x float> @_Z7testInsILj2ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {698entry:699; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_700; CHECK: xxswapd 0, 35701; CHECK: xxinsertw 34, 0, 4702; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_fET1_S1_S1_703; CHECK-BE: xxsldwi 0, 35, 35, 3704; CHECK-BE: xxinsertw 34, 0, 8705 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>706 ret <4 x float> %vecins707}708 709define <4 x float> @_Z7testInsILj2ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {710entry:711; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_712; CHECK: xxsldwi 0, 35, 35, 1713; CHECK: xxinsertw 34, 0, 4714; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_fET1_S1_S1_715; CHECK-BE-NOT: xxsldwi716; CHECK-BE: xxinsertw 34, 35, 8717 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>718 ret <4 x float> %vecins719}720 721define <4 x float> @_Z7testInsILj2ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {722entry:723; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_724; CHECK-NOT: xxsldwi725; CHECK: xxinsertw 34, 35, 4726; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_fET1_S1_S1_727; CHECK-BE: xxsldwi 0, 35, 35, 1728; CHECK-BE: xxinsertw 34, 0, 8729 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>730 ret <4 x float> %vecins731}732 733define <4 x float> @_Z7testInsILj2ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {734entry:735; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_736; CHECK: xxsldwi 0, 35, 35, 3737; CHECK: xxinsertw 34, 0, 4738; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_fET1_S1_S1_739; CHECK-BE: xxswapd 0, 35740; CHECK-BE: xxinsertw 34, 0, 8741 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>742 ret <4 x float> %vecins743}744 745define <4 x float> @_Z7testInsILj3ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {746entry:747; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_748; CHECK: xxswapd 0, 35749; CHECK: xxinsertw 34, 0, 0750; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_fET1_S1_S1_751; CHECK-BE: xxsldwi 0, 35, 35, 3752; CHECK-BE: xxinsertw 34, 0, 12753 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>754 ret <4 x float> %vecins755}756 757define <4 x float> @_Z7testInsILj3ELj1EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {758entry:759; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_760; CHECK: xxsldwi 0, 35, 35, 1761; CHECK: xxinsertw 34, 0, 0762; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_fET1_S1_S1_763; CHECK-BE-NOT: xxsldwi764; CHECK-BE: xxinsertw 34, 35, 12765 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>766 ret <4 x float> %vecins767}768 769define <4 x float> @_Z7testInsILj3ELj2EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {770entry:771; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_772; CHECK-NOT: xxsldwi773; CHECK: xxinsertw 34, 35, 0774; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_fET1_S1_S1_775; CHECK-BE: xxsldwi 0, 35, 35, 1776; CHECK-BE: xxinsertw 34, 0, 12777 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>778 ret <4 x float> %vecins779}780 781define <4 x float> @_Z7testInsILj3ELj3EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {782entry:783; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_784; CHECK: xxsldwi 0, 35, 35, 3785; CHECK: xxinsertw 34, 0, 0786; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_fET1_S1_S1_787; CHECK-BE: xxswapd 0, 35788; CHECK-BE: xxinsertw 34, 0, 12789 %vecins = shufflevector <4 x float> %b, <4 x float> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>790 ret <4 x float> %vecins791}792 793define <4 x i32> @_Z7testInsILj0ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {794entry:795; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_796; CHECK: xxswapd 0, 35797; CHECK: xxinsertw 34, 0, 12798; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_jET1_S1_S1_799; CHECK-BE: xxsldwi 0, 35, 35, 3800; CHECK-BE: xxinsertw 34, 0, 0801 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 0, i32 5, i32 6, i32 7>802 ret <4 x i32> %vecins803}804 805define <4 x i32> @_Z7testInsILj0ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {806entry:807; CHECK-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_808; CHECK: xxsldwi 0, 35, 35, 1809; CHECK: xxinsertw 34, 0, 12810; CHECK-BE-LABEL: _Z7testInsILj0ELj1EDv4_jET1_S1_S1_811; CHECK-BE-NOT: xxsldwi812; CHECK-BE: xxinsertw 34, 35, 0813 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 6, i32 7>814 ret <4 x i32> %vecins815}816 817define <4 x i32> @_Z7testInsILj0ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {818entry:819; CHECK-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_820; CHECK-NOT: xxsldwi821; CHECK: xxinsertw 34, 35, 12822; CHECK-BE-LABEL: _Z7testInsILj0ELj2EDv4_jET1_S1_S1_823; CHECK-BE: xxsldwi 0, 35, 35, 1824; CHECK-BE: xxinsertw 34, 0, 0825 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 2, i32 5, i32 6, i32 7>826 ret <4 x i32> %vecins827}828 829define <4 x i32> @_Z7testInsILj0ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {830entry:831; CHECK-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_832; CHECK: xxsldwi 0, 35, 35, 3833; CHECK: xxinsertw 34, 0, 12834; CHECK-BE-LABEL: _Z7testInsILj0ELj3EDv4_jET1_S1_S1_835; CHECK-BE: xxswapd 0, 35836; CHECK-BE: xxinsertw 34, 0, 0837 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 3, i32 5, i32 6, i32 7>838 ret <4 x i32> %vecins839}840 841define <4 x i32> @_Z7testInsILj1ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {842entry:843; CHECK-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_844; CHECK: xxswapd 0, 35845; CHECK: xxinsertw 34, 0, 8846; CHECK-BE-LABEL: _Z7testInsILj1ELj0EDv4_jET1_S1_S1_847; CHECK-BE: xxsldwi 0, 35, 35, 3848; CHECK-BE: xxinsertw 34, 0, 4849 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 0, i32 6, i32 7>850 ret <4 x i32> %vecins851}852 853define <4 x i32> @_Z7testInsILj1ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {854entry:855; CHECK-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_856; CHECK: xxsldwi 0, 35, 35, 1857; CHECK: xxinsertw 34, 0, 8858; CHECK-BE-LABEL: _Z7testInsILj1ELj1EDv4_jET1_S1_S1_859; CHECK-BE-NOT: xxsldwi860; CHECK-BE: xxinsertw 34, 35, 4861 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 6, i32 7>862 ret <4 x i32> %vecins863}864 865define <4 x i32> @_Z7testInsILj1ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {866entry:867; CHECK-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_868; CHECK-NOT: xxsldwi869; CHECK: xxinsertw 34, 35, 8870; CHECK-BE-LABEL: _Z7testInsILj1ELj2EDv4_jET1_S1_S1_871; CHECK-BE: xxsldwi 0, 35, 35, 1872; CHECK-BE: xxinsertw 34, 0, 4873 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 2, i32 6, i32 7>874 ret <4 x i32> %vecins875}876 877define <4 x i32> @_Z7testInsILj1ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {878entry:879; CHECK-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_880; CHECK: xxsldwi 0, 35, 35, 3881; CHECK: xxinsertw 34, 0, 8882; CHECK-BE-LABEL: _Z7testInsILj1ELj3EDv4_jET1_S1_S1_883; CHECK-BE: xxswapd 0, 35884; CHECK-BE: xxinsertw 34, 0, 4885 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 3, i32 6, i32 7>886 ret <4 x i32> %vecins887}888 889define <4 x i32> @_Z7testInsILj2ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {890entry:891; CHECK-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_892; CHECK: xxswapd 0, 35893; CHECK: xxinsertw 34, 0, 4894; CHECK-BE-LABEL: _Z7testInsILj2ELj0EDv4_jET1_S1_S1_895; CHECK-BE: xxsldwi 0, 35, 35, 3896; CHECK-BE: xxinsertw 34, 0, 8897 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 0, i32 7>898 ret <4 x i32> %vecins899}900 901define <4 x i32> @_Z7testInsILj2ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {902entry:903; CHECK-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_904; CHECK: xxsldwi 0, 35, 35, 1905; CHECK: xxinsertw 34, 0, 4906; CHECK-BE-LABEL: _Z7testInsILj2ELj1EDv4_jET1_S1_S1_907; CHECK-BE-NOT: xxsldwi908; CHECK-BE: xxinsertw 34, 35, 8909 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 1, i32 7>910 ret <4 x i32> %vecins911}912 913define <4 x i32> @_Z7testInsILj2ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {914entry:915; CHECK-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_916; CHECK-NOT: xxsldwi917; CHECK: xxinsertw 34, 35, 4918; CHECK-BE-LABEL: _Z7testInsILj2ELj2EDv4_jET1_S1_S1_919; CHECK-BE: xxsldwi 0, 35, 35, 1920; CHECK-BE: xxinsertw 34, 0, 8921 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 2, i32 7>922 ret <4 x i32> %vecins923}924 925define <4 x i32> @_Z7testInsILj2ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {926entry:927; CHECK-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_928; CHECK: xxsldwi 0, 35, 35, 3929; CHECK: xxinsertw 34, 0, 4930; CHECK-BE-LABEL: _Z7testInsILj2ELj3EDv4_jET1_S1_S1_931; CHECK-BE: xxswapd 0, 35932; CHECK-BE: xxinsertw 34, 0, 8933 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 3, i32 7>934 ret <4 x i32> %vecins935}936 937define <4 x i32> @_Z7testInsILj3ELj0EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {938entry:939; CHECK-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_940; CHECK: xxswapd 0, 35941; CHECK: xxinsertw 34, 0, 0942; CHECK-BE-LABEL: _Z7testInsILj3ELj0EDv4_jET1_S1_S1_943; CHECK-BE: xxsldwi 0, 35, 35, 3944; CHECK-BE: xxinsertw 34, 0, 12945 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 0>946 ret <4 x i32> %vecins947}948 949define <4 x i32> @_Z7testInsILj3ELj1EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {950entry:951; CHECK-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_952; CHECK: xxsldwi 0, 35, 35, 1953; CHECK: xxinsertw 34, 0, 0954; CHECK-BE-LABEL: _Z7testInsILj3ELj1EDv4_jET1_S1_S1_955; CHECK-BE-NOT: xxsldwi956; CHECK-BE: xxinsertw 34, 35, 12957 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 1>958 ret <4 x i32> %vecins959}960 961define <4 x i32> @_Z7testInsILj3ELj2EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {962entry:963; CHECK-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_964; CHECK-NOT: xxsldwi965; CHECK: xxinsertw 34, 35, 0966; CHECK-BE-LABEL: _Z7testInsILj3ELj2EDv4_jET1_S1_S1_967; CHECK-BE: xxsldwi 0, 35, 35, 1968; CHECK-BE: xxinsertw 34, 0, 12969 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 2>970 ret <4 x i32> %vecins971}972 973define <4 x i32> @_Z7testInsILj3ELj3EDv4_jET1_S1_S1_r(<4 x i32> %a, <4 x i32> %b) {974entry:975; CHECK-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_976; CHECK: xxsldwi 0, 35, 35, 3977; CHECK: xxinsertw 34, 0, 0978; CHECK-BE-LABEL: _Z7testInsILj3ELj3EDv4_jET1_S1_S1_979; CHECK-BE: xxswapd 0, 35980; CHECK-BE: xxinsertw 34, 0, 12981 %vecins = shufflevector <4 x i32> %b, <4 x i32> %a, <4 x i32> <i32 4, i32 5, i32 6, i32 3>982 ret <4 x i32> %vecins983}984define <4 x float> @testSameVecEl0BE(<4 x float> %a) {985entry:986; CHECK-BE-LABEL: testSameVecEl0BE987; CHECK-BE: xxinsertw 34, 34, 0988 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 5, i32 1, i32 2, i32 3>989 ret <4 x float> %vecins990}991define <4 x float> @testSameVecEl2BE(<4 x float> %a) {992entry:993; CHECK-BE-LABEL: testSameVecEl2BE994; CHECK-BE: xxinsertw 34, 34, 8995 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 5, i32 3>996 ret <4 x float> %vecins997}998define <4 x float> @testSameVecEl3BE(<4 x float> %a) {999entry:1000; CHECK-BE-LABEL: testSameVecEl3BE1001; CHECK-BE: xxinsertw 34, 34, 121002 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 5>1003 ret <4 x float> %vecins1004}1005define <4 x float> @testSameVecEl0LE(<4 x float> %a) {1006entry:1007; CHECK-LABEL: testSameVecEl0LE1008; CHECK: xxinsertw 34, 34, 121009 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 6, i32 1, i32 2, i32 3>1010 ret <4 x float> %vecins1011}1012define <4 x float> @testSameVecEl1LE(<4 x float> %a) {1013entry:1014; CHECK-LABEL: testSameVecEl1LE1015; CHECK: xxinsertw 34, 34, 81016 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>1017 ret <4 x float> %vecins1018}1019define <4 x float> @testSameVecEl3LE(<4 x float> %a) {1020entry:1021; CHECK-LABEL: testSameVecEl3LE1022; CHECK: xxinsertw 34, 34, 01023 %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>1024 ret <4 x float> %vecins1025}1026define <4 x float> @insertVarF(<4 x float> %a, float %f, i32 %el) {1027entry:1028; CHECK-LABEL: insertVarF1029; CHECK: stfsx 1,1030; CHECK: lxv1031; CHECK-BE-LABEL: insertVarF1032; CHECK-BE: stfsx 1,1033; CHECK-BE: lxv1034 %vecins = insertelement <4 x float> %a, float %f, i32 %el1035 ret <4 x float> %vecins1036}1037define <4 x i32> @insertVarI(<4 x i32> %a, i32 %i, i32 %el) {1038entry:1039; CHECK-LABEL: insertVarI1040; CHECK: stwx1041; CHECK: lxv1042; CHECK-BE-LABEL: insertVarI1043; CHECK-BE: stwx1044; CHECK-BE: lxv1045 %vecins = insertelement <4 x i32> %a, i32 %i, i32 %el1046 ret <4 x i32> %vecins1047}1048define <4 x i32> @intrinsicInsertTest(<4 x i32> %a, <2 x i64> %b) {1049entry:1050; CHECK-LABEL:intrinsicInsertTest1051; CHECK: xxinsertw 34, 35, 31052; CHECK: blr1053 %ans = tail call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> %a, <2 x i64> %b, i32 3)1054 ret <4 x i32> %ans1055}1056declare <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>, <2 x i64>, i32)1057define <2 x i64> @intrinsicExtractTest(<2 x i64> %a) {1058entry:1059; CHECK-LABEL: intrinsicExtractTest1060; CHECK: xxextractuw 34, 34, 51061; CHECK: blr1062 %ans = tail call <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64> %a, i32 5)1063 ret <2 x i64> %ans1064}1065declare <2 x i64> @llvm.ppc.vsx.xxextractuw(<2 x i64>, i32)1066