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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s4 5; The purpose of this test is to check the call protocols for the situation6; where the caller has PC Relative disabled, the callee has PC Relative7; enabled and both functions are in the same file.8; Note that the callee does not know if it clobbers the TOC because it9; contains an external call to @externalFunc.10 11@global = external local_unnamed_addr global i32, align 412 13define dso_local signext i32 @callee(i32 signext %a) local_unnamed_addr #0 {14; CHECK-LABEL: callee:15; CHECK: .localentry callee, 116; CHECK-NEXT: # %bb.0: # %entry17; CHECK-NEXT: mflr r018; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill19; CHECK-NEXT: std r0, 16(r1)20; CHECK-NEXT: stdu r1, -48(r1)21; CHECK-NEXT: mr r30, r322; CHECK-NEXT: bl externalFunc@notoc23; CHECK-NEXT: add r3, r3, r3024; CHECK-NEXT: extsw r3, r325; CHECK-NEXT: addi r1, r1, 4826; CHECK-NEXT: ld r0, 16(r1)27; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload28; CHECK-NEXT: mtlr r029; CHECK-NEXT: blr30entry:31 %call = tail call signext i32 @externalFunc(i32 signext %a) #332 %add = add nsw i32 %call, %a33 ret i32 %add34}35 36declare signext i32 @externalFunc(i32 signext) local_unnamed_addr #137 38define dso_local void @caller(i32 signext %a) local_unnamed_addr #2 {39; CHECK-LABEL: caller:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: mflr r042; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill43; CHECK-NEXT: std r0, 16(r1)44; CHECK-NEXT: stdu r1, -48(r1)45; CHECK-NEXT: addis r4, r2, .LC0@toc@ha46; CHECK-NEXT: ld r30, .LC0@toc@l(r4)47; CHECK-NEXT: lwz r4, 0(r30)48; CHECK-NEXT: add r3, r4, r349; CHECK-NEXT: extsw r3, r350; CHECK-NEXT: bl callee51; CHECK-NEXT: nop52; CHECK-NEXT: mullw r3, r3, r353; CHECK-NEXT: stw r3, 0(r30)54; CHECK-NEXT: addi r1, r1, 4855; CHECK-NEXT: ld r0, 16(r1)56; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload57; CHECK-NEXT: mtlr r058; CHECK-NEXT: blr59entry:60 %0 = load i32, ptr @global, align 461 %add = add nsw i32 %0, %a62 %call = tail call signext i32 @callee(i32 signext %add)63 %mul = mul nsw i32 %call, %call64 store i32 %mul, ptr @global, align 465 ret void66}67 68define dso_local signext i32 @tail_caller(i32 signext %a) local_unnamed_addr #2 {69; CHECK-LABEL: tail_caller:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: mflr r072; CHECK-NEXT: std r0, 16(r1)73; CHECK-NEXT: stdu r1, -32(r1)74; CHECK-NEXT: addis r4, r2, .LC0@toc@ha75; CHECK-NEXT: ld r4, .LC0@toc@l(r4)76; CHECK-NEXT: lwz r4, 0(r4)77; CHECK-NEXT: add r3, r4, r378; CHECK-NEXT: extsw r3, r379; CHECK-NEXT: bl callee80; CHECK-NEXT: nop81; CHECK-NEXT: addi r1, r1, 3282; CHECK-NEXT: ld r0, 16(r1)83; CHECK-NEXT: mtlr r084; CHECK-NEXT: blr85entry:86 %0 = load i32, ptr @global, align 487 %add = add nsw i32 %0, %a88 %call = tail call signext i32 @callee(i32 signext %add)89 ret i32 %call90}91 92 93; Left the target features in this test because it is important that caller has94; -pcrelative-memops while callee has +pcrelative-memops95attributes #0 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-spe" }96attributes #1 = { "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+pcrelative-memops,+power8-vector,+power9-vector,+vsx,-htm,-spe" }97attributes #2 = { nounwind "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+power9-vector,+vsx,-htm,-pcrelative-memops,-spe" }98attributes #3 = { nounwind }99