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1; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -O1 -code-model=medium <%s | FileCheck %s3 4; Test peephole optimization for medium code model (32-bit TOC offsets)5; for loading and storing small offsets within aligned values.6 7target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"8target triple = "powerpc64-unknown-linux-gnu"9 10%struct.b4 = type<{ i8, i8, i8, i8 }>11%struct.h2 = type<{ i16, i16 }>12 13%struct.b8 = type<{ i8, i8, i8, i8, i8, i8, i8, i8 }>14%struct.h4 = type<{ i16, i16, i16, i16 }>15%struct.w2 = type<{ i32, i32 }>16 17%struct.d2 = type<{ i64, i64 }>18%struct.misalign = type<{ i8, i64 }>19 20@b4v = dso_local global %struct.b4 <{ i8 1, i8 2, i8 3, i8 4 }>, align 421@h2v = dso_local global %struct.h2 <{ i16 1, i16 2 }>, align 422 23@b8v = dso_local global %struct.b8 <{ i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8 }>, align 824@h4v = dso_local global %struct.h4 <{ i16 1, i16 2, i16 3, i16 4 }>, align 825@w2v = dso_local global %struct.w2 <{ i32 1, i32 2 }>, align 826 27@d2v = dso_local global %struct.d2 <{ i64 1, i64 2 }>, align 1628@misalign_v = dso_local global %struct.misalign <{ i8 1, i64 2 }>, align 1629 30; CHECK-LABEL: test_b4:31; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha32; CHECK-DAG: lbz [[REG0_0:[0-9]+]], b4v@toc@l([[REGSTRUCT]])33; CHECK-DAG: lbz [[REG1_0:[0-9]+]], b4v@toc@l+1([[REGSTRUCT]])34; CHECK-DAG: lbz [[REG2_0:[0-9]+]], b4v@toc@l+2([[REGSTRUCT]])35; CHECK-DAG: lbz [[REG3_0:[0-9]+]], b4v@toc@l+3([[REGSTRUCT]])36; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 137; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 238; CHECK-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 339; CHECK-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 440; CHECK-DAG: stb [[REG0_1]], b4v@toc@l([[REGSTRUCT]])41; CHECK-DAG: stb [[REG1_1]], b4v@toc@l+1([[REGSTRUCT]])42; CHECK-DAG: stb [[REG2_1]], b4v@toc@l+2([[REGSTRUCT]])43; CHECK-DAG: stb [[REG3_1]], b4v@toc@l+3([[REGSTRUCT]])44 45define dso_local void @test_b4() nounwind {46entry:47 %0 = load i8, ptr @b4v, align 148 %inc0 = add nsw i8 %0, 149 store i8 %inc0, ptr @b4v, align 150 %1 = load i8, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 1), align 151 %inc1 = add nsw i8 %1, 252 store i8 %inc1, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 1), align 153 %2 = load i8, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 2), align 154 %inc2 = add nsw i8 %2, 355 store i8 %inc2, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 2), align 156 %3 = load i8, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 3), align 157 %inc3 = add nsw i8 %3, 458 store i8 %inc3, ptr getelementptr inbounds (%struct.b4, ptr @b4v, i32 0, i32 3), align 159 ret void60}61 62; CHECK-LABEL: test_h2:63; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha64; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])65; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])66; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 167; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 268; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])69; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])70 71define dso_local void @test_h2() nounwind {72entry:73 %0 = load i16, ptr @h2v, align 274 %inc0 = add nsw i16 %0, 175 store i16 %inc0, ptr @h2v, align 276 %1 = load i16, ptr getelementptr inbounds (%struct.h2, ptr @h2v, i32 0, i32 1), align 277 %inc1 = add nsw i16 %1, 278 store i16 %inc1, ptr getelementptr inbounds (%struct.h2, ptr @h2v, i32 0, i32 1), align 279 ret void80}81 82; CHECK-LABEL: test_h2_optsize:83; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha84; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])85; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])86; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 187; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 288; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])89; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])90define dso_local void @test_h2_optsize() optsize nounwind {91entry:92 %0 = load i16, ptr @h2v, align 293 %inc0 = add nsw i16 %0, 194 store i16 %inc0, ptr @h2v, align 295 %1 = load i16, ptr getelementptr inbounds (%struct.h2, ptr @h2v, i32 0, i32 1), align 296 %inc1 = add nsw i16 %1, 297 store i16 %inc1, ptr getelementptr inbounds (%struct.h2, ptr @h2v, i32 0, i32 1), align 298 ret void99}100 101; CHECK-LABEL: test_b8:102; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, b8v@toc@ha103; CHECK-DAG: lbz [[REG0_0:[0-9]+]], b8v@toc@l([[REGSTRUCT]])104; CHECK-DAG: lbz [[REG1_0:[0-9]+]], b8v@toc@l+1([[REGSTRUCT]])105; CHECK-DAG: lbz [[REG2_0:[0-9]+]], b8v@toc@l+2([[REGSTRUCT]])106; CHECK-DAG: lbz [[REG3_0:[0-9]+]], b8v@toc@l+3([[REGSTRUCT]])107; CHECK-DAG: lbz [[REG4_0:[0-9]+]], b8v@toc@l+4([[REGSTRUCT]])108; CHECK-DAG: lbz [[REG5_0:[0-9]+]], b8v@toc@l+5([[REGSTRUCT]])109; CHECK-DAG: lbz [[REG6_0:[0-9]+]], b8v@toc@l+6([[REGSTRUCT]])110; CHECK-DAG: lbz [[REG7_0:[0-9]+]], b8v@toc@l+7([[REGSTRUCT]])111; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1112; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2113; CHECK-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3114; CHECK-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4115; CHECK-DAG: addi [[REG4_1:[0-9]+]], [[REG4_0]], 5116; CHECK-DAG: addi [[REG5_1:[0-9]+]], [[REG5_0]], 6117; CHECK-DAG: addi [[REG6_1:[0-9]+]], [[REG6_0]], 7118; CHECK-DAG: addi [[REG7_1:[0-9]+]], [[REG7_0]], 8119; CHECK-DAG: stb [[REG0_1]], b8v@toc@l([[REGSTRUCT]])120; CHECK-DAG: stb [[REG1_1]], b8v@toc@l+1([[REGSTRUCT]])121; CHECK-DAG: stb [[REG2_1]], b8v@toc@l+2([[REGSTRUCT]])122; CHECK-DAG: stb [[REG3_1]], b8v@toc@l+3([[REGSTRUCT]])123; CHECK-DAG: stb [[REG4_1]], b8v@toc@l+4([[REGSTRUCT]])124; CHECK-DAG: stb [[REG5_1]], b8v@toc@l+5([[REGSTRUCT]])125; CHECK-DAG: stb [[REG6_1]], b8v@toc@l+6([[REGSTRUCT]])126; CHECK-DAG: stb [[REG7_1]], b8v@toc@l+7([[REGSTRUCT]])127 128define dso_local void @test_b8() nounwind {129entry:130 %0 = load i8, ptr @b8v, align 1131 %inc0 = add nsw i8 %0, 1132 store i8 %inc0, ptr @b8v, align 1133 %1 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 1), align 1134 %inc1 = add nsw i8 %1, 2135 store i8 %inc1, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 1), align 1136 %2 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 2), align 1137 %inc2 = add nsw i8 %2, 3138 store i8 %inc2, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 2), align 1139 %3 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 3), align 1140 %inc3 = add nsw i8 %3, 4141 store i8 %inc3, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 3), align 1142 %4 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 4), align 1143 %inc4 = add nsw i8 %4, 5144 store i8 %inc4, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 4), align 1145 %5 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 5), align 1146 %inc5 = add nsw i8 %5, 6147 store i8 %inc5, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 5), align 1148 %6 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 6), align 1149 %inc6 = add nsw i8 %6, 7150 store i8 %inc6, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 6), align 1151 %7 = load i8, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 7), align 1152 %inc7 = add nsw i8 %7, 8153 store i8 %inc7, ptr getelementptr inbounds (%struct.b8, ptr @b8v, i32 0, i32 7), align 1154 ret void155}156 157; CHECK-LABEL: test_h4:158; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, h4v@toc@ha159; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h4v@toc@l([[REGSTRUCT]])160; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h4v@toc@l+2([[REGSTRUCT]])161; CHECK-DAG: lhz [[REG2_0:[0-9]+]], h4v@toc@l+4([[REGSTRUCT]])162; CHECK-DAG: lhz [[REG3_0:[0-9]+]], h4v@toc@l+6([[REGSTRUCT]])163; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1164; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2165; CHECK-DAG: addi [[REG2_1:[0-9]+]], [[REG2_0]], 3166; CHECK-DAG: addi [[REG3_1:[0-9]+]], [[REG3_0]], 4167; CHECK-DAG: sth [[REG0_1]], h4v@toc@l([[REGSTRUCT]])168; CHECK-DAG: sth [[REG1_1]], h4v@toc@l+2([[REGSTRUCT]])169; CHECK-DAG: sth [[REG2_1]], h4v@toc@l+4([[REGSTRUCT]])170; CHECK-DAG: sth [[REG3_1]], h4v@toc@l+6([[REGSTRUCT]])171 172define dso_local void @test_h4() nounwind {173entry:174 %0 = load i16, ptr @h4v, align 2175 %inc0 = add nsw i16 %0, 1176 store i16 %inc0, ptr @h4v, align 2177 %1 = load i16, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 1), align 2178 %inc1 = add nsw i16 %1, 2179 store i16 %inc1, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 1), align 2180 %2 = load i16, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 2), align 2181 %inc2 = add nsw i16 %2, 3182 store i16 %inc2, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 2), align 2183 %3 = load i16, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 3), align 2184 %inc3 = add nsw i16 %3, 4185 store i16 %inc3, ptr getelementptr inbounds (%struct.h4, ptr @h4v, i32 0, i32 3), align 2186 ret void187}188 189; CHECK-LABEL: test_w2:190; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, w2v@toc@ha191; CHECK-DAG: lwz [[REG0_0:[0-9]+]], w2v@toc@l([[REGSTRUCT]])192; CHECK-DAG: lwz [[REG1_0:[0-9]+]], w2v@toc@l+4([[REGSTRUCT]])193; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1194; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2195; CHECK-DAG: stw [[REG0_1]], w2v@toc@l([[REGSTRUCT]])196; CHECK-DAG: stw [[REG1_1]], w2v@toc@l+4([[REGSTRUCT]])197 198define dso_local void @test_w2() nounwind {199entry:200 %0 = load i32, ptr @w2v, align 4201 %inc0 = add nsw i32 %0, 1202 store i32 %inc0, ptr @w2v, align 4203 %1 = load i32, ptr getelementptr inbounds (%struct.w2, ptr @w2v, i32 0, i32 1), align 4204 %inc1 = add nsw i32 %1, 2205 store i32 %inc1, ptr getelementptr inbounds (%struct.w2, ptr @w2v, i32 0, i32 1), align 4206 ret void207}208 209; CHECK-LABEL: test_d2:210; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha211; CHECK: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]])212; CHECK: addi [[BASEV:[0-9]+]], [[REGSTRUCT]], d2v@toc@l213; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1214; CHECK-DAG: ld [[REG1_0:[0-9]+]], 8([[BASEV]])215; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2216; CHECK-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]])217; CHECK-DAG: std [[REG1_1]], 8([[BASEV]])218 219define dso_local void @test_d2() nounwind {220entry:221 %0 = load i64, ptr @d2v, align 8222 %inc0 = add nsw i64 %0, 1223 store i64 %inc0, ptr @d2v, align 8224 %1 = load i64, ptr getelementptr inbounds (%struct.d2, ptr @d2v, i32 0, i32 1), align 8225 %inc1 = add nsw i64 %1, 2226 store i64 %inc1, ptr getelementptr inbounds (%struct.d2, ptr @d2v, i32 0, i32 1), align 8227 ret void228}229 230; CHECK-LABEL: test_singleuse:231; CHECK: addis [[REG:[0-9]+]], 2, d2v@toc@ha+8232; CHECK: ld 3, d2v@toc@l+8([[REG]])233define i64 @test_singleuse() nounwind {234entry:235 %0 = load i64, ptr getelementptr inbounds (%struct.d2, ptr @d2v, i32 0, i32 1), align 8236 ret i64 %0237}238 239; Make sure the optimization fails to fire if the symbol is aligned, but the offset is not.240; CHECK-LABEL: test_misalign241; CHECK: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v@toc@ha242; CHECK-DAG: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l243; CHECK-DAG: li [[OFFSET_REG:[0-9]+]], 1244; CHECK: ldx [[REG0_0:[0-9]+]], [[REGSTRUCT]], [[OFFSET_REG]]245; CHECK: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1246; CHECK: stdx [[REG0_1]], [[REGSTRUCT]], [[OFFSET_REG]]247define dso_local void @test_misalign() nounwind {248entry:249 %0 = load i64, ptr getelementptr inbounds (%struct.misalign, ptr @misalign_v, i32 0, i32 1), align 1250 %inc0 = add nsw i64 %0, 1251 store i64 %inc0, ptr getelementptr inbounds (%struct.misalign, ptr @misalign_v, i32 0, i32 1), align 1252 ret void253}254