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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-ibm-aix < %s | FileCheck %s3; RUN: llc -verify-machineinstrs -mcpu=future \4; RUN: -mtriple=powerpc64-ibm-aix < %s | FileCheck %s --check-prefix=CHECK-WACC5 6target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512"7 8define void @baz(i64 %arg) local_unnamed_addr #0 {9; CHECK-LABEL: baz:10; CHECK: # %bb.0: # %bb11; CHECK-NEXT: xxmfacc 012; CHECK-NEXT: xxmrgld 0, 0, 213; CHECK-NEXT: xxlxor 1, 1, 114; CHECK-NEXT: xvnegdp 2, 015; CHECK-NEXT: xvnegdp 0, 016; CHECK-NEXT: xvsubdp 2, 2, 117; CHECK-NEXT: xvsubdp 0, 0, 318; CHECK-NEXT: xvmuldp 2, 2, 119; CHECK-NEXT: xvmuldp 0, 0, 120; CHECK-NEXT: xvmaddadp 2, 1, 121; CHECK-NEXT: xvmaddadp 0, 1, 122; CHECK-NEXT: stxv 2, 0(3)23; CHECK-NEXT: stxv 0, 0(3)24; CHECK-NEXT: # implicit-def: $acc025; CHECK-NEXT: bc 12, 20, L..BB0_226; CHECK-NEXT: # %bb.1: # %bb1027; CHECK-NEXT: xvf64gerpp 0, 34, 028; CHECK-NEXT: L..BB0_2: # %bb1229; CHECK-NEXT: cmpdi 3, 030; CHECK-NEXT: L..BB0_3: # %bb1331; CHECK-NEXT: #32; CHECK-NEXT: bc 4, 2, L..BB0_333; CHECK-NEXT: # %bb.4: # %bb1434; CHECK-NEXT: xxmfacc 035; CHECK-NEXT: xxlxor 0, 0, 036; CHECK-NEXT: xxlxor 2, 2, 237; CHECK-NEXT: xvsubdp 1, 0, 138; CHECK-NEXT: xvmaddadp 2, 1, 239; CHECK-NEXT: xvadddp 0, 2, 040; CHECK-NEXT: xxswapd 0, 041; CHECK-NEXT: stxv 0, 0(3)42; CHECK-NEXT: blr43;44; CHECK-WACC-LABEL: baz:45; CHECK-WACC: # %bb.0: # %bb46; CHECK-WACC-NEXT: dmxxextfdmr512 34, 36, 0, 047; CHECK-WACC-NEXT: xxmrgld 1, 34, 3648; CHECK-WACC-NEXT: xxswapd 2, 149; CHECK-WACC-NEXT: xxlxor 0, 0, 050; CHECK-WACC-NEXT: xvnegdp 1, 151; CHECK-WACC-NEXT: xvnegdp 2, 252; CHECK-WACC-NEXT: xvsubdp 1, 1, 053; CHECK-WACC-NEXT: xvsubdp 2, 2, 3754; CHECK-WACC-NEXT: xvmuldp 1, 1, 055; CHECK-WACC-NEXT: xvmuldp 2, 2, 056; CHECK-WACC-NEXT: xvmaddadp 1, 0, 057; CHECK-WACC-NEXT: xvmaddadp 2, 0, 058; CHECK-WACC-NEXT: stxv 1, 0(3)59; CHECK-WACC-NEXT: stxv 2, 0(3)60; CHECK-WACC-NEXT: # implicit-def: $wacc061; CHECK-WACC-NEXT: bc 12, 20, L..BB0_262; CHECK-WACC-NEXT: # %bb.1: # %bb1063; CHECK-WACC-NEXT: xvf64gerpp 0, 34, 064; CHECK-WACC-NEXT: L..BB0_2: # %bb1265; CHECK-WACC-NEXT: cmpdi 3, 066; CHECK-WACC-NEXT: .align 467; CHECK-WACC-NEXT: L..BB0_3: # %bb1368; CHECK-WACC-NEXT: #69; CHECK-WACC-NEXT: bc 4, 2, L..BB0_370; CHECK-WACC-NEXT: # %bb.4: # %bb1471; CHECK-WACC-NEXT: dmxxextfdmr512 34, 36, 0, 072; CHECK-WACC-NEXT: xxlxor 0, 0, 073; CHECK-WACC-NEXT: xvsubdp 1, 0, 3574; CHECK-WACC-NEXT: xxlxor 2, 2, 275; CHECK-WACC-NEXT: xvmaddadp 2, 1, 276; CHECK-WACC-NEXT: xvadddp 0, 2, 077; CHECK-WACC-NEXT: xxswapd 0, 078; CHECK-WACC-NEXT: stxv 0, 0(3)79; CHECK-WACC-NEXT: blr80bb:81 %call = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> poison)82 %extractvalue = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 083 %extractvalue1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 284 %extractvalue2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call, 385 %bitcast = bitcast <16 x i8> %extractvalue to <2 x double>86 %bitcast3 = bitcast <16 x i8> %extractvalue1 to <2 x double>87 %shufflevector = shufflevector <2 x double> %bitcast, <2 x double> %bitcast3, <2 x i32> <i32 1, i32 3>88 %shufflevector4 = shufflevector <2 x double> %shufflevector, <2 x double> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 poison>89 %fneg = fneg <4 x double> %shufflevector490 %shufflevector5 = shufflevector <4 x double> %fneg, <4 x double> poison, <4 x i32> <i32 0, i32 5, i32 2, i32 7>91 %shufflevector6 = shufflevector <16 x i8> zeroinitializer, <16 x i8> %extractvalue2, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>92 %bitcast7 = bitcast <32 x i8> %shufflevector6 to <4 x double>93 %fsub = fsub <4 x double> %shufflevector5, %bitcast794 %shufflevector8 = shufflevector <4 x double> poison, <4 x double> %fsub, <4 x i32> <i32 0, i32 5, i32 2, i32 7>95 %fmul = fmul <4 x double> %shufflevector8, zeroinitializer96 %call9 = tail call <4 x double> @llvm.fmuladd.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x double> %fmul)97 %fadd = fadd <4 x double> %call9, zeroinitializer98 store <4 x double> %fadd, ptr poison, align 499 br i1 poison, label %bb10, label %bb12100 101bb10: ; preds = %bb102 %call11 = tail call <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1> poison, <256 x i1> poison, <16 x i8> poison)103 br label %bb12104 105bb12: ; preds = %bb10, %bb106 %phi = phi <512 x i1> [ poison, %bb ], [ %call11, %bb10 ]107 br label %bb13108 109bb13: ; preds = %bb13, %bb12110 %icmp = icmp eq i64 0, %arg111 br i1 %icmp, label %bb14, label %bb13112 113bb14: ; preds = %bb13114 %call15 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> poison)115 %extractvalue16 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call15, 1116 %call17 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %phi)117 %extractvalue18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %call17, 1118 %bitcast19 = bitcast <16 x i8> %extractvalue16 to <2 x double>119 %bitcast20 = bitcast <16 x i8> %extractvalue18 to <2 x double>120 %fsub21 = fsub <2 x double> zeroinitializer, %bitcast19121 %fadd22 = fadd <2 x double> zeroinitializer, %fsub21122 %fadd23 = fadd <2 x double> %fadd22, zeroinitializer123 %fsub24 = fsub <2 x double> zeroinitializer, %bitcast20124 %fadd25 = fadd <2 x double> zeroinitializer, %fsub24125 %fadd26 = fadd <2 x double> %fadd25, zeroinitializer126 %fadd27 = fadd <2 x double> %fadd26, zeroinitializer127 %call28 = tail call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %fadd27, <2 x double> zeroinitializer, <2 x double> zeroinitializer)128 %fadd29 = fadd <2 x double> zeroinitializer, %call28129 %shufflevector30 = shufflevector <2 x double> %fadd29, <2 x double> poison, <2 x i32> <i32 1, i32 0>130 store <2 x double> %shufflevector30, ptr poison, align 4131 ret void132}133 134; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)135declare <512 x i1> @llvm.ppc.mma.xxsetaccz() #1136 137; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)138declare <512 x i1> @llvm.ppc.mma.xvf64gerpp(<512 x i1>, <256 x i1>, <16 x i8>) #1139 140; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)141declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>) #1142 143; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)144declare double @llvm.fmuladd.f64(double, double, double) #2145 146; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)147declare <2 x double> @llvm.fmuladd.v2f64(<2 x double>, <2 x double>, <2 x double>) #2148 149; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)150declare <4 x double> @llvm.fmuladd.v4f64(<4 x double>, <4 x double>, <4 x double>) #2151 152attributes #0 = { "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+isa-v31-instructions,+mma,+paired-vector-memops,+pcrelative-memops,+power10-vector,+power8-vector,+power9-vector,+prefix-instrs,+quadword-atomics,+vsx,-aix-shared-lib-tls-model-opt,-aix-small-local-dynamic-tls,-aix-small-local-exec-tls,-htm,-privileged,-rop-protect,-spe" }153attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }154attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }155